JP2000071067A - Electric soldering iron with antistatic function - Google Patents
Electric soldering iron with antistatic functionInfo
- Publication number
- JP2000071067A JP2000071067A JP26093498A JP26093498A JP2000071067A JP 2000071067 A JP2000071067 A JP 2000071067A JP 26093498 A JP26093498 A JP 26093498A JP 26093498 A JP26093498 A JP 26093498A JP 2000071067 A JP2000071067 A JP 2000071067A
- Authority
- JP
- Japan
- Prior art keywords
- tip
- soldering iron
- electric soldering
- grounded
- iron
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Control Of Resistance Heating (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】この発明は、電気はんだごて
に係わる。特に、静電気による半導体部品の破壊防止を
目的とする電気はんだごてに係わるものである。[0001] The present invention relates to an electric soldering iron. In particular, the present invention relates to an electric soldering iron for preventing destruction of a semiconductor component due to static electricity.
【0002】電気はんだごての従来の技術を図2と図3
の構成図により説明する。FIGS. 2 and 3 show a conventional technique of an electric soldering iron.
The configuration will be described with reference to FIG.
【0003】図2は、従来技術によるはんだごての構成
図である。図2の電気はんだごては、こて先1が接地さ
れていないため、後述する図4の電圧波形7cのよう
に、こて先1にリーク電圧が発生する。MOS FET
等の耐電圧の低い半導体部品に、リーク電圧発生のこて
先を当接した場合、両者の電位差によって絶縁破壊が発
生し、半導体部品の破壊や特性の劣化等の障害を発生さ
せる場合がある。FIG. 2 is a configuration diagram of a conventional soldering iron. In the electric soldering iron of FIG. 2, since the tip 1 is not grounded, a leak voltage is generated at the tip 1 as shown in a voltage waveform 7c of FIG. MOS FET
When the tip of the leak voltage is brought into contact with a semiconductor component having a low withstand voltage, such as the above, dielectric breakdown may occur due to a potential difference between the two, which may cause failure such as breakdown of the semiconductor component or deterioration of characteristics. .
【0004】図3の電気はんだごては、こて先1が接地
線5で接地されている。そのため、図4の電圧波形7b
のように、こて先1のリーク電圧が放電されている。In the electric soldering iron shown in FIG. 3, a tip 1 is grounded by a ground wire 5. Therefore, the voltage waveform 7b of FIG.
As described above, the leak voltage of the tip 1 is discharged.
【0005】[0005]
【発明が解決しようとする課題】しかし、図3の電気は
んだごては、リーク電圧の発生には対策されているが、
静電気の発生には対策されていない。すなわち、帯電し
ているプリント基板に実装された半導体部品も帯電す
る。この状態で、こて先を半導体部品のリードと当接す
ると、両者の電位差によって異常電流が発生し、半導体
部品の破壊や特性の劣化等の障害を発生させる。However, the electric soldering iron shown in FIG. 3 is designed to prevent the occurrence of leakage voltage.
No measures are taken against the generation of static electricity. That is, the semiconductor components mounted on the charged printed circuit board are also charged. In this state, if the tip is brought into contact with the lead of the semiconductor component, an abnormal current is generated due to the potential difference between the two, causing troubles such as destruction of the semiconductor component and deterioration of characteristics.
【0006】この発明は、リーク電圧の発生を防ぎ、は
んだごてのこて先と半導体部品間の電位差により生ずる
異常電流を制限し、前述の課題を解決することを目的と
する。SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems by preventing the occurrence of a leak voltage, limiting an abnormal current caused by a potential difference between a soldering iron tip and a semiconductor component.
【0007】[0007]
【課題を解決させるための手段】この目的を達成するた
め、請求項1に係わる発明は、電気はんだごてのこて先
1を抵抗6を介し接地する。According to the first aspect of the present invention, an electric soldering iron tip is grounded via a resistor.
【0008】請求項2に係わる発明は、請求項1記載の
発明において、抵抗6がホルダー3に内蔵される。According to a second aspect of the present invention, in the first aspect, the resistor 6 is built in the holder 3.
【0009】請求項3に係わる発明は、請求項1及び2
の何れかの項記載の発明において、抵抗6は1MΩであ
る。The invention according to claim 3 is based on claims 1 and 2
In the invention described in any one of the above items, the resistance 6 is 1 MΩ.
【0010】[0010]
【発明の実施の形態】次に、この発明による電気はんだ
ごての実施の形態を、図面を参照して説明する。図1
は、本発明の一実施の形態による電気はんだごてを示す
構成図である。Next, an embodiment of an electric soldering iron according to the present invention will be described with reference to the drawings. FIG.
1 is a configuration diagram illustrating an electric soldering iron according to an embodiment of the present invention.
【0011】図1において、電気はんだごてのこて先1
を1MΩの抵抗6を介し接地する。このため、後述する
図4の電圧波形7aに示すようにリーク電圧の発生を防
ぐことができ、又、後述する図5の電圧波形8aのよう
に電荷の減衰時間を緩やかにすることができる。また、
本実施の形態では、1MΩの抵抗値を使用しているが、
異常電流を制限するための一例を示すものであって、実
際には、他の抵抗値でも良い。In FIG. 1, an electric soldering iron 1
Is grounded via a 1 MΩ resistor 6. Therefore, generation of a leak voltage can be prevented as shown in a voltage waveform 7a in FIG. 4 described later, and the decay time of the electric charge can be made slow like a voltage waveform 8a in FIG. 5 described later. Also,
In the present embodiment, a resistance value of 1 MΩ is used.
This is an example for limiting the abnormal current, and other resistance values may actually be used.
【0012】さらに、図1において、1MΩの抵抗6
は、ヒータ2による熱の影響を避けるため、ヒータ2と
接触させずに、ホルダー3内に収納する。Further, in FIG. 1, a 1MΩ resistor 6
Is stored in the holder 3 without contact with the heater 2 in order to avoid the influence of heat from the heater 2.
【0013】図4は、こて先と電源接地間の抵抗値が、
0Ω・1MΩ・∞Ω時におけるこて先のリーク電圧を表
す図である。図4において、こて先と接地間を1MΩの
抵抗で接続した電圧波形7aは、こて先が接地されてい
ない電圧波形7cと比較して、微少のリーク電圧が発生
する。しかし、そのリーク電圧を起因として半導体部品
が破壊されることはない。また、こて先1を接地した電
圧波形7bは、放電するため、リーク電圧は発生しな
い。FIG. 4 shows that the resistance between the tip and the power supply ground is
It is a figure showing the leak voltage of a tip at the time of 0 (ohm) * 1M (ohm) * (ohm). In FIG. 4, a voltage waveform 7a in which the tip and the ground are connected by a resistance of 1 MΩ has a smaller leak voltage than a voltage waveform 7c in which the tip is not grounded. However, the semiconductor component is not destroyed due to the leak voltage. Further, since the voltage waveform 7b having the tip 1 grounded is discharged, no leak voltage occurs.
【0014】また、図5は、こて先と電源接地間の抵抗
値が、0Ω・1MΩ・∞Ω時の電荷の減衰状態を説明す
る図である。図5において、電圧波形8aは、こて先1
と接地間を1MΩの抵抗で接続した波形であり、電圧波
形8bは、こて先1をこて先接地線5で接地した波形で
ある。電圧波形8aは単位時間あたりの電荷減衰量が小
さいため、異常電流が発生せず、半導体部品を破壊しな
い。しかし、電圧波形8bは単位時間あたりの電荷減衰
量が大きいため、半導体部品を破壊する異常電流が発生
する場合がある。また、電圧波形8cは、電荷の移動は
あるるものの、こて先1が接地されていないため、放電
しない。FIG. 5 is a diagram for explaining the charge decay state when the resistance value between the tip and the power supply ground is 0Ω / 1MΩ∞Ω. In FIG. 5, the voltage waveform 8a corresponds to the tip 1
A voltage waveform 8b is a waveform in which the tip 1 is grounded by the tip grounding wire 5 and a voltage waveform 8b. Since the voltage waveform 8a has a small amount of charge decay per unit time, no abnormal current is generated and the semiconductor component is not destroyed. However, since the voltage waveform 8b has a large amount of charge decay per unit time, an abnormal current that may destroy the semiconductor component may occur. The voltage waveform 8c does not discharge because the tip 1 is not grounded although the charge moves.
【0015】[0015]
【発明の効果】この発明によれば、こて先のリーク電圧
の発生を防ぎ、電荷減衰時間を制御するため、半導体部
品の破壊や特性の劣化等を防ぎ、また、1MΩの抵抗を
ホルダー内に収納するため、作業性を損なわず使用でき
るという効果がある。According to the present invention, in order to prevent the occurrence of a leak voltage at the tip and to control the charge decay time, it is possible to prevent the destruction of semiconductor components and the deterioration of characteristics, and to add a 1 MΩ resistor in the holder. In this case, there is an effect that it can be used without impairing the workability.
【図1】この発明による、電気はんだごての実施の形態
を示す構成図である。FIG. 1 is a configuration diagram showing an embodiment of an electric soldering iron according to the present invention.
【図2】従来技術による、こて先が接地されていない電
気はんだごての構成図である。FIG. 2 is a configuration diagram of an electric soldering iron having an ungrounded iron tip according to the related art.
【図3】従来技術による、こて先が接地されている電気
はんだごての構成図である。FIG. 3 is a configuration diagram of an electric soldering iron with a grounded tip according to the prior art.
【図4】こて先と電源接地間の抵抗値が、0Ω・1MΩ
・∞Ω時におけるこて先のリーク電圧を表す図である。FIG. 4 shows that the resistance value between the tip and the power supply ground is 0Ω · 1MΩ.
It is a figure showing the leak voltage of a tip at the time of ∞Ω.
【図5】こて先と電源接地間の抵抗値が、0Ω・1MΩ
・∞Ω時の電荷の減衰状態を説明する図である。FIG. 5 shows that the resistance value between the tip and the power supply ground is 0Ω · 1MΩ.
FIG. 4 is a diagram for explaining a state of charge decay at ΔΩ.
1 こて先 2 ヒーター 3 ホルダー 4 ヒーター電源線 5 こて先接地線 6 抵抗 7a 電圧波形 7b 電圧波形 7c 電圧波形 8a 電圧波形 8b 電圧波形 8c 電圧波形 DESCRIPTION OF SYMBOLS 1 Iron tip 2 Heater 3 Holder 4 Heater power supply line 5 Iron tip ground wire 6 Resistance 7a Voltage waveform 7b Voltage waveform 7c Voltage waveform 8a Voltage waveform 8b Voltage waveform 8c Voltage waveform
Claims (3)
地すること特徴とする帯電防止機能つき電気はんだご
て。1. An electric soldering iron with an antistatic function, wherein the tip of the electric soldering iron is grounded via a resistor.
とする請求項1記載の帯電防止機能つき電気はんだご
て。2. The electric soldering iron with an antistatic function according to claim 1, wherein said resistor is built in a holder.
請求項1又は2記載の帯電防止機能つき電気はんだご
て。3. The electric soldering iron with an antistatic function according to claim 1, wherein the resistance is 1 MΩ.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26093498A JP2000071067A (en) | 1998-08-31 | 1998-08-31 | Electric soldering iron with antistatic function |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26093498A JP2000071067A (en) | 1998-08-31 | 1998-08-31 | Electric soldering iron with antistatic function |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2000071067A true JP2000071067A (en) | 2000-03-07 |
Family
ID=17354812
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP26093498A Pending JP2000071067A (en) | 1998-08-31 | 1998-08-31 | Electric soldering iron with antistatic function |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2000071067A (en) |
-
1998
- 1998-08-31 JP JP26093498A patent/JP2000071067A/en active Pending
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