JP2000070531A - Microprocessor for game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an illegal action such as revising of a program by performing control so as not to operate a device without a certified program and data, concerning a microprocessor mounted on the control substrate of a pachinko machine or the like. SOLUTION: This microprocessor is composed of a user storage means storing an application program(AP) and certification code or the like stored in a prescribed area, a storage means with built-in chip storing a key code and a central processing unit(CPU) for comparing a certification code with the certification code read from the user storage means. When the certification codes are not coincident, the AP is executed together with a means for monitoring the execution address or execution time of the AP and when the program exceeds the area or after the lapse of prescribed program execution time, the operation of the device is stopped but when the certification codes are coincident, the AP is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an application program (equipment control program, Data), which is configured to prevent a program from being modified such that the semiconductor chip operates outside legal standards after the certification.

A gaming machine such as a pachinko machine is a product that cannot be sold unless the gaming machine has been certified and its type has been approved in accordance with the rules of the National Public Safety Commission based on the rules of the Customs Business Act. Things must also pass the security electronic communication technology association type test,
The ones that have received this type approval can be put on sale at pachinko halls and the like.

However, after receiving the type approval, the manufacturer or the hall may take various measures to remodel the microprocessor or modify the program to be used as an unauthorized gaming machine. The challenge today is to prevent post-certification modifications.

[0004]

2. Description of the Related Art A conventional game machine of this type has a circuit integrated with a microprocessor, and a device for continuously operating an electric accessory, a device for electrically controlling an electric accessory, etc. It is known to control the rotation of a rotating torso in a barrel-type game machine.In these circuits, those that pass the type test of the Security Electronics and Communication Technology Association release a victory ball to the user with a predetermined probability. It is configured to be. In the case of a gaming machine, it is obligatory to store programs and data in a predetermined address area.

[0005]

However, in the case of such a conventional circuit, if the control program or data in the circuit is modified after the type approval is obtained, it is difficult to distinguish the product from the approved product, and the external appearance alone is not enough. It is likely to be treated as a product. Therefore, there is a disadvantage that such fraud cannot be sufficiently prevented. Leaving such cheating unfair will result in disadvantages for the player, damage to the trust of the person handling the type-approved product, and may further reduce the significance of performing the type test. Accordingly, the present invention has been made in view of the above-described drawbacks of the related art, and provides a mechanism for making unauthorized modification in a gaming machine difficult, and also aims to prevent tampering of programs and data in a microprocessor in the gaming machine. The purpose is to have functions.

[0006]

That is, according to the present invention, there is provided a user storage device in which an application program stored in a predetermined area is stored, and a central control device for controlling a gaming machine based on the application program input from the user storage device. A processing unit (CPU); and an execution address monitoring unit for monitoring an execution address of the application program. The central processing unit activates a unit for monitoring an execution address of the application program. At this time, the execution address is monitored by a gaming machine microprocessor configured to stop the operation of the apparatus or reset the CPU at times, thereby eliminating illegal programs.

In the apparatus according to the present invention, Nippon Telegraph and Telephone is used as means for encrypting the authentication code C calculated from the application program stored in the user storage means with the predetermined encryption key code K given. Co., Ltd. developed an encryption device and an encryption method (commonly known as Feel patents (JP-A-62-109083, JP-A-63-204289,
It is preferable that the encryption method is calculated based on (1-147585)) and the encryption method is stored in the chip built-in storage means. The encryption method is not limited to these methods.

In order to prevent the modification of the application program in the user storage means after the authentication by decoding the authentication code and the key code, the key code and the authentication are stored in the user storage means and the chip built-in storage means as described below. If the codes are stored as follows, and the authentication codes are calculated from these and compared, the encryption becomes more complicated and cannot be easily decrypted. Authentication code stored in the user storage means, a plurality of key codes _{K 1, K 2, K 3} , ... K i, ... K those plurality of calculated respectively on the basis of _{n C 1, C 2, C} 3, ... C _i , ... C _n
Chip built-in storage unit key code is the plurality of key codes stored in the _{K 1, K 2, K 3} , ... K i, any one of the ... K _n
K is _i, authentication code user storage means for the central processing unit is compared to the authentication code C _i, which is calculated based on the key code K _i. Authentication code stored in the user storage means, a plurality of first primary key code _{K 1, K 2, K 3} , ... K i, ..., primary authorization code of the plurality which are respectively calculated based on K _n C ₁ , C ₂ , C ₃ ,
.., C _i ,..., C _n and the primary authentication codes C ₁ , C ₂ , C ₃ ,.
C _i, ..., C _n and second consists primary authentication code C _20, primary key code keycode of the plurality stored in the chip built-in storage unit which is calculated on the basis of the secondary key code K _{b
K 1, K 2, K 3} , ... K i, ..., is any one K _i and the secondary key code K _b of the K _n, the authentication code of the user storage means by the central processing unit compares and any of the primary authentication code C _i, which is calculated based on primary key code K _i, the secondary authentication code C _20. Authentication code stored in the user storage unit, an intermediate authentication code C ₀ calculated based on one of the intermediate key codes K ₀
And a plurality of primary key codes K ₁ , K ₂ , K ₃ ,... K _{i ,.}
Primary encrypted based on the authentication code _{C 1, C 2, C 3} , ...
C _i, ..., C _n and, said primary authentication code _{C 1, C 2, C 3} , ... C i,
..., the is calculated based on C _n and the second key code K _b 2
Consists of the following authentication code C _20, stored key code is an intermediate key code K ₀ in the chip built-in storage unit, the plurality of first primary key code _{K 1, K 2, K 3} , ... K i, ..., K and any one K _i of the _n, a second-order key code K _b, of any of the authentication code of the user storage means by the central processing unit is compared is calculated based on the primary key code K _i first Primary authentication code C
and _i, and secondary authentication code C _20.

[0009]

In the configuration described above, the microprocessor according to the present invention controls the device as follows by reading the application program (called AP) and the authentication code stored in the user storage means.
There are the following patterns of data stored in the user storage means. The program address area has regular and regular authentication codes. There is a format error in the data area of the user storage means. The program address area has no regular and no authentication code. The program address area is not regular and there is a regular authentication code. The program address area is not regular and there is no regular authentication code.

A part or all of the program management data and the authentication code in the user storage means are stored in the work storage means. If there is no error in the stored address area of the application program, check whether the authentication code is stored in the user storage means.If the authentication code is not recorded or if there is a format error in the address, Is stopped because it is not a proper device.

Next, when the authentication code C is provided, the same method as the normal type check (the authentication code calculation algorithm and the calculation key code K stored in the built-in chip storage means) is carried out from the read application program.
Calculates the authentication code c. Thereafter, the calculated authentication code c and the authentication code C read from the user storage means.
And confirm whether the read authentication code is legitimate (match). If the authentication code is confirmed to be legitimate, the application program is executed in a state where the execution address monitoring means is operated or not operated. When the authentication codes do not match, the application program is executed while the execution time monitoring means or the execution address monitoring means is operating.

Even when the application program is executed in a state where the authentication codes match, if the program attempts to execute beyond a predetermined address area while the execution address monitoring means is operating, the apparatus is stopped. Trap or reset the CPU,
Restart the device. If the application program is executed in a state where the authentication codes do not match, the operation of the apparatus is stopped when the application program attempts to control beyond the address area or after a predetermined time has elapsed from the start of execution of the application program. To trap. As described above, the contents of the program are confirmed for the cases such as-stored in the user storage means, and the apparatus is operated. Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

[0013]

FIG. 1 is a block diagram schematically showing an embodiment of a microprocessor according to the present invention. In the microprocessor according to the present invention, an application connected to a central processing unit 1 (CPU) via a system bus is provided. Illegal address trap generator 2 (hereinafter IAT) as a means for monitoring the execution address of a program
G), a boot watchdog timer 3 (hereinafter referred to as BWDT) as a means for monitoring the execution time of an application program, a control work RAM 4 as a system control work storage means, and a control work RAM 4 as an application program work storage means. Work RAM 5 for application programs, RAM size limiter 6 for limiting work RAM 5 for application programs corresponding to the application programs, CPU 1
Memory bank switch 7 for switching the input to the IATG2, BWDT3, control work RA
A mode controller 9 for outputting an execution mode (Md) to M4, the program memory bank switch 7 and the external bus gate 8;
ROM 10 as a built-in chip storage means storing a control program connected to the
A processor (chip) A in which the application program work RAM 5 is connected to the RAM size limiter 6; and an external bus of the chip A. An external ROM 14 as a user storage means for storing an application program connected to the gate 8, an authentication code of the application program, data for the application program, and the like.

FIG. 2 shows a specific connection between each means and the CPU 1 and a relation between the mode issued from the mode controller and the boot watchdog timer 3 for monitoring the execution time of the application program.
Is activated when a mode signal is transmitted from the mode controller 9 as shown in FIG. 4, the operation time of the application program is started to be counted by the counter 16, and the time given by the CPU 1 (predetermined time: 1-2)
Minute) and the time of the counter 16 are compared by the comparator 18, and when a predetermined time has elapsed, a stop signal is transmitted to the CPU 1.

Illegal address trap generator 2 for monitoring the execution address of the application program
Stores the upper and lower addresses of the address area given by the CPU 1 in the address registers 20 and 21 as shown in FIG. 5, and operates when a mode signal is transmitted from the mode controller 9. , CPU
The running address of the program No. 1 is constantly monitored by comparators 23 and 24.
Send a stop command to U1.

The built-in ROM 10 stores an algorithm for calculating the authentication code (expected value) of the application program in the type authentication and a key code for the calculation. Use the same one used for In addition, the ROM 1 is used to stop the operation depending on the presence or absence of the authentication code and the data relating to the address area of the application program read from the external ROM 14.
In 0, a control program is stored.

The program memory input / output device 12 mainly reads an application program memory stored in the external ROM 14 as an external I / O. In this embodiment, an authentication code,
RAM size data and resource management data are included. still,
When the ROM 14 as the user storage means is mounted on the chip A, these program memory input / output devices 12
Needless to say, it is not necessary to use the external bus gate 8 and the memory can be switched by the program memory bank switch 7.

In the configuration described above, in the microprocessor according to the present invention, the mode controller 9 outputs a mode in response to an instruction from the CPU 1 and the control work RAM.
4 in a usable state, an algorithm for calculating a model authentication code (expected value) from the built-in ROM 10, a key code (single or plural types), the presence or absence of the authentication code, and whether or not the application program address area is within the range Is loaded into the CPU 1.

Thereafter, the mode controller 9 switches the mode for the program memory bank switch 7 in accordance with an instruction from the CPU 1, and from the external ROM 14 via the external bus gate 8 and the input / output device 12, resource management data such as RAM size and the like. Read the authentication code, CPU1
Causes the mode controller 9 to switch the RAM size limiter 6 to a predetermined size. The user work data of the application program is the application program work RAM 5 and the authentication code is C
It is stored in the memory of PU1. Incidentally, 256 bytes are used for pachinko machines and 512 bytes are used for pachislot machines.

On the other hand, the CPU 1 reads all the data in the ROM 14, performs an address scan, and checks whether or not the address area of the program is larger than a predetermined area and whether or not there is authentication code data other than the resource management data. When the program address area is out of the specified range or when the authentication code is not stored, a stop command of the apparatus is automatically issued. Further, the CPU 1 confirms the data address area from the scanning result, and stores the select data.

When the check of the presence / absence of the resource management data and the authentication code data is cleared, the mode is switched, and all data including the application program stored in the external ROM 14 and the authentication code calculation stored in the internal ROM 10 are calculated. The algorithm and the key code stored in the built-in ROM 10 are read, and the authentication code of the application program is calculated.

The calculated authentication code and the external ROM 14
The authentication code read from the CPU is collated by the CPU 1, and when the collation results in a match, the mode of the apparatus is switched to the external bus 8, the switch 7, and the external ROM to shift to the application program execution mode. If the results of the comparison do not match, data relating to the upper limit and the lower limit are provided to the registers 20 and 21 of the address of the execution address IATG2, and then these are activated, and data relating to the execution time of the program is supplied to the BWDT 3 to the counter 16. To activate it and execute the application program.

Since this application program is incompatible with the authentication code, IATG2 and BW
The DT3 constantly monitors the execution state of the program. When the application program attempts to execute the program beyond the work area and when the application program attempts to execute the program for more than a set time, the stop command of the apparatus is transmitted to the CP.
Emitted for U1, the device is shut down. In the present embodiment, there is an unauthorized program that operates only occasionally beyond the address area even if the application program is properly authenticated. Such a program is an illegal program even though it is a legitimate program. Therefore, the address area scanned in advance in the transition to the application program is stored in the address registers 20 and 21 in the IATG.
2 is working.

The determination of the consistency of the authentication code by the microprocessor according to the present embodiment based on the input of the authentication code to the external ROM and the application program and the authentication code input to the external ROM is as shown in FIG. It is performed as shown in the block diagram. That is, the authentication code (security code) issuing machine B, the external ROM 1
4, the encryption program of the field 8 and the key code K for encryption are input to the issuing machine B in advance, and when the external ROM 14 is connected, the application program is scanned. While the authentication code C is calculated based on the key code K, the calculated authentication code C is written in the external ROM 14, and the inspected external ROM 14 is completed.

When the completed external ROM 14 is actually mounted on a game machine and operated, the processor (element) A
Connected to. When the external ROM 14 is connected, the processor A uses the same key code K and encryption program as the issuer B stored in the internal ROM 10 based on
The application program is scanned to calculate the authentication code c. Then, the authentication code C stored in the external ROM 14 is compared with the authentication code c calculated by the processor A, and when they match, the application program is executed, and when they do not match, the application program is stopped without executing the application program. . Note that the authentication code issuing system and the authentication code calculation / comparison system are not limited to those shown in FIG. 8, but are more difficult to decode if performed by the methods shown in FIGS. 9, 10, and 11. Become. The respective issuing systems and comparison systems will be described below.

FIG. 7 shows a second embodiment, in which an issuing machine B has a plurality of primary authentication key codes K ₁ , K ₂ ,
K ₃ , ... K _i , K _n and the encryption program are entered,
When the external ROM 14 is connected, the application programs are scanned based on the respective key codes to calculate the authentication codes C ₁ , C ₂ , C ₃ ,..., C _i , and C _n.
By writing to M14, the external ROM 14
Is completed. When this external ROM 14 is connected to the processor A, a predetermined key code is stored in the processor in advance.
K _i and the encrypted program is input, whether the key scans the application program based on the code K _i is calculated authentication code c _i, which is consistent with the stored authentication code C _i to i-th In the same manner as described above, the application program is executed if they match, and if not, the application program is stopped without executing the application program.

FIG. 8 shows a third embodiment, in which a plurality of primary authentication key codes K ₁ , K ₂ ,
K ₃ ,... K _i , K _n , the secondary authentication key code K _b and the encryption program are input, and when the external ROM 14 is connected, the application program is scanned based on the respective key codes to scan the authentication code C. _{1, C 2, C 3,} ... C i, to calculate the C _n, they write to the external ROM 14, the authentication code C ₁ written _{Additionally, C 2, C 3, ...} C i, while scanning the C _n, calculating a second-order authentication code C ₂₀ on the basis of the key code K _b, it inspected external ROM is completed by writing the secondary authentication code C ₂₀ to the outside ROM 14. The external ROM14 when connected to the processor A, one K _i of pre-primary authorization key code to the processor, the second
Next authentication key code K _b and are encrypted program is input, the secondary authentication key code K calculates a first-order authentication code c _i scans the application program on the basis of the primary authorization key code K _i External ROM 14 based on _b
Primary authentication code written in _{C 1, C 2, C 3} , ... C i, C n
Scanning the calculating the secondary authentication key code c ₂₀ in. The written i th primary authentication code c _i and written by comparing the secondary authentication code c ₂₀ and the calculated secondary authentication code C ₂₀ and the calculated first-order authentication code C _i If both match, the application program is executed and stopped at other times without execution.

FIG. 9 shows a fourth embodiment in which an issuing machine B calculates a plurality of primary intermediate key codes K ₀ and an intermediate authentication code C ₀ based on the intermediate key codes K _0. a program for, primary key code K ₁ for performing encryption of the calculated intermediate authentication code _{C 0, K 2, K 3} , ... K i, and K _n,
The calculated primary authentication codes C ₁ , C ₂ , C ₃ ,... C _i , C _n and the secondary authentication key code _Kb for scanning and encrypting are inputted. while initially scanning the application program when connecting to calculate the intermediate authentication code C _0, the intermediate authentication code calculated C ₀ and the primary authorization key code _{K 1, K 2, K 3} , ... K i, K n primary authentication and encryption on the basis of the code _{C 1, C 2, C 3} , ... C it, to calculate the C _n, primary authentication code C ₁ written in the external ROM 14 is written them into external ROM 14, .. C _i , C _n while scanning the C ₂ , C ₃ ,..., C _n , and calculating the authentication code C ₂₀ based on the secondary authentication key code _Kb and writing the same in the external ROM 14. This external ROM 14
The when connected to the processor A, are pre primary intermediate authentication key codes K _0, the primary authentication key code K _i and the secondary authentication key code K _b and encryption program input to the processor A, The application program is scanned based on the primary intermediate authentication key code K ₀ to calculate the primary authentication code c ₀ , and further encrypted based on the primary authentication key code K _i to obtain the primary authentication code c _i . calculate. Next, by scanning the primary authentication codes C ₁ , C ₂ , C ₃ ,... C _i , C _n written in the external ROM 14 based on the secondary authentication key code K _b , the secondary authentication code c ₂₀ is scanned. Is calculated. Only when the first authentication code and the second authentication code match, the application program is executed,
At other times, the program is stopped without executing the program.

The significance of the encryption shown in FIGS. 6 to 9 will be described. In FIG. 6 (first embodiment), there is one encryption key code, and based on this, the authentication code is encrypted by a predetermined algorithm, but when the key code of the processor is decrypted. It is necessary to change the key code, and in that case, it becomes necessary to change all the ROMs of the user. In FIG. 7 (second embodiment), there are a plurality (n) of encryption key codes, and an arbitrary key code is used for the processor. For this reason, even if one key code is decrypted, it does not mean that all key codes have been decrypted, and it is difficult to modify the program to match this. In FIG. 8 (third embodiment), all key codes are decrypted because the system is configured to encrypt using a plurality of key codes and calculate the secondary authentication code based on the primary authentication code. It is very difficult to change the program so that the authentication number matches the decrypted key code. However, encryption is performed n times in order to generate an authentication code in the issuing machine, and the encryption takes too much time. The one shown in FIG. 9 (fourth embodiment) is designed so as not to take too much time for the password, and the authentication code can be calculated in substantially the same time as in the first embodiment.
In addition, it becomes difficult to decode the key code and modify the program as in the second and third embodiments. Next, an algorithm (16 bits) for creating an authentication code will be briefly described.

(Authentication Code Creation Algorithm 1) As shown in FIG. 10, the 16-bit data of each address of the user area and the control area stored in the external ROM 14 are spread to data 8A _i , 8B _i of left and right 8 bits respectively. Then, as shown in FIG. 6, scanning is performed in order from the youngest address, and the immediately preceding authentication codes 8A " _{i- 1} and 8B" _i-1 (initial value: stored key code) are given, and the 8-bit data is stored. Authentication code 8
A ′ _i , 8B ′ _i are calculated. Further, the calculated 8-bit data (example 8A ′ _i ) is given as the key code to the calculated 8-bit data (example 8B ′ _i ), and the authentication code 8A ″ _i ,
8B " _i is calculated. The obtained authentication codes 8A" _i , 8B " _i
Are sequentially spread using the 8-bit data 8A _{i + 1} and 8B _{i + 1} scanned as key codes for data diffusion as described above, and finally calculated left and right 8-bit data 8A " _n ,
8B " _n is fused to form a final authentication code as 16-bit data.

[0031] (Authentication Code Algorithm 2) spreads the data of 16 bits of each address of the user area and the control area stored in an external ROM14 left and right 8 bits each of data 8A _i, the 8B _i as shown in FIG. 12 , calculated authentication code 8'a _i subjected to field 8 in a state that gave scanned from younger by the address in the order key code K, the 8'B _i, 8A _{i + 1} of the next address to these, 8B _{i + 1} Exclusive OR (E
X-OR), and spread on the field 8 with the key code K again given, and the authentication code 8'A _{i + 1} ,
The authentication code is obtained by repeating the operation of calculating 8'B _{i + 1}
8'A _n and 8'B _{n are} calculated. Finally over the field 8 8'a _n, the values for each 8'a _n or 8'b _n obtained in 8'b _n as a key code to obtain the authentication code _{8 "A n, 8" B} n.

[0032] (Authentication Code algorithm 3 (8-bit)) 8-bit algorithm of the authentication code, as shown in FIG. 11, inputs data 8 ₁ 8 bits while the initial value 0 through EX-OR circuit while it is given a predetermined key code after diffusing 8 _'1 and calculates the authentication code 8 _"1. the resulting input to EX-OR circuit for successive data spreading the authentication code, the authentication code The calculated and finally obtained authentication code 8 " _n is used as the authentication code.

(Encryption Algorithm) As shown in FIGS. 12 and 13, the encryption algorithm is applied to a field 8 with a predetermined key code K given to data to be encrypted, for example, 8A _n , 8B _n , and an authentication code 8 ′. A _n , 8′B _n are calculated, and these data 8′A _n , 8′B _n are used as key codes of 8′A _n or 8′B _n.
And then apply it to field 8 and authenticate code 8 "
A _n , 8 "B _n is obtained.

As described above, the recognition code calculated by the type approval is such that the data at each address is sequentially encrypted and the encryption code of the final data is used as the authentication code. Even if they match, if there is an error in one location, the calculated authentication code will be different, making it very difficult to modify the program.

[0035]

As described above, since the microprocessor for a gaming machine according to the present invention is configured to constantly monitor the address area even if it is a regular one, it is possible to eliminate impropriety due to omission of checks.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically illustrating a microprocessor according to the present invention.

FIG. 2 is a block diagram showing an operation relationship of the microprocessor.

FIG. 3 is a flowchart showing the operation of the microprocessor.

FIG. 4 is a block diagram illustrating a configuration example of an AP execution time monitor;

FIG. 5 is a block diagram illustrating a configuration example of an AP execution address monitor.

FIG. 6 is a schematic diagram showing encryption of an external ROM by an issuer and operation of a processor when judging the suitability of an AP.

FIG. 7 is a schematic diagram of a second embodiment showing encryption of an external ROM by an issuer and operation of a processor when judging the suitability of an AP.

FIG. 8 is a schematic diagram of a third embodiment showing encryption of an external ROM by an issuer and operation of a processor when judging the suitability of an AP.

FIG. 9 is a schematic diagram of a fourth embodiment showing encryption of an external ROM by an issuer and operation of a processor when judging the suitability of an AP.

FIG. 10 is a block diagram illustrating Algorithm 1 for calculating an authentication code of 16-bit data.

FIG. 11 is a block diagram illustrating Algorithm 2 for calculating an authentication code of 8-bit data.

FIG. 12 is a block diagram illustrating an algorithm 3 for calculating an authentication code of 16-bit data.

FIG. 13 is a block diagram illustrating an encryption algorithm for 16-bit data.

[Explanation of symbols]

 Reference Signs List 1 CPU 2 AP execution address monitor (IATG) 3 AP execution time monitor (BWDT) 4 Work RAM for control 5 Work RAM for AP 6 RAM size limiter 7 Program memory bank switch 8 External bus gate 9 Mode controller 10 Built-in ROM 12 Program memory input / output device 14 External ROM 16 Counter 18 Comparator 20, 21 Address register 23, 24 Comparator

Claims (1)

[Claims] 1. A user storage unit storing an application program stored in a predetermined area, and a central processing unit (C) controlling a gaming machine based on the application program input from the user storage unit.
PU), and execution address monitoring means for monitoring the execution address of the application program, wherein the central processing unit activates means for monitoring the execution address of the application program, and when the program exceeds a predetermined area, the CPU of the apparatus is activated. A microprocessor for a gaming machine configured to stop operation or reset a CPU.