JP2000068511A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high performance transistor, wherein there is no damage at channel part in a MOSFET, the very shallow junction can be formed, the short-channel effect is suppressed, the leakage current is less and the parasitic resistance of a diffused layer is less, and a manufacturing method thereof. SOLUTION: A gate oxide film 103 and a gate electrode 104, wherein an upper part and a side wall are covered with an oxide film 105, are formed on a semiconductor substrate 101 wherein an element separating region 102 and an active resion are formed. The surface of the active region without an electrode is exposed. A poly-Si film 106 is deposited thereon. The Si film is etched back, and the oxide film of the gate-electrode upper part is exposed. The Si film is made to remain through the side-wall oxide film around the electrode. The surface of the active region is covered with the Si film. Then, the Si film is patterned with the element separating region and separated to the regions that become the source and drain regions. After impurity ions are implanted into the Si film so as not to reach the substrate, the impurities are diffused into the semiconductor substrate from the Si film, and the source and drain regions including the patterned Si are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a MOS FET.

[0002]

2. Description of the Related Art As a conventional method of manufacturing a silicide transistor, there is a manufacturing method as shown in FIGS. As shown in FIG. 3A, a step of depositing a polycrystalline silicon film 203 on a semiconductor substrate 201 having a field oxide film 202 formed in a predetermined region is performed, and as shown in FIG. Oxide film 20 on silicon film 203
After the formation of the gate electrode 4, the oxide film 204 and the polycrystalline silicon film 203 in the region to be the channel region of the transistor are etched by RIE until the silicon substrate is exposed, and as shown in FIG. Oxide film 2
05, forming a gate electrode 206 and doping a high concentration impurity ion of a conductivity type opposite to that of the semiconductor substrate by an ion implantation method, and as shown in FIG. The source / drain region 208 and the gate electrode 20 are self-aligned by (RTA).
After forming the titanium silicide layer 207 by silicidation of the six surfaces, a step of selectively removing unreacted Ti is provided. (Eg, M. Shimizu et al., Symposium
on VLSI Technology Digest of Technical Pap
ers, p11 (1988))

[0003]

SUMMARY OF THE INVENTION Conventional MOS FET
In the step of etching the oxide film in the region to be the channel region of the transistor and the polycrystalline silicon film until the silicon substrate is exposed by RIE, the silicon substrate is damaged by RIE, Since the portions A and B in FIG. 3D have steep acute angles, there is a problem that electrolytic concentration occurs and transistor characteristics deteriorate. Further, since the impurity diffusion layer is formed before performing the silicidation reaction (before depositing the Ti metal), it is difficult to control the silicidation reaction due to the influence of impurities and the effect of the grains of polycrystalline silicon. There is a problem that the TiSi ₂ C54 crystal cannot be formed stably and the resistance increases.

[0004]

In order to solve the above problems, in a transistor forming step of a semiconductor device, a step of forming a gate insulating film on a semiconductor substrate on which an element isolation region and an active region are formed; Forming a gate electrode having an upper portion and a side wall portion covered with the insulating film on the insulating film, exposing a surface of the active region where the gate electrode does not exist, and depositing a silicon film so as to directly contact the active region; Step and immediately after depositing the silicon film, the silicon film is etched back to expose the insulating film on the gate electrode, and to leave the silicon film at least around the gate electrode via the gate electrode sidewall insulating film. And a step of covering the surface of the active region with the remaining silicon film, and patterning the silicon film on the element isolation region, Separating impurity ions into the patterned silicon film so as not to reach the semiconductor substrate, and implanting the impurity ions into the patterned silicon film so as not to reach the semiconductor substrate. Forming a source / drain region including a patterned silicon film by diffusing an impurity into the semiconductor substrate.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device and a method of manufacturing the same according to the present invention will be described in detail with reference to examples. FIG. 1 (a)
2 (c) and 2 (d) to 2 (e) are step-by-step cross-sectional views of the transistor of the present invention.

First, as shown in FIG. 1A, a field oxide film 102 and a gate oxide film 10 are formed on a semiconductor substrate 101 (a P-type semiconductor substrate in this embodiment) by a known method.
3. A gate electrode 104 having a two-layer structure of a polycrystalline silicon film and a tungsten silicide film thereon is formed, and an oxide film 105 covering the top and side walls of the gate electrode is formed.

Next, as shown in FIG. 1B, after depositing the polycrystalline silicon film 106, it is etched back by anisotropic etching until the upper portion of the gate electrode is exposed.

Next, after patterning the polycrystalline silicon into a desired pattern (to separate an active region of an adjacent transistor on a field oxide film),
As shown in FIG. 1C, the refractory metal film (in this embodiment,
A titanium film 107) is deposited.

Next, a first RTA process is performed at 625 ° C. for about 20 seconds in, for example, a nitrogen atmosphere to form a metastable titanium silicide layer 108. Fig. 2
(D) is obtained.

Next, 95% or more of the dose amount of impurity ions (arsenic ions in this embodiment) of the opposite conductivity type to the substrate is
After injecting a dose of about 5E15 / cm ² into the titanium silicide film 108 at an energy such as to be implanted into the titanium silicide film 108, for example, in this embodiment, at an implantation energy of about 35 Kev, 2 is performed to change the titanium silicide film 108 into a stable TiSi ₂ C 54 crystal structure.

Next, as shown in FIG. 2E, a source / drain region 110 reaching the semiconductor substrate 101 is formed by heat treatment at 900 ° C. for about 15 minutes after the interlayer insulating film 109 is deposited.

(Embodiment 2) The method of forming a silicide layer of the present invention is not limited to the first embodiment.

As in the first embodiment, the polycrystalline silicon film 1
After patterning No. 06 into a desired pattern, high melting point metal ions, for example, Ti ions are implanted into the polycrystalline silicon film 106 by an ion implantation method.
06 is made amorphous. Next, a high melting point metal film made of the same metal as the above high melting point metal, for example, a Ti film in this embodiment is deposited. Next, a first RTA process is performed in a nitrogen atmosphere, for example, at 625 ° C. for about 20 seconds to cause the Ti in the polycrystalline silicon film 106 and the Ti film and silicon in the polycrystalline silicon film to react with each other. Titanium silicide layer 1
08, and unreacted titanium metal is removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide solution to obtain FIG. 2 (d). Thereafter, a desired transistor element is formed through the same steps as in the first embodiment.

In the first and second embodiments, an amorphous silicon film may be used instead of the polycrystalline silicon film 106. When an amorphous silicon film is used, there is an advantage that a silicidation reaction occurs uniformly because there is no grain unlike a polycrystalline silicon film.

The high melting point metal material for forming the silicide layer of the present invention is not limited to titanium metal. C
o, Ni, Zr, V, and Hf metals may be used.

[0016]

As is clear from the above, according to the present invention, after forming a gate oxide film and a gate electrode in a transistor forming step, a polycrystalline silicon film is deposited and separated in a self-aligned manner by etch back. Since the stacked diffusion layer regions (source and drain regions) are formed, there is no damage to the channel portion as in the conventional example of FIG. Further, since impurities are diffused from the silicide layer formed above the channel portion, a very shallow junction can be formed, and the short channel effect of the transistor can be suppressed. Further, since the silicide region does not reach the semiconductor substrate, the leakage current is small.
Furthermore, since a very resistant silicide layer is formed, and it is not necessary to provide a contact region on the active region, the diffusion layer area (active region) can be designed to be very small, so that the parasitic resistance of the diffusion layer can be reduced. Thus, the speed of the transistor can be improved.

[Brief description of the drawings]

1A to 1C are cross-sectional views in the order of steps in an embodiment of the present invention.
It is.

FIGS. 2A to 2E are sectional views in the order of steps of an embodiment of the present invention.
It is.

3A to 3C are cross-sectional views in the order of steps of a conventional transistor.
(D).

[Explanation of symbols]

 101, 201 semiconductor substrate 102, 202 field oxide film 203 polycrystalline silicon film 204 oxide film 103, 205 gate oxide film 104, 206 gate electrode 105 oxide film 106 polycrystalline silicon film 107 Ti film 108, 207 Ti silicide film 109 interlayer insulation Film 110, 208 Source and drain regions

Claims (1)

[Claims] In a transistor forming step of a semiconductor device, a semiconductor substrate on which an element isolation region and an active region are formed,
Forming a gate insulating film, forming a gate electrode having an upper portion and a side wall portion covered with an insulating film on the gate insulating film, and exposing a surface of an active region where no gate electrode is present; Depositing a silicon film so as to be in direct contact with the region; etching the silicon film immediately after depositing the silicon film to expose an insulating film above the gate electrode; and forming a gate electrode at least around the gate electrode. Leaving the silicon film through the sidewall insulating film, and covering the active region surface with the remaining silicon film; patterning the silicon film on the element isolation region;
A step of separating into a region to be a source region and a drain region; a step of injecting impurity ions into the patterned silicon film so as not to reach a semiconductor substrate; Forming a source / drain region including a patterned silicon film by diffusing an impurity into a semiconductor substrate.