JP2000068171A - Semiconductor wafer and its manufacture - Google Patents

Semiconductor wafer and its manufacture

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Publication number
JP2000068171A
JP2000068171A JP10232484A JP23248498A JP2000068171A JP 2000068171 A JP2000068171 A JP 2000068171A JP 10232484 A JP10232484 A JP 10232484A JP 23248498 A JP23248498 A JP 23248498A JP 2000068171 A JP2000068171 A JP 2000068171A
Authority
JP
Japan
Prior art keywords
wafer
orientation flat
flat portion
orientation
chamfering
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10232484A
Other languages
Japanese (ja)
Other versions
JP4449088B2 (en
Inventor
Hideki Kurita
英樹 栗田
Kenji Suzuki
健二 鈴木
Junichi Shinohara
順一 篠原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Eneos Corp
Original Assignee
Japan Energy Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Japan Energy Corp filed Critical Japan Energy Corp
Priority to JP23248498A priority Critical patent/JP4449088B2/en
Publication of JP2000068171A publication Critical patent/JP2000068171A/en
Application granted granted Critical
Publication of JP4449088B2 publication Critical patent/JP4449088B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To make easy and accurate the angularly aligning optical work of a device creating process, by applying no chamfering to the orientation-flat portion of a wafer to machine only its side surface, and by making its side surface orthogonal to the top and rear surfaces of the wafer. SOLUTION: In the chamfering process of a semiconductor-wafer manufacturing process, machining only the side surface of the orientation-flat portion of a wafer, no chamfering is applied to the orientation-flat portion to make its side surface orthogonal to the top and rear surfaces of the wafer. Also, applying chamferings to the outer peripheral side surface of the wafer wherefrom the one of the orientation-flat portion is excluded, its side surface and its top and rear surfaces are connected continuously by curves. In this case, the machining means such one as a grinding other than a cleavage. Also, in the machining, a regrinding, chemical etching, or the like after performing the machining is included too. As result, facilitating the focussing of a microscopy on the ridge formed out of the side and top surfaces of the orientation-flat portion, its angularly aligning accuracy is improved.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は円形の半導体ウエハ
ーに関し、特には、オリエンテーションフラット部を有
する円形半導体ウエハー及びその製造方法に関するもの
である。
The present invention relates to a circular semiconductor wafer, and more particularly, to a circular semiconductor wafer having an orientation flat portion and a method of manufacturing the same.

【0002】[0002]

【従来の技術】円形半導体ウエハーは通常図1のような
工程で製造される。
2. Description of the Related Art A circular semiconductor wafer is usually manufactured by a process as shown in FIG.

【0003】ウエハーの外周部には、その結晶方位を示
すためにオリエンテーションフラットと呼ばれる直線部
分がもうけられる。このオリエンテーションフラットは
図1の円筒研削(2)、面取り(4)工程において形成され
る。または他の方法として劈開により形成する方法もあ
る。このオリエンテーションフラットは、ウエハー上に
デバイスを作製する際、特定の結晶方位に対する角度合
わせの基準として用いられるため、指定された結晶方位
に対してできるだけ正確につけられることが望ましい。
デバイス作製時の角度合わせの方法として、機械的な突
き当てによる方法と、光学的な方法があるが、後者につ
いてはウエハーの表面からオリエンテーションフラット
部を顕微鏡で観察し、オリエンテーションフラットに焦
点を合わせこれを基準に角度合わせを行う方法である。
また、そのほかに光学式センサーでオリエンテーション
フラットの位置を検知し、角度をあわせる方法もある。
一般に、このような円形ウエハーにおいては、取扱い時
の外周部のカケ、ワレを防止するため、オリエンテーシ
ョンフラットを含む外周側面部に一様に面取り加工が施
され、表裏面と滑らかな曲線で結ばれるようになってい
る。
[0003] A linear portion called an orientation flat is provided on the outer peripheral portion of the wafer to indicate its crystal orientation. This orientation flat is formed in the cylindrical grinding (2) and chamfering (4) steps of FIG. Alternatively, as another method, there is a method of forming by cleavage. Since the orientation flat is used as a reference for angle adjustment with respect to a specific crystal orientation when a device is formed on a wafer, it is desirable that the orientation flat be as accurate as possible with respect to a specified crystal orientation.
There are two methods for adjusting the angle during device fabrication: mechanical abutment and optical methods.The latter method involves observing the orientation flat from the wafer surface with a microscope and focusing on the orientation flat. This is a method of adjusting the angle based on the reference.
In addition, there is a method of detecting the position of the orientation flat with an optical sensor and adjusting the angle.
Generally, in such a circular wafer, in order to prevent chipping and cracking of the outer peripheral portion during handling, the outer peripheral side surface portion including the orientation flat is uniformly chamfered and connected to the front and back surfaces with a smooth curve. It has become.

【0004】[0004]

【発明が解決しようとする課題】従来技術においては、
特に光学的な方法で角度合わせをする場合、例えば顕微
鏡による方法ではオリエンテーションフラット部の断面
形状が図2のように曲線になっているため、図3に示す
様に表面からみた状態においてオリエンテーションフラ
ット部で顕微鏡観察像の焦点をあわせることが困難であ
り、角度合わせの精度を悪くしていた。
In the prior art,
In particular, when the angle is adjusted by an optical method, for example, in a method using a microscope, since the cross-sectional shape of the orientation flat portion is curved as shown in FIG. 2, the orientation flat portion is viewed from the surface as shown in FIG. However, it was difficult to focus the microscope observation image, and the accuracy of the angle adjustment was deteriorated.

【0005】また、光学式センサーを用いて角度合わせ
をする場合にも、オリエンテーションフラット部側面と
ウエハー表面がなす曲線部分で光が反射したり回り込ん
だりするため、角度合わせの精度に悪影響を与えること
があった。これに対し、例えば(100)面の表面を有す
るIII−V族化合物半導体では、[011]方向を示すオリ
エンテーションフラットを劈開により形成すれば、オリ
エンテーションフラット部の側面と表面とを直角にし、
光学的な角度合わせが容易なウエハーを作製することが
可能である。しかし、この劈開による方法では、ウエハ
ー1枚1枚を手作業で処理する必要があり、非常に手間
がかかる。また、オリエンテーションフラットの長さを
正確に制御することが難しく、さらに劈開のためにオリ
エンテーションフラットの一端につけたキズが残存する
といった問題があった。
[0005] In addition, when an angle is adjusted using an optical sensor, light is reflected or wrapped around a curved portion formed by the side surface of the orientation flat and the wafer surface, which adversely affects the accuracy of the angle adjustment. There was something. On the other hand, for example, in a III-V group compound semiconductor having a surface of the (100) plane, if an orientation flat indicating the [011] direction is formed by cleavage, the side surface and the surface of the orientation flat portion are perpendicular to each other,
A wafer whose optical angle can be easily adjusted can be manufactured. However, in this cleavage method, it is necessary to manually process each wafer one by one, which is very troublesome. In addition, it is difficult to accurately control the length of the orientation flat, and further, there is a problem that a flaw at one end of the orientation flat remains for cleavage.

【0006】本発明は上記の問題点を解決し、光学的な
角度合わせが正確にできるウエハー、及びそれを容易に
製造する方法を提供することを課題とした。
SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems and to provide a wafer capable of accurately adjusting an optical angle and a method of easily manufacturing the wafer.

【0007】[0007]

【課題を解決するための手段及び作用】本発明者は鋭意
研究を行った結果、オリエンテーションフラット部には
面取りを施さないことによって上記の課題を解決するこ
とが可能であることを見いだした。
As a result of intensive studies, the present inventor has found that the above-mentioned problems can be solved by not chamfering the orientation flat portion.

【0008】本発明は、この知見に基づき、 1.平坦な表裏面を有する円形ウエハーにおいて、オリ
エンテーションフラット部を除く外周側面部については
面取り加工を施し表裏面と滑らかな曲線で連続させ、オ
リエンテーションフラット部には面取りを施さず側面の
みを機械加工することにより表裏面と直交したオリエン
テーションフラット部側面を有することを特徴とする半
導体ウエハー
The present invention has been made based on this finding. For circular wafers with flat front and back surfaces, chamfering is applied to the outer peripheral side surface except for the orientation flat portion to make it smooth with the front and back surfaces, and only the side surface is machined without chamfering the orientation flat portion. Semiconductor wafer having an orientation flat portion side surface orthogonal to the front and back surfaces by means of

【0009】2.平坦な表裏面を有する円形ウエハーに
おいて、オリエンテーションフラット部を除く外周側面
部については面取り加工を施し表裏面と滑らかな曲線で
連続させ、オリエンテーションフラット部には面取りを
施さず側面のみを機械加工することにより表裏面と直交
させるようにしたことを特徴とする半導体ウエハーの製
造方法を提供するものである。
[0009] 2. For circular wafers with flat front and back surfaces, chamfering is applied to the outer peripheral side surface except for the orientation flat portion to make it smooth with the front and back surfaces, and only the side surface is machined without chamfering the orientation flat portion. And a method for manufacturing a semiconductor wafer characterized by being perpendicular to the front and back surfaces.

【0010】[0010]

【発明の実施の形態】本発明では、図1に示した半導体
ウエハーの製造工程のうち面取り工程(4)において図4
に示した様にオリエンテーションフラット部は側面のみ
機械加工し、面取りを施さず、側面と表面が直交するよ
うにする。
DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, in the chamfering step (4) of the manufacturing process of the semiconductor wafer shown in FIG.
As shown in (2), the orientation flat portion is machined only on the side surface, and is not chamfered so that the side surface and the surface are orthogonal.

【0011】また、オリエンテーションフラットを除く
外周側面には面取りを施し、側面と表面が曲線で連続す
るようにする。面取り部分の大きさは、チッピングを防
ぐという目的から、ウエハー上部または下部から見た場
合の長さとして75μm以上とすることが好ましい。
In addition, the outer peripheral side surface excluding the orientation flat is chamfered so that the side surface and the surface are continuously curved. For the purpose of preventing chipping, the size of the chamfered portion is preferably 75 μm or more when viewed from above or below the wafer.

【0012】なお、ここで言う機械加工とは、劈開以外
の研削加工などの機械的な加工を意味するものである。
また、機械加工を行った後に、さらに研磨あるいは化学
エッチング等を施すことを妨げるものではない。
Here, the mechanical processing means mechanical processing such as grinding other than cleavage.
Further, it does not prevent further polishing or chemical etching after the mechanical processing.

【0013】その結果、オリエンテーションフラット部
側面と表裏面とが直交するため、デバイス作製時顕微鏡
でオリエンテーションフラットの角度合わせを行う際、
オリエンテーションフラット側面と表面がなす稜線に容
易に焦点が合わせられ、角度合わせの精度を向上させる
ことができる。また、光学式センサーによる方法でも、
不必要な光の反射、回り込みがなくなり、角度合わせの
精度が向上する。さらに、劈開による方法に比べ手間が
かからず、オリエンテーションフラット長さ精度が向上
し、もちろん劈開によるキズも残らない。
As a result, since the side surface of the orientation flat portion and the front and back surfaces are perpendicular to each other, when the angle of the orientation flat is adjusted with a microscope during device fabrication,
The ridge formed by the orientation flat side surface and the surface is easily focused, and the accuracy of the angle adjustment can be improved. Also, with the method using an optical sensor,
Unnecessary light reflection and wraparound are eliminated, and the accuracy of angle adjustment is improved. Further, compared to the cleavage method, the method is less troublesome, the accuracy of the orientation flat length is improved, and, of course, no scratch due to cleavage is left.

【0014】[0014]

【実施例及び比較例】以下に本発明の半導体ウエハー及
びその製造方法を2“InPウエハーに適用した実施例
を説明する。はじめに、LEC(Liquid Encapsulated Czoc
hralski)法によりn型InP単結晶を(100)方向に成
長させた。この単結晶を2“より若干大きい直径の円柱
状にし、さらに[011]方向にオリエンテーションフラ
ットに当たる平坦面を形成した。これを表面が(100)
面になるようにスライシングし、ウエハーを切り出し
た。次に面取り加工において、まず直径が正確に50.
8mmになるように外周側面を研削した後、オリエンテー
ションフラットを除く部分については、側面と表面の接
する角の部分を曲線状になるよう研削した。図4はこの
様な面取り加工により得られたウエハーの形状を示した
ものである。また、図5は面取り工程に投入する前のウ
エハーの形状を示したものである。
EXAMPLES AND COMPARATIVE EXAMPLES The following describes examples in which the semiconductor wafer of the present invention and its manufacturing method are applied to a 2 "InP wafer. First, the LEC (Liquid Encapsulated Czoc) is used.
An n-type InP single crystal was grown in the (100) direction by the (hralski) method. This single crystal was formed into a cylindrical shape having a diameter slightly larger than 2 ", and a flat surface corresponding to an orientation flat was formed in the [011] direction.
Slicing was performed so as to form a surface, and a wafer was cut out. Next, in the chamfering process, first, the diameter is exactly 50.
After grinding the outer peripheral side surface to 8 mm, the portion excluding the orientation flat was ground so that the corner portion where the side surface and the surface contact was curved. FIG. 4 shows the shape of a wafer obtained by such chamfering. FIG. 5 shows the shape of the wafer before it is put into the chamfering step.

【0015】なお、このような加工は倣い方式の面取り
機では不可能であるため、数値制御機構を有する面取り
加工機を使用した。また、この際面取り加工前のすなわ
ち円筒研削工程でつけたオリエンテーションフラットの
結晶方位をX線回折法などで測定しておき、その誤差分
を補正するように面取り加工機でオリエンテーションフ
ラット部側面の加工を行えば、より正確な結晶方位精度
を持ったオリエンテーションフラットを形成することが
できる。本実施例では、その後ラッピング、エッチン
グ、ポリシングを施し鏡面仕上げウエハーとした。完成
したウエハーのオリエンテーションフラット部を表面か
ら光学顕微鏡で観察したところ、オリエンテーションフ
ラット部側面と表面がなす稜線が明瞭に認められ、容易
に焦点を合わせることができた。さらに、このオリエン
テーションフラットを用いて、顕微鏡によりマスクの角
度合わせを行い、ウエハー表面にオリエンテーションフ
ラットに直交する方向を狙ってストライプ状のパターン
を形成した。その後、ウエハーをオリエンテーションフ
ラットと直交する方向に劈開し、図6に示す劈開面とス
トライプ状パターンとの角度のズレθを測定した。
Since such a processing cannot be performed by a copying-type chamfering machine, a chamfering machine having a numerical control mechanism is used. At this time, the crystal orientation of the orientation flat before the chamfering, that is, in the cylindrical grinding process, is measured by an X-ray diffraction method or the like, and the side of the orientation flat is machined by a chamfering machine so as to correct the error. Is performed, an orientation flat having more accurate crystal orientation can be formed. In this embodiment, a lapping, etching, and polishing are performed to obtain a mirror-finished wafer. When the orientation flat portion of the completed wafer was observed from the surface with an optical microscope, the ridge formed by the side surface of the orientation flat portion and the surface was clearly recognized, and the focus could be easily focused. Further, using this orientation flat, the angle of the mask was adjusted with a microscope, and a stripe-shaped pattern was formed on the wafer surface in a direction orthogonal to the orientation flat. Thereafter, the wafer was cleaved in a direction orthogonal to the orientation flat, and the angle θ between the cleavage plane and the stripe pattern shown in FIG. 6 was measured.

【0016】また、比較のため図1のフローの面取り工
程においてオリエンテーションフラット部にも面取りを
施し、すなわち従来技術で述べたようにオリエンテーシ
ョン部側面とウエハー表裏面が滑らかな曲線で連続する
ように加工し、面取り工程以外の工程については前述の
実施例と同様の方法で加工したウエハーを用意した。こ
れらのウエハーの劈開面とストライプ状パターンの角度
のズレθを測定した結果、比較例においてはθ>0.05°
となるウエハーが5%あった。一方、本発明の実施例で
はθ>0.05°となるウエハーは1%以下であった。
For comparison, the orientation flat portion is also chamfered in the chamfering step of the flow shown in FIG. 1, that is, processing is performed so that the side surface of the orientation portion and the front and back surfaces of the wafer are continuous with a smooth curve as described in the prior art. A wafer processed by the same method as that of the above-described embodiment was prepared for the steps other than the chamfering step. As a result of measuring the angle θ between the cleavage plane of these wafers and the angle of the stripe pattern, in the comparative example, θ> 0.05 °
Was 5%. On the other hand, in Examples of the present invention, the ratio of wafers satisfying θ> 0.05 ° was 1% or less.

【0017】[0017]

【発明の効果】以上説明したように本発明によれば、オ
リエンテーションフラット部に面取りを施さず、側面の
み機械加工し、オリエンテーションフラット部側面とウ
エハー表面を直交させることにより、デバイス作製工程
における光学的な角度合わせ作業を容易、かつ正確に行
うことができる。さらに、このような形状を得るための
従来の製造方法例えば劈開によるものに比較し、製造に
手間がかかからず、さらにオリエンテーションフラット
長さを正確に制御することができる。
As described above, according to the present invention, the orientation flat portion is not chamfered, but only the side surface is machined, and the orientation flat portion side surface and the wafer surface are orthogonalized, thereby achieving an optical process in the device manufacturing process. Angle adjustment work can be performed easily and accurately. Further, as compared with a conventional manufacturing method for obtaining such a shape, for example, by cleaving, it takes less time and effort to manufacture, and the orientation flat length can be accurately controlled.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 半導体ウエハーの製造工程を説明するフロー
FIG. 1 is a flowchart illustrating a semiconductor wafer manufacturing process.

【図2】 従来技術による半導体ウエハーのオリエンテ
ーションフラット部の断面図
FIG. 2 is a cross-sectional view of an orientation flat portion of a semiconductor wafer according to the related art.

【図3】 従来技術による半導体ウエハーのオリエンテ
ーションフラット部表面から光学顕微鏡により観察した
際、焦点が合わないことを示す図
FIG. 3 is a diagram showing that a focus is not obtained when observed by an optical microscope from the surface of an orientation flat portion of a semiconductor wafer according to a conventional technique.

【図4】 本発明による面取り工程を施した後のウエハ
ーの形状を示す図
FIG. 4 is a view showing a shape of a wafer after a chamfering step according to the present invention;

【図5】 面取り工程に投入する前のウエハー形状を示
す図
FIG. 5 is a view showing the shape of a wafer before it is put into a chamfering process.

【図6】 オリエンテーションフラットを基準に形成し
たストライプ状パターンとオリエンテーションフラット
に直交する劈開面とのズレ角度θを示す図
FIG. 6 is a diagram showing a deviation angle θ between a stripe pattern formed based on an orientation flat and a cleavage plane orthogonal to the orientation flat.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 平坦な表裏面を有する円形ウエハーにお
いて、オリエンテーションフラット部を除く外周側面部
については面取り加工を施し表裏面と滑らかな曲線で連
続させ、オリエンテーションフラット部には面取りを施
さず側面のみを機械加工することにより表裏面と直交し
たオリエンテーションフラット部側面を有することを特
徴とする半導体ウエハー。
1. A circular wafer having flat front and back surfaces, chamfering is applied to an outer peripheral side surface excluding an orientation flat portion so as to be continuous with the front and back surfaces with a smooth curve, and the orientation flat portion is not chamfered and only a side surface is not provided. A semiconductor wafer having an orientation flat portion side surface orthogonal to the front and back surfaces by machining.
【請求項2】 平坦な表裏面を有する円形ウエハーにお
いて、オリエンテーションフラット部を除く外周側面部
については面取り加工を施し表裏面と滑らかな曲線で連
続させ、オリエンテーションフラット部には面取りを施
さず側面のみを機械加工することにより表裏面と直交さ
せるようにしたことを特徴とする半導体ウエハーの製造
方法。
2. In a circular wafer having flat front and rear surfaces, the outer peripheral side surface except for the orientation flat portion is chamfered to be continuous with the front and rear surfaces with a smooth curve, and the orientation flat portion is not chamfered and only the side surfaces are not chamfered. A semiconductor wafer is machined so as to be orthogonal to the front and back surfaces.
JP23248498A 1998-08-19 1998-08-19 Semiconductor wafer and manufacturing method thereof Expired - Lifetime JP4449088B2 (en)

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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23248498A JP4449088B2 (en) 1998-08-19 1998-08-19 Semiconductor wafer and manufacturing method thereof

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Application Number Title Priority Date Filing Date
JP2001105397A Division JP4011300B2 (en) 2001-04-04 2001-04-04 Semiconductor wafer and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2000068171A true JP2000068171A (en) 2000-03-03
JP4449088B2 JP4449088B2 (en) 2010-04-14

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WO2003077297A1 (en) * 2002-03-14 2003-09-18 Disco Corporation Method for grinding rear surface of semiconductor wafer
US7374618B2 (en) 2005-11-09 2008-05-20 Hitachi Cable, Ltd. Group III nitride semiconductor substrate
US7595509B2 (en) 2005-02-03 2009-09-29 Hitachi Cable, Ltd. Single crystal wafer for semiconductor laser
JP2021020844A (en) * 2019-07-26 2021-02-18 Jx金属株式会社 Indium phosphide substrate
JP2021020843A (en) * 2019-07-26 2021-02-18 Jx金属株式会社 Indium phosphide substrate
JP2021022659A (en) * 2019-07-26 2021-02-18 Jx金属株式会社 Indium phosphide substrate and manufacturing method thereof
JP2021022660A (en) * 2019-07-26 2021-02-18 Jx金属株式会社 Indium phosphide substrate and manufacturing method thereof

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003077297A1 (en) * 2002-03-14 2003-09-18 Disco Corporation Method for grinding rear surface of semiconductor wafer
EP1484792A1 (en) * 2002-03-14 2004-12-08 Disco Corporation Method for grinding rear surface of semiconductor wafer
EP1484792A4 (en) * 2002-03-14 2006-08-02 Disco Corp Method for grinding rear surface of semiconductor wafer
US7595509B2 (en) 2005-02-03 2009-09-29 Hitachi Cable, Ltd. Single crystal wafer for semiconductor laser
US7374618B2 (en) 2005-11-09 2008-05-20 Hitachi Cable, Ltd. Group III nitride semiconductor substrate
CN100456506C (en) * 2005-11-09 2009-01-28 日立电线株式会社 Group iii nitride semiconductor substrate
JP2021020844A (en) * 2019-07-26 2021-02-18 Jx金属株式会社 Indium phosphide substrate
JP2021020843A (en) * 2019-07-26 2021-02-18 Jx金属株式会社 Indium phosphide substrate
JP2021022659A (en) * 2019-07-26 2021-02-18 Jx金属株式会社 Indium phosphide substrate and manufacturing method thereof
JP2021022660A (en) * 2019-07-26 2021-02-18 Jx金属株式会社 Indium phosphide substrate and manufacturing method thereof

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