JP2000065604A - Encoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect a malfunction of an optical encoder caused by stains to slits of a scale plate. SOLUTION: A light-projecting part 12a, a light-detecting part 12b are set at opposite positions to a scale plate 11. In addition to photodetecting elements of an A-phase and a-B phase for detecting a transmission light from a light projector via the fixed slit plate, a photodetecting element of a C-phase which is the same phase as the A-phase is arranged. Since outputs of the A-phase and C-phase synchronize, an abnormal signal is detected by an exclusive OR circuit. An abnormal state caused by stains of slits can be detected accordingly.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical rotary encoder and a linear encoder, and more particularly to an encoder having an abnormality detecting circuit.

[0002]

2. Description of the Related Art An optical encoder is provided with a scale plate in which slits of minute pitches are formed at regular intervals, and a sensor head having a light projecting unit and a light receiving unit sandwiching the scale plate. The relative position between the scale plate and the sensor head is detected based on the output. Such a linear encoder may be used in an open structure, and dust or the like may adhere to the slit of the scale plate, and a normal output may not be obtained.

In order to solve such a problem, fixed slits corresponding to a plurality of slits of the scale plate are provided,
A light receiving section is provided at each position passing through the fixed slit. An encoder that adds the outputs of the respective light receiving units and shapes the obtained analog waveform to obtain a position signal is also used. In this way, even if some of the slits are dirty, no malfunction occurs.

[0004]

However, if the slit pitch is reduced to improve the resolution, it becomes difficult to mount a plurality of light receiving elements. For example, if the slit pitch is as small as 1 mm, a plurality of light receiving elements cannot usually be mounted. Therefore, one corresponding to one slit
In the case where two light receiving elements are provided, there is a problem in that if dust or the like adheres to the slit of the scale plate and the light cannot be transmitted, a malfunction occurs immediately. When used in an environment where dirt is likely to occur, a linear encoder such as a magnetic encoder cannot be used.

Further, there is also used an encoder in which the analog output from the two-phase light receiving element of the encoder is divided by a resistance voltage dividing circuit and a multiplied signal is taken out to improve the resolution of position detection. Such a multiplication type encoder has a drawback that the multiplication may not be performed normally due to contamination of the slit or the like.

The invention of claim 1 of the present application has been made in view of such a conventional problem, and an object of the invention is to make it possible to detect a multiplication abnormality in a multiplication type encoder. Another object of the present invention is to make it possible to detect in advance the contamination of the slits of the scale plate and the deterioration of the amount of light upon detection as an abnormal state with a relatively simple configuration in the encoder.

[0007]

According to a first aspect of the present invention, there is provided a scale plate having slits at a constant pitch,
A light-emitting unit that irradiates light toward the scale plate, and a light-receiving unit that receives light through the scale plate, and a head unit that is provided to move relative to the scale plate,
Wherein the light receiving unit has a first slit having the same width as the slit of the scale plate, and an interval corresponding to a certain phase difference of a slit pitch of the scale plate with respect to the first slit. A fixed slit plate having a second slit provided at a distance, first and second light receiving elements respectively attached to positions of the fixed slit plate corresponding to the first and second slits, , Multiplying the output based on the phase difference of the output obtained from the second light receiving element,
A multiplying circuit that outputs the multiplied signal as a signal of a relative movement amount, and counts the signal multiplied by the multiplying circuit using a light receiving signal input to the multiplying circuit, and performs multiplication based on the counted value. And a multiplication abnormality detection circuit for detecting abnormality.

In this case, a switch may be provided to switch between the input of the multiplier and the output of the multiplier, and a counter may be provided at the output side of the multiplier, and the count value may be stored in the output side. You may make it output as a signal. Further, this encoder can be applied to either a linear encoder or a rotary encoder.

According to a second aspect of the present invention, there is provided a scale plate having slits formed at a constant pitch, a light projecting unit for emitting light toward the scale plate, and a light receiving unit for receiving light via the scale plate. And a head portion provided so as to move relative to the scale plate, wherein the light receiving portion has a first slit corresponding to a slit of the scale plate, and the first slit. A fixed slit plate having a third slit provided at intervals of an integral multiple of the slit pitch of the scale plate, and attached to positions corresponding to the first and third slits of the fixed slit plate, respectively. The first and third light receiving elements, a signal processing circuit unit for detecting a relative movement amount between the scale plate and the head unit, and exclusion of signals obtained from the first and third light receiving elements. By logical disjunction Have an abnormal signal processing circuit for detecting an abnormality of the transmission of the slits, the Te is characterized in.

According to a third aspect of the present invention, in the encoder of the second aspect, the abnormal signal processing circuit performs an exclusive OR operation on the light receiving signals obtained by the first and third light receiving elements of the light receiving circuit. It has an exclusive OR circuit, eliminates a phase shift at the time of rising and falling of the exclusive OR circuit, and detects an abnormality in transmission of the slit based on a difference between its inputs. is there.

According to a fourth aspect of the present invention, in the encoder according to the third aspect, the abnormal signal processing circuit takes an exclusive OR of signals obtained from first and third light receiving elements of the light receiving circuit. An exclusive-OR circuit, a detection circuit that outputs only one of the rising and falling of the output of the exclusive-OR circuit, and a fall or rising of the output by integrating the output of the exclusive-OR circuit. And an AND circuit for detecting an abnormal signal based on a logical product of the output of the integration circuit and the output of the detection circuit.

In these encoders, the light receiving section is composed of a first slit and a second slit having a slightly different phase from the first slit.
And a second light receiving element may be provided at a position corresponding to the second slit and the second slit. In this case, the relative movement direction and rotation direction between the scale plate and the head can be detected based on the phase relationship between the outputs of the first and second light receiving elements. The encoder can be applied to both a linear encoder and a rotary encoder.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1A is a schematic diagram showing a configuration of a head portion of a linear encoder according to an embodiment of the present invention, FIG. 1B is a diagram showing a configuration of a slit thereof, FIG.
FIG. 2A is a perspective view showing the appearance of a linear encoder, and FIG.
(B) is a front view thereof. As shown in these figures, a sensor head 12 for detecting the position of a scale plate 11 is fixed to a base 10. The sensor head 12 has a gap at the center, and a light projecting portion 12a and a light receiving portion 12b on both sides.
Are configured to face each other. FIG. 1 (a)
As shown in FIG. 1, a light emitting element 13 for emitting light of a fixed width is mounted on a printed circuit board 14 on the side of the light emitting portion 12a. A fixed slit plate 15 is provided on the front surface on the side of the light receiving unit 12b opposite to the light receiving unit 12b.
At positions corresponding to the third to third slits 15a, 15b, and 15c, first, second, and third light receiving elements 16a, 16b, and 16c such as photodiodes are attached, respectively. The light receiving elements 16a to 16c are mounted on a printed circuit board 17, and electronic circuit components for signal processing for outputting position signals based on these outputs are mounted on the printed circuit board 17.

Here, the scale plate 11 and the fixed slit plate 1
FIG. 1 (b) shows the relationship with No. 5. As shown in this figure, the scale plate 11 is formed with an elongated slit having a constant pitch p and a constant width. As shown in the figure, the fixed slit plate 15 has a shape equal to the slit of the scale plate 11, and is located at an integer multiple of the pitch p, that is, at a position np (n is an integer) away.
First and third slits 15a and 15c are provided. Further, the second slit 15b is provided at a position having a predetermined phase difference, for example, at a position shifted by 1 / 4p, irrespective of the pitch of the integral multiple pitch with respect to the slit 15a.

Next, the configuration of the signal processing circuit will be described. FIG. 3 shows each slit 15 behind the fixed slit plate 15.
It is a block diagram which shows the light receiving element provided behind a-15c, and the structure of the electronic circuit part which processes the output. Outputs of the light receiving elements 16a to 16c are input to amplifiers 21 to 23, respectively, and amplified outputs are input to waveform shaping circuits 24 to 26, respectively. Outputs of the waveform shaping circuits 24 and 25 are input to a signal processing circuit 27, and outputs of the waveform shaping circuits 24 and 26 are input to an abnormal signal processing circuit 28A. Here, the outputs of the waveform shaping circuits 24, 25 and 26 are assumed to be A-phase, B-phase and C-phase outputs, respectively. The signal processing circuit 27 detects the moving direction of the scale plate 11 based on the phase difference between the A-phase and B-phase outputs, and outputs a position signal by counting the number of A-phase or B-phase input pulses. Abnormal signal processing circuit 2
8A is the first and third slits 15 of the fixed slit plate 15
Since the interval between a and 15c is in the relationship of np, the same signal should always be obtained. An abnormality is detected by detecting the mismatch.

Next, the configuration of the abnormal signal processing 28A will be described with reference to FIG. The abnormal signal processing circuit 28A is provided with an EOR circuit 31 for performing an exclusive OR operation on the outputs of the A and C phases of the waveform shaping circuits 24 and 26, a CR type integrating circuit 32 for integrating the outputs, and an output of the integrating circuit 32. Is input to the flip-flop 33. The flip-flop is constituted by two NOR circuits 34 and 35,
The output of the circuit 34 is provided to one input terminal of a NOR circuit 35. A reset input terminal is connected to the other input side of the NOR circuit 35, and its output is output as the other input terminal of the NOR circuit 34 and an output abnormality signal.

Next, the operation of this embodiment will be described. The scale plate 11 corresponds to the sensor head 12 in FIG.
In the case of moving in the direction of the arrow R or L shown in (a), each time the light passes through the slits of the scale plate 11, the light receiving elements 16a-1 through the slits 15a-15c of the fixed slit plate.
An analog signal shown in FIGS. 5A, 5B and 5C is obtained in FIG. 6C. The waveform shaping circuits 24 and 26 obtain the outputs shown in FIGS. 5D and 5E by shaping the waveform. Then, as shown in FIG.
If some of the slits 11x are dirty and hardly transmit light, the C-phase light receiving element 16
As shown in FIG. 5C, a low-level output is obtained from c. Therefore, as shown in FIGS. 5F and 5G, the output of the EOR circuit 31 becomes H level, the output levels of the NOR circuits 34 and 35 are inverted, and an output abnormality signal can be output. As described above, in the present embodiment, the exclusive OR of the two signals of the light receiving elements 16a and 16c arranged in the two in-phase slits of the fixed slit plate 15 reduces the light transmission amount of the slit. In such a case, an abnormal state is detected.

Next, a second embodiment of the present invention will be described. In this embodiment, similarly to the above-described first embodiment, the slits 15 of the A to C phases are formed in the fixed slit plate 15.
a to 15c, and the light receiving element 16
a to 16c are provided, and the abnormal signal is processed based on the outputs of the A and C phases. In this embodiment, a malfunction of the abnormal signal processing circuit due to a phase shift between two inputs is prevented, and the abnormal signal processing circuit will be described. As shown in FIG. 6, the abnormal signal processing circuit 28B includes a rising detection circuit 41, an EOR circuit 42 for performing an exclusive OR operation of the C phase and the A phase, and an EOR circuit 42.
, And an AND circuit 44 that calculates the logical product of the outputs of the in-phase and phase shift permitting circuits 43 and 41, and an integrating circuit 45 that integrates these outputs. The output of the integration circuit 45 is supplied to a flip-flop 46, and when an abnormality is detected, the output is processed as an abnormal signal. A rising detection circuit 41 inverts and integrates the output of the A-phase, and calculates a logical product with the A-phase. A rising detection circuit 51 inverts and integrates the output of the C-phase to obtain the logical product with the C-phase. It is configured to include a phase rise detection circuit 52 and an OR circuit 53 that calculates the logical sum of the outputs of the two rise detection circuits 51 and 52.

Next, the operation of the abnormal signal processing circuit 28B according to this embodiment will be described with reference to a time chart. (A) to (j) of FIGS. 7 and 8 show waveforms of respective parts of a to j of FIG. FIGS. 7A and 7B show the outputs of the A phase and the C phase, respectively. The phases of the A phase and the C phase are almost the same, but it is assumed that there is a slight phase difference. Therefore, the outputs of the rise detection circuits 51 and 52 are respectively shown in FIG.
(C) and (d). The output of the OR circuit 53 is as shown in FIG. Further, since the A phase and the C phase have a slight phase difference, the output of the EOR circuit 42 corresponds to the phase difference between the A phase and the C phase as shown in FIG. Here, assuming that the phase difference does not coincide between the rising edge and the falling edge, the output shown is obtained. Further, the common-mode phase shift allowable circuit 43 integrates this output,
A waveform having a blunt rising as shown in FIG. 7 (g) is obtained. Also, a rising edge detection circuit 41 and an in-phase phase shift allowable circuit 43
When an AND operation is performed with the output of (i), an L level signal is always obtained as shown in FIG. When a slight phase difference occurs in this way, only the rise is detected by the rise detection circuit 41.
And the phase difference is removed by the common-mode phase shift permitting circuit 43, so that an abnormality detection signal cannot be obtained.

However, as shown in FIG. 8, when any of the slits is in the light-impermeable state, an abnormality is detected. For example, as shown in FIGS. 8A and 8B, when the output of the C phase is obtained when the output of the A phase is not obtained due to the contamination of the scale plate, and while the output of the A phase is obtained. When the output of the C-phase is not obtained at the same time, a rising detection signal is obtained at the time of rising of each output by the OR circuit 53 of the rising detecting circuit 41. In this case, as shown in FIGS. 8F and 8G, the pulse width of the output of the EOR circuit 42 increases, so that the integrated output of the phase shift permitting circuit 43 also increases. Therefore, the set signal is given to the flip-flop 46 by the output of the AND circuit 44, and an abnormality detection signal can be output as shown in FIG. Then, as shown in FIG. 8 (i), the abnormal output is held until the reset input is applied to the flip-flop 46.

As described above, in the present embodiment, the presence or absence of an abnormality is detected based on only the phase change at the time of rising by processing the outputs of the exclusive OR of the two rising detection circuits. . Therefore, even when the phases of the two inputs are different at the time of rising and at the time of falling, the abnormality is reliably detected with a simple configuration without complicating the setting of the time constant of the integration circuit and the like of the abnormality detection circuit. be able to. Needless to say, the same processing may be performed by the two falling detection circuits, and an abnormality may be detected based on the phase mismatch at the time of falling.

Next, a third embodiment of the present invention will be described. The linear encoder according to this embodiment is a multiplication type encoder that uses a multiplication circuit to improve the resolution and detects an abnormality in multiplication.
FIG. 9 is a block diagram showing a configuration of a signal processing unit of the linear encoder. In this figure, the linear encoder is provided with the first and second slits on the fixed slit plate and the first and second light receiving elements 16a and 16b are arranged behind the fixed slit plate as in the first embodiment described above. The outputs are amplifiers 21 and 22 and waveform shaping circuits 24 and 25 as in FIG.
Waveform dividing / shaping circuit 6 as A-phase and B-phase outputs via
1 is input. The waveform dividing / shaping circuit 61 includes the A phase and the B
The input of the phase is divided by a resistance dividing circuit and shaped for each divided waveform. The multiplying circuit 62 combines the divided signals, performs multiplication by a predetermined multiplication number, for example, 16 times, and outputs the output to the outside as a position signal to improve the resolution. A direction discriminating circuit 63 for discriminating the direction based on the output of the multiplying circuit 62 is provided. The direction discriminating circuit 63 discriminates the direction based on the phase difference between the A-phase multiplied signal and the B-phase multiplied signal, and is output to the outside as a direction discriminating signal D.
Further, the direction discrimination signal D, the A-phase input and the A-phase 16-times multiplied output A16 are input to the multiplication abnormality detection circuit 64. The multiplying circuit 62 may simultaneously perform other multiplications such as quadruple multiplication and eight multiplication, and may be provided with a switch for switching between them. Alternatively, an input signal before multiplication and a multiplied signal may be switched and output. Further, a counter for counting the number of pulses of the multiplied output or the original output may be provided, and the count value of the counter may be output as a position signal.

FIG. 10 is a block diagram showing a configuration of the multiplication abnormality detection circuit 64. As shown in FIG.
Is input to the direction determination signal latch circuit 71. The direction discrimination signal latch circuit 71 sets an H level when discriminating the direction in one of the directions, for example, the R direction, and latches the discrimination signal to set an abnormality detection state.
The latch output RA of the direction determination signal is input to the AND circuit 72. An A-phase input signal is input to the other input terminal of the AND circuit 72, and its AND signal is input to the falling / rising detecting circuit 73. The falling / rising detecting circuit 73 holds the output at the H level except for the first pulse of the A-phase signal when the moving direction changes in the R direction, and detects the signal at the H level. The output S2 is input to the AND circuit 74. An A-phase input signal is supplied to the other input terminal of the AND circuit 74, and a logical product signal thereof is provided as a load signal LOAD to the counter 75 and the fall detecting circuit 7.
6 given. The counter 75 outputs the value of 1 from the multiplication circuit 62.
The signal A16 multiplied by 6 is input, and the load signal LOA is input.
When D is at the H level, this is counted and a parallel signal of QA to QD is supplied to the latch circuit 77. Fall detection circuit 7
6 outputs a clock signal CLK at the falling timing of the load signal LOAD, and outputs a latch circuit 77 and an AND circuit 7.
8 and a pulse delay circuit 79. The latch circuit 77 holds the parallel output of the counter 75 at the timing of the clock signal CLK. The comparison circuit 80 outputs the held output of a predetermined count value, in this case, 1/2 of the signal multiplied by 16 in this case. When the number of pulses, that is, the count value is “8”, the comparison signal C is set to L level, and otherwise to H level.
NT is supplied to an AND circuit 78. The AND circuit 78 gives the logical product of the clock signal CLK and the comparison signal CNT to the AND circuit 81. The pulse delay circuit 79 delays one clock of the clock signal CLK and supplies the delayed signal S3 to the AND circuit 81. The AND circuit 81 sets an RS flip-flop 82 that holds an abnormal output by its logical product. The RS flip-flop 82 holds the abnormality detection state after the abnormality is detected, and resets when a reset input is given from the outside, and its output OUT is output to the outside as an abnormality signal.

The following is an explanation of the multiplying abnormality detection operation of this embodiment.
This will be described with reference to the time charts of FIGS.
You. In FIG. 11 and FIG.₁Move to the right
It is assumed that the movement has started. The A-phase input signal is shown in FIG.
As shown in (a), the clock signal has a substantially constant cycle.
The rightward rotation is performed by the direction determination signal latch circuit 71.
After the rotation, the direction discrimination signal D is held and shown in FIG.
It is at the H level as described above. The multiplication from the multiplication circuit 62
The multiplied signal A16 is multiplied as shown in FIG.
Is a multiplied signal with a constant pulse width as long as
You. The output S1 of the AND circuit 72 is at the time of rightward movement.
This is the same signal as the A-phase signal. Rise / fall detection times
From the path 73, as shown in FIG.
The signal S2 which becomes H level after being delayed by one clock of the signal is obtained.
During this time, the detection range for abnormality detection is
You. While the signal S2 is at the H level, the A-phase input signal is
As shown in FIG.
To the counter 75 and the falling detection circuit 76.
Accordingly, the falling time t of the A-phase signal_Two , t_Three, T_Four, T
₆ As shown in FIG. 11 (g), the falling detection circuit 76
Clock signal CLK is applied to latch circuit 77, and
The count outputs QA to QD of the counter 75 at the down timing
Is held. Therefore, as shown in FIGS.
In the normal state, the timing of falling of phase A shown by the broken line
The count value "8" is held by the
Becomes L level. The clock signal CLK is pulse delayed
As shown in FIG.
Delayed at time t_ThreeThe level becomes higher. And 16
As long as the multiplication is performed normally, the output CNT of the comparison circuit is
Since the output is at L level, the outputs of the AND circuits 78 and 81 are at L level.
Level, and the RS flip-flop 82 is set.
No abnormal signal can be obtained.

[0025] Now operation time t ₅ ~t ₇ of the multiplier circuit 62
11C, the count value becomes a value other than “8” at time t ₆ of the timing at which the falling edge detection circuit 76 outputs the clock signal CLK. As shown in 1), the output of the comparison circuit 80 becomes H level. Accordingly, the output of the AND circuit 78 also goes to H level, and the signal of H level is
The signal is input to the S flip-flop 82. Therefore, FIG.
As shown in (p), the abnormal state is notified to the outside. In this case, unless an external reset signal is applied, the abnormal state is maintained as it is, and the abnormal state of the multiplication can be detected.

An abnormal state of the multiplication is more likely to occur when the slit is dirty over a wide area because the analog output level from the light receiving element is reduced. Therefore, when the slit has a wide range of dirt that cannot be detected in the first and second embodiments and affects the operation of the multiplying circuit, an abnormal state of the multiplication can be identified.

In each of the embodiments described above, the scale plate of the linear encoder is moved left and right.
Needless to say, the scale plate can be fixed and the sensor head can be moved, so that the linear encoder can be configured as a linear encoder that detects the moving distance.

Further, the first and second embodiments described above and the third
It goes without saying that two abnormality detection circuits may be provided in one encoder by combining the abnormality detection with the embodiment.

In each of the embodiments described above, a linear encoder is described. However, the present invention can be applied to an incremental rotary encoder as shown in FIG. In this case, the rotating scale plate 101 is a circular plate having slits formed at equal intervals on the circumference. Also, the sensor head 1 is held so as to sandwich the rotating scale plate 101.
02 is provided. The sensor head 102 is the first
As in the first embodiment, a light emitting unit and a light receiving unit are integrally formed at a position facing the light emitting unit, and the light receiving unit is located at a position n pitches apart from the light emitting unit as in the first embodiment. 1st, 3rd
Is provided in a position shifted by a predetermined phase from the first fixed slit, and a light receiving element is provided in each position, thereby providing the same as in the first and second embodiments described above. An abnormal signal detection circuit can be configured. Also, when multiplying the outputs of the A-phase and the B-phase, a multiplication abnormality detection circuit similar to that of the third embodiment can be provided.

[0030]

As described in detail above, according to the first aspect of the present invention, if the slit is dirty over a wide range and an abnormality of the multiplication occurs when the analog output level is lowered, etc. The effect that the abnormal state can be identified is obtained. According to the invention of claims 2 to 4, dirt on the slit of the scale plate or a decrease in output level from the slit can be detected as an abnormal state with a relatively simple configuration in the optical encoder, and a part of the slit can be detected. Can be detected when there is a defect. According to the third and fourth aspects of the present invention, even when there is a slight phase shift in the output from the two phases, it is possible to perform the abnormality detection without malfunction.

[Brief description of the drawings]

FIG. 1A is a schematic diagram illustrating a configuration of a sensor head of an encoder according to a first embodiment of the present invention, and FIG. 1B is a diagram illustrating a relationship between a scale plate and a fixed slit plate.

FIG. 2 is a perspective view and a side view showing a configuration of a linear encoder according to the present embodiment.

FIG. 3 is a block diagram illustrating a configuration of a signal processing unit according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of an abnormal signal processing circuit according to the present embodiment.

FIG. 5 is a time chart illustrating an operation of the abnormal signal processing circuit according to the present embodiment.

FIG. 6 is a circuit diagram showing a configuration of an abnormal state processing circuit according to a second embodiment of the present invention.

FIG. 7 is a time chart (part 1) showing waveforms of respective units of the abnormal state processing circuit according to the second embodiment of the present invention.

FIG. 8 is a time chart (part 2) showing waveforms of respective parts of the abnormal state processing circuit according to the second embodiment of the present invention.

FIG. 9 is a block diagram illustrating a configuration of a signal processing unit of a linear encoder according to a third embodiment of the present invention.

FIG. 10 is a block diagram showing a configuration of a multiplication abnormality detection circuit of the rotary encoder according to the present embodiment.

FIG. 11 is a time chart (part 1) illustrating an operation of the multiplication abnormality detection circuit according to the present embodiment;

FIG. 12 is a time chart (part 2) illustrating the operation of the multiplication abnormality detection circuit according to the present embodiment;

FIG. 13 is a perspective view showing an example of a rotary encoder to which the present invention can be applied.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Calt plate 12 Sensor head 12a Light emitting part 12b Light receiving part 13 Light emitting element 15 Fixed slit plate 16a-16c Light receiving element 24, 25, 26 Waveform shaping circuit 27 Signal processing circuit 28A, 28B Abnormal signal processing circuit 41 Rise detection circuit 42 EOR circuit 43 In-phase shift permitting circuit 44 AND circuit 45 Integrating circuit 46 Flip-flop 51, 52 Rise detection circuit 61 Waveform division / shaping circuit 62 Multiplication circuit 63 Direction discrimination circuit 64 Multiplication abnormality detection circuit 71 Direction discrimination signal latch circuit 72, 74 , 78, 81 AND circuit 73 Rise / fall detection circuit 75 Counter 76 Fall detection circuit 77 Latch circuit 79 Pulse delay circuit 80 Comparison circuit 82 RS flip-flop

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2F003 AA13 AA22 AB02 AC02 AD03 2F077 AA01 AA41 CC02 CC08 NN05 NN30 PP19 QQ02 RR25 TT71 UU18 VV33

Claims (4)

[Claims] 1. A scale plate having a scale plate provided with slits of a constant pitch, a light projecting unit for irradiating light to the scale plate, and a light receiving unit for receiving light through the scale plate. A head portion provided to move relative to the
The light receiving unit comprises: a first slit having the same width as the slit of the scale plate; and an interval corresponding to a certain phase difference of a slit pitch of the scale plate with respect to the first slit. A fixed slit plate having a second slit provided at a distance; first and second light receiving elements respectively attached to positions of the fixed slit plate corresponding to the first and second slits; A multiplying circuit that multiplies the output based on the phase difference of the output obtained from the second light receiving element and outputs the multiplied signal as a signal of a relative movement amount; and a light receiving signal input to the multiplying circuit. A multiplication abnormality detection circuit for counting a signal multiplied by the multiplication circuit and detecting a multiplication abnormality based on the counted value. 2. The scale plate, comprising: a scale plate having slits of a constant pitch formed therein; a light projecting unit for irradiating the scale plate with light; and a light receiving unit for receiving light through the scale plate. A head portion provided to move relative to the
Comprising: a first slit corresponding to a slit of the scale plate;
And a fixed slit plate having a third slit provided at an interval of an integral multiple of the slit pitch of the scale plate with respect to the first slit, and a first slit and a third slit of the fixed slit plate. First and third light receiving elements respectively attached to corresponding positions; a signal processing circuit unit for detecting a relative movement amount between the scale plate and the head unit; and the first and third light receiving elements. An abnormal signal processing circuit for detecting an abnormality in transmission of the slit by using an exclusive OR of signals obtained from the encoder. 3. An abnormal signal processing circuit, comprising: an exclusive OR circuit that performs an exclusive OR operation on light receiving signals obtained by first and third light receiving elements of the light receiving circuit; 3. The encoder according to claim 2, wherein a phase shift at the time of rising and falling of the circuit is eliminated, and an abnormality in transmission of the slit is detected based on a difference between the inputs. 4. The exclusive signal OR circuit for taking an exclusive OR of signals obtained from first and third light receiving elements of the light receiving circuit, wherein the abnormal signal processing circuit comprises: A detection circuit that outputs only one of a rising edge and a falling edge of the output; an integrating circuit that eliminates a falling or rising phase shift by integrating an output of the exclusive OR circuit; and the integrating circuit. The encoder according to claim 3, further comprising: an AND circuit that detects an abnormal signal based on a logical product of outputs of the detection circuit.