JP3945813B1 - Photoelectric sensor - Google Patents

Abstract

Even in the case of an asynchronous photoelectric sensor having an oscillation circuit on each of a light projecting unit side and a light receiving unit side, a pseudo synchronization signal is generated, and a clock on the light receiving unit side with respect to an input pulse signal is generated. Even if the phase of the pulse is advanced or delayed, the received pulse signal must be accurately processed without malfunction.
The cycle of the input pulse and the cycle of the oscillator 27 are made the same, and the duty ratio of the clock pulse output from the input pulse and the oscillator 27 is set to 50%. The clock pulse C (j) and the inverted clock pulse BarC (j) are constantly monitored for receiving the input pulse, and the shift register 25 depends on whether the clock pulse C (j) or BarC (j) is received. The clock pulse C (j) or BarC (j) for shifting the signal is properly used.
[Selection] Figure 3

Description

The present invention relates to a photoelectric sensor that example Bei oscillator respectively to the sender and receiver.

  At present, there are two types of photoelectric sensors or photoelectric switches for detecting articles conveyed by position detection, conveyors, and the like, which are roughly classified into synchronous photoelectric sensors and asynchronous photoelectric sensors.

  The synchronous photoelectric sensor has only one oscillator on the whole of the light projecting unit side and the light receiving unit side, and projects pulse-modulated light from the light projecting element of the light projecting unit, and the light receiving element of the light receiving unit projects the light. The pulse modulated light from the light unit is received, and the same clock pulse from the oscillator in the light receiving unit is used as the synchronization signal between the light projecting unit and the light receiving unit. That is, the pulse modulated light synchronized with the synchronization signal from the light receiving unit is projected from the light projecting unit, and the light receiving unit receives the pulse modulated light with the same synchronization signal (clock pulse) and The presence or absence of the detection target object is determined based on the presence or absence.

  On the other hand, in the asynchronous photoelectric sensor, an oscillator is separately provided on the light projecting unit side and the light receiving unit side, and each clock pulse that is an output of the separate oscillator is used as a synchronization signal. In the synchronous photoelectric sensor, the light projecting part and the light receiving part are connected by a cable or the like in order to synchronize the light projecting part and the light receiving part, but in the asynchronous photoelectric sensor, the light projecting part and the light receiving part are connected. Since the unit is not connected with a cable or the like, it is often used when the light projecting unit and the light receiving unit are installed far apart.

  As an asynchronous photoelectric sensor, for example, there is one disclosed in Patent Document 1 below.

Japanese Patent Publication No. 4-48286

In the technique described in Patent Document 1, pulse-modulated light having a fixed repetition period projected from a light projecting unit is received on the light receiving unit side, and the received light input signal is received for each pulse. And a shift register that shifts a predetermined number of times so that the shift amount becomes larger than the period of the incident light signal and uses two output pulses at the rear stage based on the incident light signal as a counting signal.
Then, the previously received light incident signal is shifted by a shift register to be taken out as a counting signal, a gate signal is obtained from the received light signal received after a certain period, and the counting signal is output by the gate signal.

A D-type flip-flop is used in the preceding stage of the shift register described in Patent Document 1, and a light input signal has a circuit configuration that is input to a preset input terminal of the D-type flip-flop. . When the incoming light signal is input from the preset input terminal, all the incoming light signals are taken in even if they are not synchronized with the clock pulse.
That is, all the optical noise (disturbance light) is mistakenly taken in as an incoming light signal. In particular, when a signal having a constant period and a light noise having the same period received by the light projecting means are received, it does not operate normally and malfunctions.

  By the way, this patent document 1 includes the following patent document 2 as a reference document. This Patent Document 2 is used as a cited document (reference document) when an examiner issues a notice of reasons for refusal in the examination process.

Japanese Examined Patent Publication No. 56-28049

  The technology described in Patent Document 2 is an asynchronous photoelectric switch (photoelectric sensor) circuit, and an oscillation circuit is provided on the light projecting portion side of the photoelectric sensor. Light emission of the optical element is pulse-modulated. Further, the light receiving unit side includes an oscillation circuit provided separately from the light projecting unit side, and a signal processing circuit that performs signal processing on the received light pulse. The signal processing circuit includes a flip-flop that temporarily holds the received light pulse, And a shift register for sequentially shifting the output of the flip-flop, and a delay circuit for resetting the flip-flop.

In this Patent Document 2, a light receiving pulse (pulse signal) is read in series in response to a clock pulse of a predetermined period from an oscillation circuit, and a serial input parallel output type shift register that is sequentially shifted, and a parallel output of this shift register are It has a flip-flop that is set when all are “1” and reset when all are “0”.
For example, when five pulse signals are continuously received, all the outputs of the shift register are “1”, and the detection target object is detected.

  In the asynchronous photoelectric sensor described in Patent Document 2, since the light projecting unit side and the light receiving unit side are not synchronized, the light receiving unit side uses a flip-flop to generate a pulse signal from the light projecting unit side. Once held, the signal is shifted to the next flip-flop, and the flip-flop is reset before the next pulse signal arrives.

However, in Patent Document 2, for example, when five light reception pulses (pulse signals) are received, it is determined that an object is detected for the first time, and an object detection signal is output. The object detection signal is output at the fifth clock pulse before receiving the signal and receiving the fifth pulse signal.
In such a case, if the four pulse signals are optical noise, the object detection signal is erroneously output.

Further, in Patent Document 2, a pulse projected from a light projecting element of a light projecting unit is output in synchronization with a clock pulse from an oscillation circuit in the light projecting unit. The pulse signal from the light projecting unit is received by the clock pulse from the oscillation circuit.
In such a case, a relative phase shift always occurs between the pulse signal from the light projecting unit and the clock pulse of the light receiving unit. However, no countermeasure has been taken against the effects caused by this phenomenon. Therefore, there is a problem that a malfunction occurs.

  In other words, when the phase of the clock pulse on the light receiving unit side is advanced relative to the received pulse signal, or when the pulse signal is detected normally or not detected when the phase of the clock pulse is delayed Occurs. This is because an oscillation circuit that outputs a clock pulse is separately provided on each of the light projecting unit side and the light receiving unit side, and the synchronization between the clock pulses is not synchronized. As a fate.

In other words, the frequency of the oscillation circuit on the light emitting unit side and the frequency of the oscillation circuit on the light receiving unit side are the same, and the pulse signal from the light projecting unit and the clock pulse on the light receiving unit side are matched, The phase of the clock pulse is advanced or delayed. This is due to the following reason.
(1) Even if the electronic components that make up the oscillation circuit on the light emitting unit side and the light receiving unit side are manufactured using the same lot and the same specification value, the time constant of the completed oscillation circuit must not be exactly the same. .
(2) Even if the initial values of the oscillation circuits on the light emitting unit side and the light receiving unit side are adjusted to the same value, if the current flows after the power is turned on and the temperature rises, the clock pulse and light reception on the light projecting unit side The time constant with the clock pulse on the part side must not match.
(3) Since the power supply for the light projecting part and the light receiving part are provided separately, even if the power is turned on at the same time, the time until each voltage becomes constant does not exactly match. The time required for the oscillator circuit to start generating pulses is not exactly the same.

  If the phase of the pulse signal and the clock pulse are relatively shifted with the passage of time due to the physical reasons such as the physical properties of the electronic component materials described above and the transient phenomenon of the electric circuit, malfunction occurs at a point on a certain time chart. (Does not operate normally.)

The present invention was provided in view of the above problems, it is to provide a photoelectric sensor having at least the following purposes.
(1) Even in the case of an asynchronous photoelectric sensor having an oscillation circuit on each of the light projecting unit side and the light receiving unit side, a pseudo synchronization signal is created and a pulse signal from the light projecting unit side is generated. Even if the phase of the clock pulse on the light receiving unit side is advanced or delayed, the received pulse signal must be accurately processed without malfunction.
(2) It is possible to easily avoid malfunction even when optical noise having the same period as the optical signal from the light projecting unit side arrives.
(3) The same circuit can be applied to either a reflection type photoelectric sensor or a transmission type photoelectric sensor.

Therefore, in the photoelectric sensor according to the first aspect of the present invention, the first oscillator 11 that outputs a clock pulse as a synchronization signal, and the clock pulse and the period in synchronization with the clock pulse from the first oscillator 11 are provided. And a light projecting unit 1 having a light projecting element 13 for projecting pulse-modulated light having the same duty ratio;
A light receiving element 21 that receives the pulse modulated light from the light projecting element 13 of the light projecting unit 1, a second oscillator 27 that outputs a clock pulse as a synchronization signal, and an input pulse signal output from the light receiving element 21. temporarily holds the flip-flop 24, this takes in the output of the flip-flop 24 and shift register 25 for sequential shift, detection determining circuit 28 determines the presence or absence of the detection target object (3) at the output of the shift register 25 And the signal path of the light receiving element 21, the flip-flop 24 and the shift register 25. The signal from the second oscillator 27 is sequentially shifted in order to sequentially shift the signals received by the shift register 25. The clock pulse C (j) or the inverted clock pulse BarC (j) obtained by inverting the clock pulse C (j) is used as the shift register. A light receiving section 2 having a synchronization signal generating circuit 26 that generates 25 synchronization signals for circuit operation ,
The period of the clock pulse of the first oscillator 11 and the clock pulse of the second oscillator 27 are the same, and the first oscillator 11 and the first oscillator 11 are configured to receive the pulse-modulated light from the light projecting element 13. Setting means for setting the duty ratio of both clock pulses of the second oscillator 27 to 50%, respectively;
The synchronization signal generating circuit 26 is
Wherein are input simultaneously with the input pulse signal to the flip-flop 24, the input pulse signal from the clock pulses C (j) more the light projecting unit 1 of the light emitting element 13 from the second oscillator 27 of the light receiving portion 2 First receiving means 31 for receiving
An input pulse signal input from the light projecting element 13 of the light projecting unit 1 by the inverted clock pulse BarC (j) from the second oscillator 27 of the light receiving unit 2 that is input simultaneously with the input pulse signal to the flip-flop 24. Second receiving means 32 for receiving the signals synchronously;
Whether the receiving means 31 and 32 receive the input pulse signal from the light receiving element 21 in synchronization with the clock pulse C (j) of the second oscillator 27 or the inverted clock pulse BarC (j). The input pulse signal received by the light receiving element 21 of the light receiving unit 2 and the clock pulse C (j) and the inverted clock pulse BarC (j) of the second oscillator 27 as a synchronizing signal of the receiving means 31 and 32 Determining means for determining based on;
The clock pulse sent to the shift register 25 is the clock pulse C (j) when the input pulse signal is received by the clock pulse C (j) based on the determination result of the determination means, and the inverted clock pulse BarC. When an input pulse signal is received at (j), a synchronizing signal determining means for determining a synchronizing signal for circuit operation of the shift register 25 as the inverted clock pulse BarC (j);
Consisting of
When an input pulse signal is received by the first receiving means 31, an input pulse signal input to the shift register 25 in synchronization with the clock pulse C (j) from the synchronization signal generating circuit 26 is obtained. Sequential capture,
When an input pulse signal is received by the second receiving means 32, an input pulse signal that is input to the shift register 25 in synchronization with the inverted clock pulse BarC (j) from the synchronization signal generating circuit 26. It is characterized by sequentially taking in .

In the photoelectric sensor according to claim 2 , the synchronization signal generating circuit 26 is
A first flip-flop 31 for outputting a set output by synchronizing the input pulse signal with the clock pulse C (j);
A second flip-flop 32 for outputting a set output in synchronization with the input pulse signal by the inverted clock pulse BarC (j);
When the set output is output from the first flip-flop 31, the output of the inverted clock pulse BarC (j) is blocked, and when the set output is output from the second flip-flop 32, Gate circuits G4 and G6 for passing the inverted clock pulse BarC (j);
When the set output is output from the second flip-flop 32, the output of the clock pulse C (j) is blocked, and when the set output is output from the first flip-flop 31, the clock is output. Gate circuits G5 and G7 for passing the pulse C (j);
A gate circuit G8 that sends an inverted clock pulse BarC (j) or a clock pulse C (j) output from the gate circuits G4 and G6 or the gate circuits G5 and G7 to the shift register 25 as a synchronization signal for circuit operation. It is characterized by that.

The photoelectric sensor according to claim 3 is provided with two first and second inverter gates G1 and G2 through which an input pulse signal from the light receiving element 21 is passed in series, and an input from the second inverter gate G2. A signal having the same polarity as the pulse signal is input to the set input terminal S of the flip-flop 24, and a signal having an opposite polarity to the input pulse signal from the first inverter gate G1 is input to the reset input terminal R of the flip-flop 24. It is characterized by being input to.

In the photoelectric sensor according to claim 4 , an input pulse signal corresponding to the presence or absence of the detection target object 3 is continuously shifted to the shift register 25, and a plurality of stages of flip-flops constituting the shift register 25 The flip-flop 35 is set when all the outputs of the groups 41 to 45 become “1” and reset when all the outputs become “0”.

In the photoelectric sensor according to claim 5 , the Q output of the flip-flop 35 is used as the output of the reflection type photoelectric sensor, and the Qbar output of the flip-flop 35 is used as the output of the transmission type photoelectric sensor. It is said.

In the photoelectric sensor according to claim 6 , an amplifier circuit 12 for amplifying the output of the first oscillator 11 of the light projecting unit 1 is provided, and the amplification degree of the amplifier circuit 12 and the frequency of the first oscillator 11 are variable. Made possible
An amplification circuit 22 that amplifies the output of the light receiving element 21 of the light receiving unit 2 and a waveform shaping circuit 23 that includes a Schmitt circuit that shapes the output of the amplification circuit 22 are provided. The Schmitt level of 23 and the frequency of the second oscillator 27 are variable.

According to the photoelectric sensor according to claim 1, also includes a light projecting unit 1 has established a separate oscillator 27 to the light receiving portion 2, the inverting input pulses coming clock pulse C and (j) a clock pulse BARC ( j) are constantly monitored over the entire period, so that even if the phase of the clock pulse is advanced or delayed with respect to the input pulse, the signal received from the flip-flop 24 is transferred by the shift register 25. The shift can be surely performed, and therefore normal operation can be performed without malfunction.

According to the photoelectric sensor of the second aspect , the synchronization signal generation circuit 26 includes a first flip-flop 31, a second flip-flop 32, gate circuits G4 and G6, gate circuits G5 and G7, Since the gate circuit G4 or G6 or the gate circuit G5 or G7 outputs the inverted clock pulse BarC (j) or the clock pulse C (j) to the shift register 25 as a synchronization signal, the gate circuit G8 is used. The synchronization signal generating circuit 26 can be configured with a simple configuration and at a low cost. Further, the synchronization signal generating circuit 26 and the entire circuit can be integrated into an IC.

According to the photoelectric sensor of the third aspect, the two first and second inverter gates G1 and G2 that pass the input pulse signal from the light receiving element 21 in series are provided, and the second inverter gate G2 A signal having the same polarity as that of the input pulse is input to the set input terminal S of the flip-flop 24, and a signal having a polarity opposite to that of the input pulse signal from the first inverter gate G1 is input to the reset input terminal of the flip-flop 24. Since the signal is input to R, the flip-flop 24 is always reset after the flip-flop 24 is set by the input pulse, and the incoming input pulse signals can be detected without omission.

According to the photoelectric sensor of claim 4 , an input pulse signal corresponding to the presence or absence of the detection target object 3 is continuously shifted to the shift register 25, and a plurality of stages constituting the shift register 25 Since the flip-flop 35 is set when all the outputs of the flip-flops 41 to 45 become “1” and reset when all the outputs become “0”, the optical noise is received. Even if the input pulse signal disappears due to disturbance, the presence or absence of the detection target object 3 can be reliably detected, and malfunction due to optical noise or disturbance can be prevented.

According to the photoelectric sensor of the fifth aspect , the Q output of the flip-flop 35 is used as the output of the reflection type photoelectric sensor, and the Qbar output of the flip-flop 35 is used as the output of the transmission type photoelectric sensor. The same circuit configuration can be used regardless of whether the photoelectric sensor is used as a reflection type or a transmission type, and unlike the case where a circuit is configured separately, the photoelectric sensor can be manufactured at low cost.

According to the photoelectric sensor of the sixth aspect , when the optical noise has the same period as the regular pulse-modulated light, the generated frequencies of the oscillator 11 of the light projecting unit 1 and the oscillator 27 of the light receiving unit 2 are set. Changing by using a variable resistor can prevent malfunction due to optical noise. In this case, the duty ratio of the variable frequency (cycle) is 50%. Further, when optical noise of a certain level or more is generated, the level of the amplifier circuit 12 of the light projecting unit 1 is raised, and the Schmitt level in the waveform shaping circuit 23 of the light receiving unit 2 is raised, so that a normal pulse The modulated light can be received effectively.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a block diagram of an asynchronous photoelectric sensor. As is well known, this asynchronous photoelectric sensor receives a light projecting unit 1 and pulse-modulated light from the light projecting unit 1, and detects it. The light receiving unit 2 determines whether or not the object 3 is present and outputs the determination output.
FIG. 1 is a block diagram of an asynchronous and reflective photoelectric sensor, and FIG. 2 is a block diagram of an asynchronous and transmissive photoelectric sensor. The circuit configuration is the same whether it is a reflection type or a transmission type.

The light projecting unit 1 oscillates an arbitrary frequency and outputs it as a clock pulse (synchronization signal) of the light projecting unit 1, an amplifier circuit 12 that amplifies the output of the oscillator 11, and the amplifier circuit 12 And a light projecting element 13 formed of a light emitting diode that is pulse-modulated with a clock pulse and outputs a pulse signal.
The oscillator 11 can vary the pulse width and frequency, and the amplification circuit 12 can vary the amplification degree.

  The light receiving unit 2 includes a light receiving element 21 including a phototransistor and a photodiode that receives a pulse signal from the light projecting element 13 of the light projecting unit 1, and an amplification circuit 22 that amplifies the output from the light receiving element 21. From the waveform shaping circuit 23 composed of a Schmitt circuit that shapes the output from the amplifier circuit 22, the flip-flop 24 that instantaneously holds the input pulse signal that is output from the waveform shaping circuit 23, and the flip-flop 24 A synchronization signal is created by using a shift register 25 that sequentially takes in the signals of the signal, an input pulse signal from the waveform shaping circuit 23 for shifting the shift register 25, and an original clock pulse from the oscillator 27 before processing. A synchronization signal generating circuit 26 for outputting the clock pulse thus generated to the shift register 25 as a synchronization signal, and this synchronization An oscillator 27 that supplies an original clock pulse before processing to the signal generation circuit 26, and a detection determination circuit 28 that determines the presence or absence of the detection target object 3 by a signal from the shift register 25 and outputs a determination output. ing.

  In the amplification circuit 22 of the light receiving unit 2, the amplification degree can be varied, and the Schmitt level in the waveform shaping circuit 23 can also be varied. Further, in the oscillator 27, the pulse width and the frequency can be changed, and the oscillator 27 and the oscillator 11 of the light projecting unit 1 have the same frequency in setting. Further, the duty ratio of the oscillator 11 of the light projecting unit 1 and the duty ratio of the oscillator 27 of the light receiving unit 2 are the same, and the duty ratio is 50%. Further, circuits such as the power supply unit of the light projecting unit 1 and the light receiving unit 2 are omitted.

  FIG. 3 shows a specific circuit diagram of the synchronization signal generating circuit 26 and the like. The shift register 25 is composed of, for example, five D-type flip-flops 41 to 45. Although the number of flip-flops 41 to 45 of the shift register 25 is five here, the number of stages is not limited to this, and the number of stages is arbitrary. Further, the Q outputs of the flip-flops 41 to 45 of the shift register 25 are SF1 to SF5, respectively.

  An input pulse signal, which is a signal from the waveform shaping circuit 23, is input to the point a in the figure, and is input to the set input terminal S of the RS flip-flop 24 via the inverter gate G1 and the inverter gate G2. The output signal of the inverter gate G1 is input to the reset input terminal R of the flip-flop 24. The signal from the output terminal Q of the flip-flop 24 is input to the D input terminal of the first-stage flip-flop 41 of the shift register 25.

The synchronization signal generation circuit 26 includes an RST type first flip-flop 31 and a second flip-flop 32, three inverter gates G3 to G5, two AND gates G6 and G7, and an OR gate G8. Yes.
The output of the inverter gate G 1 is input to the reset input terminal R of the first flip-flop 31 and the reset input terminal R of the second flip-flop 32, similarly to the flip-flop 24. The output of the inverter gate G2 is input to the set input terminal S of the first flip-flop 31 and the set input terminal S of the second flip-flop 32, respectively.

A clock pulse C (j) having a duty ratio of 50% as shown in FIG. 5E is output from the oscillator 27, and this clock pulse C (j) is applied to the trigger terminal T of the first flip-flop 31. While being input, it is input to one input terminal of the AND gate G7.
A clock pulse obtained by inverting the clock pulse C (j) from the oscillator 27 by the inverter gate G3 is input to the trigger terminal T of the second flip-flop 32 as an inverted clock pulse BarC (j), and the AND gate G6 It is input to one input terminal.

The Q output of the first flip-flop 31 is inverted through the inverter gate G4 and input to the other input terminal of the AND gate G6, and the Q output of the second flip-flop 32 is input through the inverter gate G5. Is inverted and input to the other input terminal of the AND gate G7.
The outputs of the AND gate G6 and the AND gate G7 are respectively input to the OR gate G8, and the clock pulse C (j) or the clock pulse BarC (j) is output from the output of the OR gate G8 as a synchronizing signal to each flip-flop 41- It is input to 45 clock terminals CLK.

Note that the circuit diagram shown in the drawings attached to the specification of the present invention is not a design drawing at the time of actual circuit manufacture, and therefore does not show circuit elements for timing adjustment. Only the logic circuits necessary for explaining the content of the invention are described.
Inverter gates G1 and G2 are drawn as representative circuit diagrams. When manufacturing an actual circuit, the timing of the input signal is adjusted according to the time required for setting or resetting the flip-flop 24 (response speed of the flip-flop element to be used). Both the gate G1 and the inverter gate G2 are connected in series with one or more odd number of inverters.

FIG. 4 shows a specific circuit diagram of the shift register 25 and the detection determination circuit 28. The detection determination circuit 28 includes two AND gates G10 and G11, five inverter gates G21 to G25, and an RS flip-flop 35.
The Q outputs (SF1 to SF5) of the flip-flops 41 to 45 of the shift register 25 are respectively input to the input terminals of the AND gate G10 and are also input to the input terminals of the AND gate G11 via the inverter gates G21 to G25. Has been.

  The output of one AND gate G10 is input to the set input terminal S of the flip-flop 35, and the output of the other AND gate G11 is input to the reset input terminal R of the flip-flop 35. The Q output of the flip-flop 35 is used to output as an object detection signal of the reflection type photoelectric sensor, and the Qbar output of the flip-flop 35 is used to output as an object detection signal of the transmission type photoelectric sensor. It is done.

Here, in the case of the reflection type photoelectric sensor, as shown in FIG. 1, when the light receiving element 21 does not receive the pulse signal, the detection target object 3 does not exist, and the pulse signal is continuously received. Is the case where the detection target object 3 exists.
On the contrary, in the transmissive photoelectric sensor, as shown in FIG. 2, when the detection target object 3 does not exist, a pulse signal is received, and when the detection target object 3 exists. Is a case where the pulse-modulated light from the light projecting element 13 is blocked by the detection object 3 and does not receive the pulse signal.

Next, the operations of the flip-flop 24 and the synchronization signal generation circuit 26 shown in FIG. 3 of the present invention will be described. The asynchronous photoelectric sensor is different from the synchronous photoelectric sensor in that the light projecting unit 1 and the light receiving unit 2 are used. Are individually provided with the oscillators 11 and 27, respectively, and therefore it is necessary to devise processing of the clock pulse as the synchronization signal.
In the synchronous photoelectric sensor, since the same clock pulse from one oscillator is used, the received input pulse signal and the clock pulse for the signal processing circuit on the light receiving unit side are synchronized, but the asynchronous photoelectric sensor In the photoelectric sensor, the input pulse signal continuously arriving from the light projecting unit 1 side and the signal processing circuit clock pulse on the light receiving unit 2 side are not identical and are not synchronized. Ingenuity is required for the method.

That is, on the light receiving unit 2 side, as shown in FIG. 3, the input pulse is stored in the flip-flop 24 and shifted to the shift register 25 in the subsequent stage. How is the input pulse stored in the flip-flop 24? It is important to shift with a simple clock pulse.
If the object detection signal is output when five input pulse signals are continuously input, the input pulse is reliably stored in the flip-flop 24, and the input pulse is set in the flip-flop 24. Thereafter, the flip-flop 24 must be reset before the next input pulse arrives. Then, the signal set by the flip-flop 24 is shifted to the subsequent shift register 25 by a clock pulse.

  Also, the reception of the input pulse is constantly monitored by the clock pulse on the light receiving unit 2 side and the inverted signal of the clock pulse. The input is either the clock pulse C (j) or the inverted clock pulse BarC (j). Depending on whether the pulse is received, the clock pulse C (j) or the inverted clock pulse BarC (j) for shifting the outputs of the flip-flops 41 to 45 of the shift register 25 is selectively used, and each flip-flop of the shift register 25 is used. The signals 41 to 45 are surely shifted. This is the gist of the present invention.

  First, the method of capturing the input pulse (light reception signal) in the flip-flop 24 and automatically selecting the clock pulse C (j) or the inverted clock pulse BarC (j) of the shift register 25 will be described with reference to FIGS. explain. Note that the waveforms at points a to k in FIG. 3 correspond to (a) to (k) in FIGS. 5 and 6.

FIG. 5 shows a timing chart of each part when the input pulse is captured by the clock pulse C (j) output from the oscillator 27. When the input pulse shown in FIG. ), An inverted signal slightly delayed by the inverter gate G1 is output. Further, the input pulse is output with a slight delay by the inverter gate G2 (see FIG. 5C).
In an initial state when the power is turned on, the flip-flops 24, 31, and 32 are in a reset state. When the first input pulse A1 is received, the flip-flop 24 is turned on by the set pulse S1 from the inverter gate G2. Set. Thereafter, the flip-flop 24 is reset by a reset pulse R1 (see FIG. 5B) from the inverter gate G1. Thereafter, as shown in FIG. 5D, the flip-flop 24 similarly repeats the setting and resetting every time it receives the input pulse A.

Here, the clock pulse C (j) having the same frequency (cycle) as the input pulse A and the duty ratio shown in FIG. 5E is 50% is inputted to the trigger terminal T of the first flip-flop 31. Further, an inverted clock pulse BarC (j) (see FIG. 5F) obtained by inverting the clock pulse C (j) by the inverter gate G3 is input to the trigger terminal T of the second flip-flop 32. .
In FIG. 5, in the case of the clock pulse C (j), the first flip-flop 31 is held in the set state (see FIGS. 5E and 5G), and the Q output of the first flip-flop 31 is at the H level. Output.

  As shown in FIG. 5 (f), since the level input to the set input terminal S of the second flip-flop 32 is L level at the time of rising of the inverted clock pulse BarC (j), The flip-flop 32 takes in the L level, and the Q output is at the L level as shown in FIG.

The Q output of the first flip-flop 31 is at the H level as described above (see FIG. 5G), the output of the inverter gate G4 is at the L level, and the output of the AND gate G6 is in the L level state. Thus, the inverted clock pulse BarC (j) is not output (see FIG. 5 (i)).
The Q output of the second flip-flop 32 is at L level (see FIG. 5 (h)). Therefore, the output of the inverter gate G5 is at H level, and the output of the AND gate G7 is shown in FIG. 5 (j). Thus, the clock pulse C (j) is output. Then, the clock pulse C (j) is input to the OR gate G8 that supplies the clock pulse of the shift register 25, and the output of the OR gate G8 is the clock pulse C (j) as shown in FIG. ) Is output.

  The clock pulse C (j) from the OR gate G8 is input to the clock terminals of the flip-flops 41 to 45 as a synchronizing signal of the shift register 25, and an H level signal corresponding to the input pulse A is supplied to the clock pulse C (j ) Shift every time.

FIG. 6 shows a timing chart when the phase of the clock pulse from the oscillator 27 is shifted with respect to the input pulse A and the input pulse A is captured by the inverted clock pulse BarC (j). d) is the same as FIG. 5, but the phases of the clock pulse C (j) and the inverted clock pulse BarC (j) are inverted as shown in (e) and (f).
In the case of the inverted clock pulse BarC (j), the second flip-flop 32 is held in the set state (see FIGS. 6F and 6H), and the Q output of the second flip-flop 32 outputs H level. Yes. Since the level input to the first flip-flop 31 is L level at the rising edge of the clock pulse C (j) shown in FIG. 6E, the first flip-flop 31 takes in the L level and Q The output is L level (see FIG. 6G).

In this state, as shown in FIG. 3, since the Q output of the second flip-flop 32 is at the H level, the output of the AND gate G5 is at the L level. Therefore, a clock pulse is applied to one input terminal of the AND gate G7. Even if C (j) is input, the output of the AND gate G7 maintains the L level.
Since the Q output of the first flip-flop 31 is L level, the output of the AND gate G4 becomes H level, and the inverted clock pulse BarC (j) is output from the output of the AND gate G6.

Then, an inverted clock pulse BarC (j) is input from the AND gate G6 to the OR gate G8 that supplies the clock pulse of the shift register 25, and as shown in FIG. 6 (k), the inverted clock pulse BarC (j ) Is output.
This inverted clock pulse BarC (j) is input to the clock terminals CLK of the flip-flops 41 to 45 of each stage as a synchronizing signal of the shift register 25, and an H level signal corresponding to each input pulse A is inverted clock pulse BarC (j ) Shift every time.

  In this manner, each time the input pulse A arrives, the flip-flop 24 is set, and then the flip-flop 24 is immediately reset to hold the standby state for the next incoming pulse A. Even when the phase of the clock pulse (clock pulse C (j), inverted clock pulse BarC (j)) used when receiving the input pulse A is shifted, either C (j) or BarC (j) With the clock pulse, the light reception signal set by the flip-flop 24 can be reliably shifted in the shift register 25, so that it can operate normally without malfunction.

FIG. 7 shows that, according to the present invention, the clock pulse generated by the oscillator 11 of the light projecting unit 1 (becomes a light reception signal) and the clock pulse generated by the oscillator 27 of the light receiving unit 2 (C (j) and BarC (j ) And (becomes a clock pulse for the signal processing circuit).
That is, the timing chart shows that the received light signal (input pulse) can be accurately taken in regardless of the phase of the clock pulse.
First, A in FIG. 7 shows a case where the phase of the clock pulse C (j) is advanced with respect to the light reception signal (input pulse). In this case, the light reception signal is represented by the inverted clock pulse BarC (j). take in.

FIG. 7B shows a case where the phase of the clock pulse is delayed with respect to the light reception signal, and the falling edge of the light reception signal and the rising edge of the inverted clock pulse BarC (j) are almost the same. In this case, the inverted clock pulse BarC (j ) Capture the received light signal.
FIG. 7C shows the case where the clock pulse is further delayed and the rising edge of the light reception signal and the clock pulse C (j) is almost the same. In this case, the light reception signal is captured by the clock pulse C (j). .

D in FIG. 7 shows a case where the clock pulse is delayed with respect to the light reception signal, and the light reception signal is captured by the clock pulse C (j).
E in FIG. 7 is a case where the clock pulse is further delayed with respect to the light reception signal, and is a case where the fall of the light reception signal and the rise of the clock pulse C (j) are substantially the same. ) Capture the received light signal.

  F in FIG. 7 shows a case where the rising edge of the light receiving signal and the rising edge of the inverted clock pulse BarC (j) are substantially the same, and the received light signal is captured by the inverted clock pulse BarC (j). And after this F, it returns to said A and repeats this.

  The selection of the clock pulse C (j) and the inverted clock pulse BarC (j) as the synchronization signals used in the shift register 25 shown in FIG. 3 is automatically performed by the synchronization signal generation circuit 26, and the incoming input pulses (Light reception signal) is reliably set and reset by the flip-flop 24, and the clock pulse C (j) or the inverted clock pulse BarC (j) automatically selected by the synchronization signal generation circuit 26 for each input pulse. Thus, the flip-flops 41 to 45 of the shift register 25 can be shifted.

  In the timing chart shown in FIG. 7, when the rise and fall between the input pulse (light reception signal) and the clock pulse are the same on the drawing, the relative phase shift between the two causes The H level or L level of the input pulse is captured by the clock pulse.

  As described above, the frequency (cycle) of the oscillator 11 of the light projecting unit 1 and the oscillator 27 of the light receiving unit 2 are the same and the duty ratio is 50%, so that the light receiving unit 2 side with respect to the input pulse. Even when the phase of the clock pulse is advanced or delayed, the signal in the shift register 25 can be sequentially shifted in synchronization with the input pulse.

Next, the reason why the periods of the two oscillators 11 and 27 are the same and the duty ratio is 50% will be described. 8 to 10 show a case where the cycle of the input pulse and the clock pulse is the same, the duty ratio of the input pulse is 50% or less, and the duty ratio of the clock pulse is 50%.
FIG. 8 shows a case where the position of the input pulse and the rising point of the clock pulse C (j) overlap. In this case, the input pulse can be captured by the clock pulse C (j).

However, as shown in FIG. 9, the phase of the clock pulse is delayed with respect to the input pulse, and the rising edge of the clock pulse C (j) and the inverted clock pulse BarC (j) is located at a position where the input pulse does not exist. In this case, the input pulse cannot be captured even with the clock pulse C (j) or the inverted clock pulse BarC (j).
Therefore, the first flip-flop 31 and the second flip-flop 32 shown in FIG. 3 cannot be set, and the Q outputs of the flip-flops 31 and 32 become L level, and the two AND gates G6 and 7 respectively An inverted clock pulse BarC (j) and a clock pulse C (j) are output. As a result, the inverted clock pulse BarC (j) and the clock pulse C (j) are simultaneously input to the clock terminals CLK of the flip-flops 41 to 45 of the shift register 25, so that the shift register 25 operates normally. Can not be made. Therefore, although the input pulse has arrived, the input pulse cannot be detected.

  As shown in FIG. 10, when the phase of the clock pulse is further delayed with respect to the input pulse and the rising edge of the inverted clock pulse BarC (j) overlaps with the input pulse, the inverted clock pulse BarC (j ) Can be used to capture input pulses.

  Thus, when the duty ratio of the input pulse is set to 50% or less, both the clock pulse C (j) or the inverted clock pulse BarC (j) are input during the L level period of the input pulse. It cannot be imported. Therefore, the duty ratio of the input pulse needs to be 50%.

  Next, as shown in FIGS. 11 to 13, the case where both the duty ratios of the input pulse and the clock pulse C (j) are 50% or less will be described. First, FIG. 11 shows a case where the position of the input pulse overlaps the rising edge of the clock pulse C (j). In this case, the input pulse can be captured by the clock pulse C (j).

However, as shown in FIG. 12, the phase of the clock pulse is delayed with respect to the input pulse, and the rising edge of the clock pulse C (j) and the inverted clock pulse BarC (j) is located at a position where the input pulse does not exist. Clock pulse C (j)
Or the input pulse cannot be captured even with the inverted clock pulse BarC (j). For this reason, the input pulse cannot be detected even though the input pulse has arrived for the reason described above.

  As shown in FIG. 13, when the phase of the clock pulse is further delayed with respect to the input pulse and the rising edge of the inverted clock pulse BarC (j) overlaps with the input pulse, the inverted clock pulse BarC (j ) Can be used to capture input pulses.

  Thus, when the duty ratio of both the input pulse and the clock pulse C (j) is 50% or less, the clock pulse C (j) or the inverted clock pulse BarC ( Both of j) cannot capture an input pulse. Therefore, both the duty ratio of the input pulse and the clock pulse C (j) must be 50%.

Next, as shown in FIGS. 14 to 16, the case where the duty ratio of the input pulse is 50% and the duty ratio of the clock pulse C (j) is 50% or less will be described.
FIG. 14 shows a case where the position of the input pulse and the rising point of the clock pulse C (j) overlap, and in this case, the input pulse can be captured by the clock pulse C (j).

However, as shown in FIG. 15, the phase of the clock pulse is delayed with respect to the input pulse, and the rising edge of the clock pulse C (j) and the inverted clock pulse BarC (j) is located at a position where the input pulse does not exist. Clock pulse C (j)
Or the input pulse cannot be captured even with the inverted clock pulse BarC (j). For this reason, the input pulse cannot be detected even though the input pulse has arrived for the reason described above.

  As shown in FIG. 16, when the phase of the clock pulse is further delayed with respect to the input pulse and the rising edge of the inverted clock pulse BarC (j) overlaps with the input pulse, the inverted clock pulse BarC (j ) Can be used to capture input pulses.

  Thus, even if the duty ratio of the input pulse is 50%, if the duty ratio of the clock pulse C (j) is 50% or less, the clock pulse C (j ) Or the inverted clock pulse BarC (j) cannot be input. Therefore, both the duty ratio of the input pulse and the clock pulse C (j) must be 50%.

  FIG. 17 and FIG. 18 show a case where the input pulse is captured only by the clock pulse C (j) from the oscillator 27 of the light receiving unit 2, unlike the present embodiment. FIG. 17 shows the case where the position of the input pulse and the rising point of the clock pulse C (j) overlap. In this case, the input pulse can be captured by the clock pulse C (j).

  However, as shown in FIG. 18, when the phase of the clock pulse is delayed with respect to the input pulse and the rising edge of the clock pulse C (j) is located at a position where the input pulse does not exist, the clock pulse C ( The input pulse cannot be captured in j). Therefore, the input pulse cannot be detected although the input pulse has arrived.

That is, when the synchronization signal generating circuit 26 does not exist in FIG. 3 and the clock pulse C (j) from the oscillator 27 is directly input to the clock terminals CLK of the flip-flops 41 to 45 of the shift register 25, FIG. As shown in FIG. 5, since the input pulse is at the L level at the rising edge of the clock pulse C (j), the L level signal is sequentially shifted.
Therefore, although the input pulses arrive continuously, the L level portion of the input pulses is shifted, and the input pulses cannot be accurately detected and captured.

  In particular, when the input pulse is attempted to be captured only by the clock pulse C (j) without using the inverted clock pulse BarC (j), the phase of the clock pulse C (j) advances relatively with respect to the input pulse. As shown in FIG. 17, the input pulse cannot be captured unless the input pulse exists at the rising edge of the clock pulse C (j).

  Therefore, as shown in FIG. 18, if the input pulse is not located at the rising edge of the clock pulse C (j) even though the input pulse has arrived, the input is made with the clock pulse C (j). The pulse cannot be detected. That is, after the rising edge of the clock pulse C (j) deviates from the input pulse, the phase of the clock pulse C (j) gradually delays with respect to the input pulse, and the rising edge of the clock pulse C (j) becomes the input pulse. Until they overlap, a malfunction occurs in which the input pulse cannot be captured by the clock pulse C (j).

As described above, in this embodiment, the synchronization signal generation circuit 26 inverts the input pulse signal from the light receiving element 21 to the clock pulse C (j) of the oscillator 27 of the light receiving unit 2 or the clock pulse C (j). It is determined which one of the inverted clock pulses BarC (j) is received synchronously, and when the clock pulse sent to the shift register 25 is received by the clock pulse C (j), the clock pulse C (j When the pulse signal is received by the inverted clock pulse BarC (j), the shift register 25 is synchronized as the inverted clock pulse BarC (j).
Thereby, even if an oscillator 27 separate from the light projecting unit 1 is provided on the light receiving unit 2 side, the incoming input pulse is constantly monitored over the entire period by the clock pulse C (j) and the inverted clock pulse BarC (j). Therefore, even if the phase of the clock pulse is advanced or delayed with respect to the input pulse, the signal fetched from the flip-flop 24 can be surely shifted by the shift register 25. Can be made.

As described above, the input pulses input through the flip-flop 24 are sequentially used in accordance with the synchronization signal (clock pulse C (j) or inverted clock pulse BarC (j)) automatically selected by the synchronization signal generation circuit 26. It will be shifted. Next, the operation of the detection determination circuit 28 that determines the presence / absence of the detection target object 3 based on the signal from the shift register 25 will be described with reference to FIGS. 4 and 19.
The operation will be described in the case of the reflection type shown in FIG. 1 and the clock pulse being C (j). Since it is a reflection type, when the detection target object 3 is not detected, the light receiving element 21 of the light receiving unit 2 does not receive the input pulse, and when the detection target object 3 is detected, the light projection unit 1 emits light. This is a case where the pulse-modulated light from the optical element 13 strikes the reflection target object 3 and is reflected, and the light-receiving element 21 receives the pulse-modulated light reflected from the detection target object 3, that is, the input pulse.

  The points a to l in FIG. 4 correspond to the waveforms (a) to (l) shown in FIG. First, as shown in FIG. 19A, the input pulse A1 is inputted to the set input terminal S of the flip-flop 24 at time t0, and at the same time, the Q output becomes H level as shown in FIG. 19B. Next, as shown in FIGS. 4 and 19C, the clock pulse C (j) automatically selected as described above is supplied from the OR gate G8 to the clock terminals CLK of the flip-flops 41 to 45 of the shift register 25. Has been entered.

At time t1, the H level signal of the Q output of the flip-flop 24 is taken into the first flip-flop 41 of the shift register 25 at the rising edge of the clock pulse C (j), and the Q output SF1 of the flip-flop 41 becomes It becomes the H level (see FIG. 19D).
Next, the second input pulse A2 arrives and is taken in by the clock pulse C (j) at time t2, and at the same time, the Q output SF1 is shifted to the second-stage flip-flop 42 and the Q output SF2 becomes H level. Become. Similarly, the third input pulse A3 is taken in at time t3, and further, the fourth input pulse A4 is taken in at time t4, and the Q outputs SF2 and SF3 of the flip-flops 42 and 43 become the flip-flops 43 in the subsequent stage. Shifted to 44.

Next, when the fifth input pulse A5 is taken into the flip-flop 41 of the shift register 25 by the clock pulse C (j) at time t5, the Q outputs SF1 of the flip-flops 41 to 45 of the shift register 25. ... SF5 are all at the H level, so that the output of the AND gate G10 is at the H level as shown in FIG.
When the Q outputs SF1 to SF5 of the flip-flops 41 to 45 of the shift register 25 become H level, the input of the AND gate G11 becomes L level by the inverter gates G21 to G25 shown in FIG. Is at the L level (see FIG. 19J).

  When the output of the AND gate G10 becomes H level, the set input terminal S of the flip-flop 35 shown in FIG. 4 becomes H level, and the Q output of the flip-flop 35 becomes H level as shown in FIG. 19 (k). (See time t5). When the Q output of the flip-flop 35 becomes H level, it means that five input pulses A arrive continuously at a predetermined cycle, and a determination detection output indicating that the detection target object 3 has been detected is output. It will be. Note that the Qbar output of the flip-flop 35 changes from the H level to the L level at time t5 (see FIG. 19L).

  In the above case, when the five input pulses A are continuously received at a predetermined cycle, the detection target object 3 remains. In this detection of the detection target object 3, it is assumed here that five input pulses A are received, but the number of input pulses A can be arbitrarily set. In such a case, the number of flip-flop stages of the shift register 25 is also set corresponding to the number of input pulses A.

Next, when the detection target object 3 passes and the input pulse A is not received, the Q output of the flip-flop 24 becomes L level at time t6, and this L level is shifted by the clock pulse C (j). It is taken into the register 25. Then, as shown in FIG. 19D, the Q output of the first-stage flip-flop 41 of the shift register 25 becomes L level.
When the Q output of the flip-flop 41 becomes L level, the output of the AND gate G10 becomes L level as shown in FIG. At this time, the Q output of the flip-flop 35 remains at the H level.

Since the input pulse A does not exist from time t7 to time t9, the L level is shifted in the shift register 25 by the clock pulse C (j), and the Q outputs SF1 to SF1 of the flip-flops 41 to 44 of the shift register 25 are shifted. SF4 is at L level.
Next, since the input pulse A does not exist at time t10, the clock pulse C (j)
Since the L level of the Q output of the flip-flop 24 is taken in, the Q outputs SF1 to SF5 of the flip-flops 41 to 45 of the shift register 25 all become the L level.

When the Q outputs SF1 to SF5 of the flip-flops 41 to 45 of the shift register 25 all become L level, the inputs of the AND gate G11 all become H level, so the output of the AND gate G11 becomes H level (FIG. 19). (See (j)).
When the Q output of the AND gate G11 becomes H level, an H level signal is input to the reset input terminal R of the flip-flop 35, and the flip-flop 35 is reset. When the flip-flop 35 is reset, the Q output of the flip-flop 35 becomes L level at time t10 (see FIG. 19 (k)), and the Qbar output becomes H level (see FIG. 19 (l)).

  Here, when five input pulses A are not received in succession, the detection target object 3 does not exist. For this reason, the Q output of the flip-flop 35 outputs an L level, thereby detecting the detection target object. 3 is not detected. Then, the flip-flop 35 is in a reset state and waits for the next input pulse A to be received.

When the circuit of the present invention is used as a transmissive photoelectric sensor, if a predetermined number of input pulses are not continuously received, the detection target object 3 is present and a predetermined number of input pulses are continuously received. In the case where it is determined, the detection target object 3 is absent. Therefore, when the Qbar output of the flip-flop 35 shown in FIG. 4 becomes H level, the detection target object 3 is present, and when the Qbar output is L level, the detection target object 3 is absent. .
Therefore, by properly using the Q output and Qbar output of the flip-flop 35, the same circuit configuration can be applied to a reflection type photoelectric sensor and a transmission type photoelectric sensor.

  In the above description, the case where the clock pulse is C (j) has been described. However, since the same applies to the case where the clock pulse is the inverted clock pulse BarC (j), detailed description thereof is omitted.

  Next, a case where the light receiving element 21 receives disturbance light (optical noise) other than the regular input pulse signal will be described with reference to FIG. FIG. 20A shows an input pulse. However, in this state, the input pulse is not received. As shown in FIG. 20B, the light receiving element 21 receives three pulses of optical noise, The case where it outputs from the Q output of the flip-flop 24 is shown.

First, the first optical noise N1 is received, and is taken into the first-stage flip-flop 41 of the shift register 25 by the clock pulse C (j) at time t1, and the Q output SF1 of the flip-flop 41 becomes H level. (See FIG. 20D).
Next, the second optical noise N2 is received and taken into the shift register 25 by the clock pulse C (j) at time t2, and the Q output SF2 of the second-stage flip-flop 42 becomes H level ((e )reference).

At time t3, since no optical noise exists, the L level at that time is taken into the flip-flop 41 of the shift register 25, and the Q output SF1 of the flip-flop 41 becomes L level. At this time, since the shift register 25 is sequentially shifted by the clock pulse C (j), the Q output SF3 of the third-stage flip-flop 43 becomes H level.
When the third optical noise N3 is received, the optical noise N3 is not taken into the shift register 25 because it does not overlap with the rising edge of the clock pulse C (j). Then, from time t4 to time t6, the shift register 25 is shifted by the clock pulse C (j). At time t7, the Q outputs SF1 to SF5 of all the flip-flops 41 to 45 of the shift register 25 are L Become a level.

  At time t7, the Q outputs SF1 to SF5 of the respective flip-flops 41 to 45 of the shift register 25 become L level, so that the output of the AND gate G11 becomes H level, and this H level signal becomes the reset input of the flip-flop 35. Input to terminal R. However, while the optical noise is occurring, the Q output and Qbar output of the flip-flop 35, which are the judgment outputs, hold the state before the occurrence of the optical noise, so FIG. 20 (k) (l) There is no change. That is, the previous state is retained.

  In this way, even if a plurality of optical noises are received successively, the optical register is shifted by the shift register 25 by two optical noises N1 and N2 in order to make the periods of the optical noise, the input pulse and the clock pulse different. However, the Q outputs of the flip-flops 41 to 45 of the shift register 25 are not all at the H level. Therefore, even if optical noise is received, the determination output of the detection target object 3 is erroneously output. Absent.

Here, when the optical noise has the same period as the regular pulse-modulated light, the frequency generated by the oscillator 11 of the light projecting unit 1 and the oscillator 27 of the light receiving unit 2 is changed using a variable resistor, It is possible to prevent malfunction due to optical noise. In this case, the duty ratio of the variable frequency (cycle) is 50%.
Further, when optical noise of a certain level or more is generated, the level of the amplifier circuit 12 of the light projecting unit 1 is raised, and the Schmitt level in the waveform shaping circuit 23 of the light receiving unit 2 is raised, so that a normal pulse The modulated light can be received effectively.

  Next, a case where the regular pulse modulated light partially disappears due to some disturbance and the input pulse partially disappears will be described with reference to FIG. As shown in FIG. 21 (a), five input pulses A1 to A5 should be received originally, but foreign matters such as dust other than the detection target object 3 fly by the wind and the like, and pulse modulated light. This is a case where the light path of the light receiving unit 2 is blocked from receiving the regular pulse signal. The example shown in FIG. 21 shows a case where the third and fourth input pulses A3 and A4 are not received.

The first input pulse A1 and the second input pulse A2 are captured by the clock pulse C (j) at time t1 and time t2, respectively, and Q outputs SF1 and SF2 of the flip-flops 41 and 42 of the shift register 25 are obtained. Shift each one.
At time t3, since the input pulse A3 is not received, the output of the flip-flop 24 is L level. Therefore, at time t3, the first-stage flip-flop 41 of the shift register 25 is shifted by the clock pulse C (j). The L level is taken in, and the Q output SF1 of the flip-flop 41 becomes the L level (see FIG. 21D). At this time, the flip-flops 42 and 43 of the shift register 25 are shifted and the Q outputs SF2 and SF3 are at the H level (see (e) and (f)).

  Next, since the fourth input pulse A4 is not received, the output of the flip-flop 24 is at the L level. Therefore, at the time t4, the first-stage flip-flop of the shift register 25 by the clock pulse C (j). The L level is input to the flip-flop 41, and the Q output SF1 of the flip-flop 41 becomes the L level (see FIG. 21D). At this time, the flip-flops 43 and 44 of the shift register 25 are shifted, and the Q outputs SF3 and SF4 are at the H level (see (f) and (g)).

Since the fifth input pulse A5 is received, at time t5, the first-stage flip-flop 41 of the shift register 25 receives the H level signal by the clock pulse C (j), and the Q level of the flip-flop 41 is increased. The output SF1 becomes H level (see FIG. 21D).
Further, the Q output SF5 of the fifth flip-flop 45 of the shift register 25 is also at the H level (see (h)). Even when the fifth input pulse A5 is received, at time t5, the Q outputs SF2 and SF3 of the flip-flops 42 and 43 of the shift register 25 are at the L level, so the output of the AND gate G10 is at the L level. Yes (see FIG. 21 (i)).

The flip-flops 41 to 45 of the shift register 25 sequentially shift the L level of the Q output of the flip-flop 24 until the time t10 when the fifth clock pulse C (j) rises after the time t6. At time t10, the Q outputs SF1 to SF5 of the flip-flops 41 to 45 of the shift register 25 are all at the L level.
Since the Q outputs SF1 to SF5 of the flip-flops 41 to 45 of the shift register 25 become L level at time t10, the output of the AND gate G11 becomes H level, and this H level signal becomes the reset input of the flip-flop 35. Input to terminal R. However, while the disturbance is occurring, the Q output and Qbar output of the flip-flop 35, which are the judgment outputs, hold the state before the occurrence of the disturbance, and are shown in FIGS. 21 (k) and (l). There is no change. That is, the previous state is retained.

In FIG. 21, five normal input pulses are continuous. However, when the detection target object 3 is detected, more input pulses are continuously received. The input pulses are continuously received after A5.
For this reason, when five consecutively input pulses from the input pulse A5 are received, the detection target object 3 is detected, and as shown in FIG. Even when it disappears, the detection target object 3 is actually detected without hindrance.

  FIG. 22 shows another circuit example of the detection determination circuit 28 with respect to FIG. 4. The Qbar outputs of the flip-flops 41 to 45 of the shift register 25 are ANDed with the AND gate G12, and the output of the AND gate G12 is output. This is input to the reset input terminal R of the flip-flop 35. The circuit operation is the same as in FIG.

Here, if the pulse-modulated light from the light projecting unit 1 coincides with the optical noise, the resistors that determine the time constants of the oscillators 11 and 27 and the resistors in the capacitors are made variable, and the pulse-modulated light By changing the period, the pulse peak value, etc., it is possible to freely and easily generate a pulse completely different from optical noise. Thereby, even when the pulse-modulated light and the optical noise match, the optical noise can be completely eliminated.
In particular, by using a potentiometer or other means to freely change the period of pulse-modulated light, pulse peak value, etc., the more adjacent photoelectric sensors are placed adjacent to each other, the light-receiving signals do not interfere with each other. Even in the case of performing, for example, it can be performed on the production line of a factory, and interference between photoelectric sensors can be prevented.

Further, the synchronization signal generation circuit 26 which is the gist of the present invention is configured by a first flip-flop 31, a second flip-flop 32, inverter gates G1 to G5, AND gates G6 and G7, and an OR gate G8. Therefore, the synchronization signal generating circuit 26 can be configured with a simple configuration and at a low cost.
In addition to the synchronization signal generating circuit 26, the circuit of the entire light projecting unit 1 excluding the light projecting element 13 and the circuit of the entire light receiving unit 2 excluding the light receiving element 21 in the circuit shown in FIG. be able to.

  Further, since the Q output of the flip-flop 35 is used as the output of the reflection type photoelectric sensor and the Qbar output of the flip-flop 35 is used as the output of the transmission type photoelectric sensor, even when the photoelectric sensor is used as the reflection type. Even when used as a transmission type, the same circuit configuration can be used, and unlike a case where a circuit is configured separately, a photoelectric sensor can be manufactured at low cost.

In addition, although the case where the synchronizing signal generation circuit 26 of the present invention is applied to a photoelectric sensor has been described, it is not limited to the photoelectric sensor. For example, mutual synchronization control between independent systems using an optical pulse signal or an electronic pulse signal can be performed between a plurality of independent electronic systems each independently having an individual oscillator and a signal processing circuit.
In the prior art, in an electronic system that has its own power supply unit, pulse generation unit, digital circuit for transmission / reception of pulse signals, signal processing and control, and other circuit units, for example, between two electronic systems , Complete linkage signal processing and control between two independent electronic systems, which can only be achieved by completely synchronizing the individual clock pulse signals generated by the individual pulse generators, has not been realized . In the prior art, it is impossible to completely synchronize two different clock pulse signals generated by the individual pulse generator (the signal operation in a digital circuit is often synchronized with a dedicated clock pulse). And most of the more complex digital circuits do so.)
In the present invention, as a specific example of a method that can completely synchronize two individual clock pulse signals between two electronic systems, “asynchronous type two independent mini electronic systems” The invention is described between the light projecting unit and the light receiving unit of the photoelectric sensor.

It is a block diagram of the photoelectric sensor in the reflection type in the embodiment of the present invention. It is a block diagram of the photoelectric sensor in the case of the transmission type in the embodiment of the present invention. FIG. 3 is a specific circuit diagram of a synchronization signal generation circuit and the like in the embodiment of the present invention. It is a specific circuit diagram of the shift register and the detection determination circuit in the embodiment of the present invention. (A)-(k) is a timing chart when the input pulse in embodiment of this invention is taken in with the clock pulse C (j). (A)-(k) is a timing chart when the input pulse in the embodiment of the present invention is captured by the inverted clock pulse BarC (j). It is explanatory drawing which shows taking in an input pulse correctly no matter how the phase of the clock pulse in the embodiment of this invention has shifted | deviated. (A)-(c) is explanatory drawing when the duty ratio of the input pulse in embodiment of this invention is 50% or less. (A)-(c) is explanatory drawing when the duty ratio of the input pulse in embodiment of this invention is 50% or less. (A)-(c) is explanatory drawing when the duty ratio of the input pulse in embodiment of this invention is 50% or less. (A)-(c) is explanatory drawing at the time of making the duty ratio of the input pulse and a clock pulse into 50% or less in embodiment of this invention. (A)-(c) is explanatory drawing at the time of making the duty ratio of the input pulse and a clock pulse into 50% or less in embodiment of this invention. (A)-(c) is explanatory drawing at the time of making the duty ratio of the input pulse and a clock pulse into 50% or less in embodiment of this invention. (A)-(c) is explanatory drawing when the duty ratio of a clock pulse in embodiment of this invention is 50% or less. (A)-(c) is explanatory drawing when the duty ratio of a clock pulse in embodiment of this invention is 50% or less. (A)-(c) is explanatory drawing when the duty ratio of a clock pulse in embodiment of this invention is 50% or less. (A) (b) is explanatory drawing at the time of using only the clock pulse C (j) in embodiment of this invention. (A) (b) is explanatory drawing at the time of using only the clock pulse C (j) in embodiment of this invention. It is a timing chart which shows operation | movement of the detection determination circuit in embodiment of this invention. It is a timing chart at the time of receiving the optical noise in embodiment of this invention. 6 is a timing chart when an input pulse disappears due to a disturbance in the embodiment of the present invention. It is a circuit diagram which shows the other circuit example of the detection determination circuit in embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Light projection part 2 Light reception part 3 Object to be detected 11 Oscillator 12 Amplification circuit 13 Light projection element 21 Light reception element 22 Amplification circuit 23 Waveform shaping circuit 24 Flip-flop 25 Shift register 26 Synchronization signal creation circuit 27 Oscillator 28 Detection determination circuit 31 Flip-flop 32 Second flip-flop G1-G5 Inverter gate G6, G7 And gate G8 OR gate

Claims (6)

A first oscillator (11) that outputs a clock pulse as a synchronization signal, and a pulse-modulated light having the same period and duty ratio as that of the clock pulse is synchronized with the clock pulse from the first oscillator (11). A light projecting unit (1) having a light projecting element (13) that emits light;
A light receiving element (21) that receives pulse modulated light from the light projecting element (13) of the light projecting unit (1), a second oscillator (27) that outputs a clock pulse as a synchronization signal, and the light receiving element a flip-flop for temporarily holding an input pulse signal outputted from the (21) (24), a shift register which takes in sequential shifts the output of the flip-flop (24) (25), of the shift register (25) A detection determination circuit (28) for determining the presence / absence of the detection target object (3) by output and a signal path for the light receiving element (21), flip-flop (24), and shift register (25) are provided in different paths. The clock pulse C (j) from the second oscillator (27) or this clock pulse is used to sequentially shift the signal received by the shift register (25). A light receiving section (2) having a synchronization signal generating circuit (26) that generates an inverted clock pulse BarC (j) obtained by inverting C (j) as a synchronization signal of the circuit operation of the shift register (25). ,
To make the period of the clock pulse of the first oscillator (11) and the clock pulse of the second oscillator (27) the same, and to receive the pulse modulated light from the light projecting element (13). Setting means for setting the duty ratio of both clock pulses of the first oscillator (11) and the second oscillator (27) to 50%, respectively;
The synchronization signal generating circuit (26)
Wherein are input simultaneously with the input pulse signal to the flip-flop (24), projecting more the light projecting section to the clock pulse C (j) from the second oscillator (27) of the light receiving portion (2) (1) First receiving means (31) for synchronously receiving an input pulse signal from the optical element (13);
The light input to the flip-flop (24) is input simultaneously with the input pulse signal, and the light projecting section (1) is projected by the inverted clock pulse BarC (j) from the second oscillator (27) of the light receiving section (2). Second receiving means (32) for synchronously receiving an input pulse signal from the optical element (13);
An input pulse signal from the light receiving element (21) is synchronized with either the clock pulse C (j) of the second oscillator (27) or the inverted clock pulse BarC (j), and the receiving means (31) (32 ) Is received by the light receiving element (21) of the light receiving section (2) and the second oscillator (27) as a synchronizing signal of the receiving means (31) (32). A determination means for determining based on the clock pulse C (j) and the inverted clock pulse BarC (j);
The clock pulse to be sent to the shift register (25) is the clock pulse C (j) when the input pulse signal is received as the clock pulse C (j) based on the determination result of the determination means, and the inverted clock When an input pulse signal is received with the pulse BarC (j), a synchronizing signal determining means for determining a synchronizing signal for the circuit operation of the shift register (25) as the inverted clock pulse BarC (j);
Consisting of
When the input pulse signal is received by the first receiving means (31), it is input to the shift register (25) in synchronization with the clock pulse C (j) from the synchronization signal generating circuit (26). Sequentially capture input pulse signals
When an input pulse signal is received by the second receiving means (32), the shift register (25) is synchronized with the inverted clock pulse BarC (j) from the synchronization signal generating circuit (26). A photoelectric sensor characterized by sequentially taking input pulse signals . The synchronization signal generating circuit (26)
A first flip-flop (31) for outputting a set output in synchronization with the input pulse signal by the clock pulse C (j);
A second flip-flop (32) for outputting a set output by synchronizing the input pulse signal with the inverted clock pulse BarC (j);
When the set output is output from the first flip-flop (31), the output of the inverted clock pulse BarC (j) is blocked and the set output is output from the second flip-flop (32). In this case, gate circuits (G4) and (G6) for passing the inverted clock pulse BarC (j),
When the set output is output from the second flip-flop (32), the output of the clock pulse C (j) is blocked and the set output is output from the first flip-flop (31). Includes a gate circuit (G5) (G7) for passing the clock pulse C (j);
The inverted clock pulse BarC (j) or clock pulse C (j) output from the gate circuit (G4) (G6) or gate circuit (G5) (G7) is sent to the shift register (25) as a synchronization signal for circuit operation. The photoelectric sensor according to claim 1 , wherein the photoelectric sensor is configured with a gate circuit (G8) to be transmitted. Two first and second inverter gates (G1) and (G2) that pass the input pulse signal from the light receiving element (21) in series are provided, and the input pulse signal from the second inverter gate (G2) and Inputs a signal having the same polarity to the set input terminal (S) of the flip-flop (24), and a signal having a polarity opposite to that of the input pulse signal from the first inverter gate (G1) is input to the flip-flop (24). The photoelectric sensor according to claim 1 , wherein the photoelectric sensor is input to a reset input terminal (R). Input pulse signals corresponding to the presence or absence of the detection target object (3) are continuously shifted to the shift register (25), and a plurality of stages of flip-flops (41) constituting the shift register (25) claims all outputs to (45) is set when a "1", all output is characterized by having a flip-flop (35) which is reset when the "0" The photoelectric sensor in any one of Claims 1-3 . Using Q output of the flip-flop (35) as an output of the photoelectric sensor of the reflection type, in claim 4, characterized in that using the Qbar output of the flip-flop (35) as an output of the photoelectric sensor of transmission type The photoelectric sensor as described. An amplifier circuit (12) for amplifying the output of the first oscillator (11) of the light projecting unit (1) is provided, and the amplification degree of the amplifier circuit (12) and the frequency of the first oscillator (11) are variable. Made possible
An amplifying circuit (22) for amplifying the output of the light receiving element (21) of the light receiving unit (2), and a waveform shaping circuit (23) comprising a Schmitt circuit for shaping the output of the amplifying circuit (22); The photoelectric sensor according to claim 4 , wherein the amplification degree of the amplification circuit (22), the Schmitt level of the waveform shaping circuit (23), and the frequency of the second oscillator (27) can be varied .

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