JP2000059692A - Solid-state imaging device and solid-state image pickup device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To distinguish a defective pixel and a normal pixel from signal levels when reading the signals of pixels. SOLUTION: Concerning a solid-state imaging device 100 having plural pixels that is provided with optic/electric converting functions and an operating means for providing a video signal by selecting plural pixels at least, a fuse 103 is integrally built in for storing the defect information of a pixel while relating it to that pixel, when the relevant pixel has a defect. Thus, since the defective pixel and normal pixel can be distinguished from signal levels at the time of reading the signals of pixels, it is not necessary to generate a flaw correcting pulse through a conventional timing generator and no noise is mixed into the video signal. Further, since the imaging device itself is provided with a memory function, even in the case of an image pickup device which requires the exchange of the imaging device, it is enough that only the imaging device is exchanged.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for correcting a defective pixel (scratch) of a solid-state image sensor caused by a crystal defect in a semiconductor, and more particularly, to a solid-state image sensor having a method and means for storing defect information and a solid-state image sensor. The present invention relates to a solid-state imaging device used.

[0002]

2. Description of the Related Art In solid-state imaging devices, nano-ampere (n)
A) Since the optical excitation current on the order is at the signal level, the influence of the leak current due to the defect of the semiconductor crystal is very large. For this reason, it is manufactured in a manufacturing environment that is more highly clean than a general integrated circuit, and is manufactured by a low leak current manufacturing process by introducing various annealing processes for reducing crystal defects. However, a small number of pixels having a large leak current (white defects) and a small pixel of light sensitivity (black defects) may occur. A solid-state imaging device having such pixels is a solid-state imaging device having a so-called pixel defect. However, even in a solid-state imaging device having a pixel defect, an image substantially free from scratches can be obtained by replacing the defective pixel with a predetermined value obtained from neighboring pixels. A circuit that replaces this pixel information is usually called a flaw correction circuit.

A flaw correction circuit is disclosed, for example, in Japanese Patent Laid-Open No. 4-160.
No. 883, a non-volatile memory storing position information of defective pixels is connected to a timing generator. Then, at the position of the defective pixel of the image sensor (information processing timing to be obtained from the defective pixel), the pixel information is replaced with a predetermined value obtained from a pixel in the vicinity of the defective pixel to obtain an image substantially free from scratches. .

However, in this case, since the scanning timing of the solid-state imaging device and the access timing of the nonvolatile memory are different, there is a disadvantage that noise is easily mixed in the video signal.

In order to avoid this, Japanese Patent Laid-Open Publication No. Hei.
No. 73, the position information of a pixel defect is transferred from a non-volatile memory to a random access memory (RAM) provided inside a timing generator during a blanking period when there is no video signal. There is a method of preventing noise from being mixed into a video signal by energizing a memory.

In addition, since the nonvolatile memory storing the position information of the defective pixel has a one-to-one correspondence with the image sensor, it is necessary to replace a scope including the image sensor such as an electronic endoscope. However, it has been necessary to mount a nonvolatile memory on the scope section as disclosed in Japanese Patent Application Laid-Open No. 61-264770.

[0007]

In a conventional image sensor, when correcting a defect based on a pixel defect, a nonvolatile memory for storing defective pixel (scratch) position information of the image sensor is provided outside the image sensor. The nonvolatile memory must be replaced when the image sensor is replaced, and the handling is difficult. In addition, it is necessary to take care to avoid noise from being mixed into the video signal.

Accordingly, the present invention provides a solid-state image pickup device which realizes a defect correction with a simple structure by devising an image pickup device capable of correcting a defect which does not cause noise to be mixed into a video signal. It is intended to provide a device.

[0009]

According to the present invention, means for making the output signal level of a defective pixel out of the range of the output signal level of a normal pixel is integrally incorporated in the pixel array. With this configuration, when reading out a signal from a pixel,
Since the defective pixel and the normal pixel can be distinguished according to the signal level, if this distinguishing information is used, there is no need to bother to generate a flaw correction timing pulse with the timing generator, and no noise is mixed into the video signal. It is not necessary to provide a non-volatile memory for storing defective pixel positions outside.

Since the memory function for notifying the defective pixel position is equivalently integrated into the image pickup device itself, even in an image pickup device requiring replacement of the image pickup device, only the image pickup device is required. Just replace it.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic configuration diagram of a solid-state imaging device according to a first embodiment of the present invention. Reference numeral 100 denotes a solid-state imaging device. Pixels are two-dimensionally arranged on an imaging surface of the solid-state imaging device 100. In the figure, the pixels are simplified and the lower left pixels A1, A2,..., B1, B2,. That is, in this figure, the row directions are indicated by A, B, C,... And the column directions are indicated by 1, 2, 3,.

Since the structure of each pixel is the same,
One of them will be described as a representative. That is, the photosensitive N
Channel type field effect transistor (hereinafter referred to as photo MOS)
A positive voltage is applied to the gate of 101).
The gate of the photo MOS 101 is formed of a thin polysilicon film and has optical transparency.

Light incident on the gate electrode portion of the photo MOS 101 generates a pair of electrons and holes in the semiconductor crystal below the gate electrode, and the electrons are attracted by a positive voltage applied to the gate electrode, thereby causing the semiconductor surface to emit light. The holes are repelled by the voltage applied to the gate electrode and diffuse into the substrate.
As a result, a negative charge corresponding to the amount of light applied to the gate is accumulated below the gate electrode, and acts equivalently in the direction of reducing the gate applied voltage of the photo MOS 101 and decreasing the channel current.

The gate electrode of the photo MOS 101 in each row is connected to a common row line 201, 202,... For each row, and each row line 201, 202,. The source electrode of each photo MOS 101 is connected to the drain electrode of the corresponding row selection transistor 102. The source electrode of the row selection transistor 102 in each column is
Each column is connected to a common column line 21a, 21b,..., And each column line 21a, 21b,... Is connected to an output line 108 via a horizontal selection transistor 104a, 104b,. The gate electrodes of the horizontal selection transistors 104a, 104b,... Are connected to the horizontal shift register 106.

Next, the drain electrode of the photo MOS 101 is connected to a power supply via a corresponding cut-off type fuse 103. Also, the row selection transistor 102
Are connected to common row lines 221 and 22 for each row.
, And each row line 221, 222,.
Each is connected to the vertical shift register 105.

The vertical shift register 105 sequentially applies a high voltage to one row to be selected, and applies a photo MOS to the row.
101 is operated as a drive transistor of a source follower.

The horizontal shift register 106 supplies a control signal to the gate electrode of the horizontal selection transistor 104, and controls so that a scanning video current output can be obtained from the output line 108 by sequentially selecting the control signal. The signal charges stored under the gate electrode of the photo MOS 101 are diffused into the semiconductor crystal and reset by the electronic shutter shift register 107 when a low voltage is applied.

Since the signal charge stored under the gate electrode of the photo MOS 101 is not stored so much as to pinch off the channel of the photo MOS 101, the photoelectric conversion characteristic has the minimum value of the output current as shown in FIG.

Here, in the case of a pixel in which the cut-off type fuse 103 is cut, no output current flows, so that it is possible to determine whether a pixel is defective or not by the output current value. FIG. 3 is an embodiment of a solid-state imaging device having a pixel defect function.

The solid-state image sensor 301 has the elements shown in FIG. The solid-state imaging device 301 is driven by a pulse generated by the timing generator 309. The current output of the solid-state imaging device 301 is
After being converted into a voltage signal, the signal is passed to an A / D (analog-digital) converter 303 and a comparator 304.

The output of the A / D converter 303 is a digital value j delayed by one clock and a digital value k delayed by two clocks in D flip-flop circuits 305 and 306.
Is obtained.

The comparator 304 determines whether or not the pixel is a defective pixel, and the determination output is latched by a latch circuit 307 in synchronization with a clock, and becomes a defect flag pulse signal. Based on this defect flag pulse signal, the signal selection circuit 308 outputs the output of the D flip-flop circuit 305 if the pixel is not defective, and outputs the output of the D flip-flop circuit 306 (the output of the previous pixel) if the pixel is defective. Signal), and in the case of a pixel defect, the output signal value of the immediately preceding pixel is employed. With this operation, a complementary type flaw correction function can be realized.

As a method for first inspecting the position of a defective pixel after manufacturing, for example, the following method is used. The defect information of the solid-state image sensor 301 is obtained by keeping the image sensor 301 in a light-shielded state, obtaining a scan output, determining white spots, irradiating the image sensor 301 with uniform light, and setting the scan output. By obtaining it, a black flaw can be determined.

To write the defect information into the solid-state imaging device 301, all the photo MOSs 101 are turned on, the vertical selection transistor 102 and the horizontal selection transistor 104 are selected in the same order as in the normal scanning, and the output terminal 108 is selected. By applying a low voltage to the fuse 103, an excessive current can be applied to the fuse 103 where defect information is to be written, thereby cutting the fuse 103. The acquisition and writing of the defect information can be automatically performed by a die sorter for judging the quality of the image sensor, and the yield can be improved and the solid-state image sensor can be supplied at low cost.

The cut-off type fuse is a photo MOS 1
Although the case where the drain electrode of the vertical selection transistor 102 is connected to the drain electrode of the vertical selection transistor 102 is described in a series, the connection between the source electrode of the photo MOS 101 and the drain electrode of the vertical selection transistor 102 is connected to the series. Has the same effect.

FIG. 4 is a schematic configuration diagram of a solid-state imaging device according to a second embodiment of the present invention. Reference numeral 400 denotes a solid-state imaging device. Pixels are two-dimensionally arranged on an imaging surface of the solid-state imaging device 400. In the figure, the pixels are simplified and the lower left pixels A1, A2,..., B1, B2,. That is, in this figure, the row directions are A, B, C...
Suffixes are given as 2, 3,....

Since the structure of each pixel is the same,
One of them will be described as a representative. That is, a short-circuit type fuse 403 is connected in parallel to each of the photodiodes 402 having a photoelectric conversion function. The photodiode 402 and the short-circuit type fuse 403 are connected in parallel between the drain electrode of the transistor 401 and the ground potential. The source of the transistor 401 is connected to the corresponding column line 21a, 21b,. The gate electrodes of the transistors 401 are connected to the corresponding row lines 201, 202,. The column lines 21a, 21b,.
, 405b,... are connected in series.

The vertical shift register 105 is connected to the row line 2
01, 202... Are sequentially driven in a horizontal cycle. During one horizontal period, the horizontal shift register 106 sequentially turns on the transistor 4
By turning on the signals 05a, 405b,..., The output signal of each pixel of the accessed row can be obtained on the output line 108.

The short-circuit type fuse is, as shown in FIG.
It has a structure in which upper and lower electrodes (polysilicon) 52, 53 are opposed to each other with an extremely thin insulating film (silicon oxide film) 51 interposed therebetween. The upper and lower electrodes are short-circuited.

The video signal of each row is transmitted to the vertical shift register 1
05 and a pulse from the horizontal shift register 106, the transistor 401 in each row and the transistor 405 in each column
are obtained from the output line 108 by sequentially selecting a, 405b,.

Here, when the defect information is written in the short-circuit type fuse 403, a current exceeding the saturation signal amount flows, and it can be determined that the pixel is a defective pixel. Furthermore, as shown in FIG. 7, a reverse voltage equal to or higher than the breakdown voltage may be applied to the PN junction to supply power equal to or higher than the allowable power loss of the photodiode 402 to break the PN junction to form a resistive region. .
FIG. 7 shows the allowable power of the photodiode and the PN junction breakdown region.

In the case of a CCD image pickup device for sequentially transferring photoelectrically converted signal charges, the PN junction of the photodiode 402 is irradiated with laser light 601 and heated to destroy the PN junction as shown in FIG. And the resistive region 602
And a low resistance may be formed in parallel with the photodiode 402 as a photosensitive element.

The method of first examining the position where the defective pixel exists is the same as that of the embodiment of FIG. 1 described above. FIG. 8 is a schematic block diagram of a solid-state imaging device according to the third embodiment of the present invention.

Reference numeral 800 denotes a solid-state image sensor. Pixels are two-dimensionally arranged on an image forming surface of the solid-state image sensor 400. In the drawing, the pixel is simplified, and the lower left pixel A1,
A2,..., B1, B2,. That is, also in this figure, the suffixes are given as A, B, C... In the row direction and 1, 2, 3,.

The solid-state imaging device 800 includes a no-signal voltage holding unit 881 for holding a no-signal voltage of each phototransistor in the row direction, and a signal voltage holding unit 882 for holding a signal when a signal is extracted. Is provided. The output voltage from the signal voltage holding unit 882 and the output voltage from the no-signal voltage holding unit 881 are equal to the differential amplifier 883.
, And the difference is extracted as a normal output signal.

First, the configuration of the pixel will be described. Since each pixel has the same configuration, only one pixel will be described as a representative. That is, the anode of the photodiode 801 having the photoelectric conversion function is connected to the ground potential portion, and the cathode is connected to the gate of the buffer transistor 803 and the drain of the reset transistor 802. The drain of the reset transistor 802 is connected to a column signal line 821 via a fuse 805. On the other hand, the drain of the buffer transistor 803 is connected to the power supply, and the source is connected to the source of the vertical selection transistor 804. The source of the vertical transistor 804 is connected to the column signal line 821.

Next, the gate of the reset transistor 802 is connected to a reset line 831 in the row direction.
The gate of the vertical transistor 804 is connected to a line 841 in the row direction.

Next, the no-signal voltage holding unit 881 will be described. Since each column signal line 821 is connected to a no-signal voltage holding circuit having the same configuration, only one will be described as a representative. A switch 811 and a capacitor 812 are connected in series between the column signal line 821 and the ground.
A switch 813 is connected between a connection point between the switch 811 and the capacitor 812 and the no-signal voltage output line 851. The no-signal voltage output line 851 is connected to the output terminal 853 via the inverter 852 and to the differential amplifier 883 described above.

Next, the signal voltage holding section 882 will be described. Since each column signal line 821 is connected to a no-signal voltage holding circuit having the same configuration, only one will be described as a representative. A switch 814 and a capacitor 815 are connected in series between the column signal line 821 and the ground. A switch 816 is connected between a connection point between the switch 814 and the capacitor 815 and the signal voltage output line 861. The signal voltage output line 861 is connected to the differential amplifier 883. An image signal is obtained at an output terminal 862 of the differential amplifier 883.

One of the column signal lines 821 is connected to a constant current source, and the other is connected to a power source via a switch 818. Each column selection line 821 is connected to a terminal 819 via a switch 817.

The reset line 831 in the row direction and the line 841 in the row direction are connected to the vertical shift register 806. The column selection line 821 is connected to the horizontal shift register 820.

FIG. 9 is a timing chart for explaining the operation of the solid-state imaging device. The case where the fuse 805 is in the conductive state will be described. After the photodiode 801 having a photoelectric conversion function is set to a predetermined voltage by the reset transistor 802, a potential change corresponding to the amount of irradiated light occurs. The voltage of the photodiode 801 is impedance-converted by the buffer transistor 803. For example, when the S1 pulse is output, the transistor 804 is turned on and appears on the vertical signal line, that is, the column selection line 821. Now, it is assumed that the signal of each column in the lowermost row is output to the column selection line 821.

At this time, the SP of the timing generator 816
The switch 814 is turned on by the pulse. As a result,
The signal voltage is stored on the capacitor 815. Next, the timing generator 816 uses the RP pulse to
Turn on 8. Then, the column selection line 821 is biased to the power supply voltage. Next, the transistor 802 is turned on by a pulse R1 from the vertical register 806. Then, the cathode voltage of the photodiode 801 is set to a predetermined voltage. Here, the switch 818 is turned off. Then, the voltage of the photodiode 801 when there is no signal is supplied to the buffer transistor 803 and the transistor 804.
Appear on the column select line 821 via The voltage at the time of no signal is stored in the capacitor 812 when the switch 811 is turned on by the CP pulse from the timing generator 816.

Next, Ha from the horizontal shift register 820 is used.
Switches 813 and 816 are turned on by the pulse. Then, the output voltage of the capacitor 815 of the signal voltage holding unit 882 and the output voltage of the capacitor 812 of the non-signal voltage holding unit 881 are input to the differential amplifier 883.

As a result, a subtraction result between the signal voltage and the no-signal voltage is obtained at the output of the differential amplifier 883,
The correct signal is output to the output terminal 862. The defective pixel information can be stored by cutting the fuse 805.

In this case, the reset transistor 80
Even when 2 is turned on, a predetermined voltage cannot be applied to the photodiode 801, and the leak current and the photocurrent continue to be accumulated, and the equilibrium point is reached at almost 0V. Since this voltage is read by the capacitor 812, it is output at the same timing as the video signal through the inverter 852. That is, in the case of a pixel that has undergone such processing, an output voltage from the differential amplifier 883 cannot be obtained.

In the method of storing defective pixel information in the fuse 805, the fuse 805 can be blown by applying a voltage pulse equal to or higher than the breakdown voltage of the photodiode to the write pin 819. In this case, for example, the horizontal shift register 820 is slowly driven to apply a voltage pulse at a defective pixel position which has been confirmed in advance. Note that the method of inspecting the position of the defective pixel of the image sensor after manufacturing is the same method as in the above embodiment.

FIG. 10 is a schematic block diagram of a solid-state imaging device using the solid-state imaging device of FIG. Solid-state imaging device 80
The signal output of 0 (the output signal of the differential amplifier 883) is supplied to the signal switch 1005 through the delay elements 1002 and 1003. Defect information terminal (output terminal of inverter 82)
Is a signal switch 100 via a delay element 1004
The switching signal is connected to the switching control signal input terminal No. 5, and at the timing of the defective pixel, the current signal is replaced with a signal before a predetermined time and output.

FIG. 11 is a schematic block diagram of a solid-state imaging device according to a fourth embodiment of the present invention, FIG. 12 is a timing chart for explaining its operation, and FIG. 13 is a solid-state imaging device using the same. is there.

When storing information indicating the position of a defective pixel, this solid-state imaging device reads out the defect information stored in the pixel and automatically refreshes the defect information instead of cutting the fuse. It is comprised so that it may have. The configurations of the non-signal-time voltage holding unit 881 and the signal voltage holding unit 882 are the same as those in the above embodiment, and are denoted by the same reference numerals.

In FIG. 11, reference numeral 1100 denotes a solid-state image sensor, and pixels are two-dimensionally arranged on an image forming surface of the solid-state image sensor 1100. In the figure, the pixels are simplified and the lower left pixels A1, A2,..., B1, B2,. That is, also in this figure, similarly to the previous embodiment, the row directions are indicated by A, B, C..., And the column directions are indicated by 1, 2, 3,.

The solid-state imaging device 1100 includes a no-signal voltage holding unit 881 for holding a no-signal voltage of each phototransistor in a row direction, and a signal voltage holding unit 882 for holding a signal when a signal is extracted. Is provided. The output voltage from the signal voltage holding unit 882 and the output voltage from the no-signal voltage holding unit 881 are equal to the differential amplifier 88.
3 and the difference is extracted as a normal output signal.

First, the configuration of the pixel will be described. Since each pixel has the same configuration, only one pixel will be described as a representative. That is, the anode of the photodiode 1101 having a photoelectric conversion function is connected to the ground portion, and is connected to the source of the transistor 1102. Transistor 110
2 is connected to the source of the reset transistor 1103 and to the gate of the amplification transistor 1104. The drain of the reset transistor 1103 is connected to the column selection line 821. The drain of the amplification transistor 1104 is connected to a power supply, and the source is connected to the drain of the reading transistor 1105. The source of the read transistor 1105 is connected to the column selection line 821.

Next, the configuration of the defect information refresh circuit 900 will be described. Since the flaw determination circuit 900 includes a similar circuit in each column, one of the flaw determination circuits 900 will be described as a representative.
Each row of circuits has a flaw information capturing switch 1109, a flaw information output switch 1111 and a flaw information holding capacitor 1110 (flaw scanning circuit). The circuits in each column have a flaw signal feedback switch 1112.

The switch 1109 and the capacitor 1110 are connected in series between each column signal line 821 and the ground. A flaw information output switch 1111 is connected between a connection point between the switch 1109 and the capacitor 1110 and a flaw information output line 1120.

The flaw information output line is connected to an output terminal 1123 via an amplifier 1121.
The defect information of 123 is input to the D flip-flop 1124. An output line 1125 of the D flip-flop 1124 is connected to a column signal line 821 via a flaw signal feedback switch 1112.

The line 1130 is for controlling the voltage supply switch 1131 provided in each column. Reference numeral 1132 denotes a timing generator that outputs various timing signals.

Next, the operation will be described with reference to FIG.
The operation of the no-signal voltage holding unit 881 and the signal voltage holding unit 882 is the same as that of the embodiment shown in FIG.

When the selection switch 1105 is turned on by the signal S1 and then the pulse DP is output, the flaw information stored in the gate node of the amplification transistor 1104 is output to the column signal line 821, and is output via the switch 1109. Sampled by the capacitor 1110.

Next, a preset bias switch 1
A pulse RP is given to 131, a pulse R1 is given to a reset transistor 1103, and an amplifying transistor 110 is given.
After setting the gate voltage of the pulse No. 4 to a predetermined value, the pulse CP
Is supplied to the transistor 811, and the voltage when there is no signal is sampled to the capacitor 812. Next, a pulse T1 is applied to the reading transistor 1102, and signal charges are read from the photodiode 1101.
4, 1105, and output to the column signal line 821. next,
The switch 814 is turned on by the pulse SP, and the signal voltage is sampled by the capacitor 1119.

Next, when a pulse Ha is output from the horizontal shift register 1122, the switches 1111 and 81 in the first column are output.
3 and 816 are turned on, the voltage when there is no signal and the signal voltage are input to the differential amplifier 883, and the normal signal is output to the output terminal 86.
2 is output. In addition, a defect signal based on the defect information is output from the amplifier 1121 from the capacitor 1110.

This flaw signal output from the amplifier 1121 is sampled by the flip-flop 1124,
When a pulse Hb for selecting the next column is output from the horizontal shift register 1122, the signal is rewritten to the gate of the transistor 1104 via the flaw write switch 1112 and the transistor 1103. By repeating this operation, a signal can be read from the pixel while retaining the flaw information written in the pixel.

FIG. 13 shows a configuration example of a solid-state imaging device using the solid-state imaging device 1100 described above. The signal output from the solid-state imaging device 1100 is
After being given a predetermined delay by 1302, it is supplied to the changeover switch 1303. The changeover switch 1303 selects and derives the output of the delay element 1301 when the pixel is not a defective pixel, and selects and derives the output of the delay element 1302 when the pixel is a defective pixel to output a signal free from scratches. The delay element 1304 is a circuit that delays the signal of the defect information by one pixel. By the output, the changeover switch 130
3 is controlled.

The flaw information in the solid-state image pickup device is obtained by using a flaw information acquisition circuit 1306 which closes the switch 1307 when the power is turned on, determines white flaws from a dark image, and determines black flaws from a signal of uniform illumination. To write the flaw information to the solid-state imaging device. If the current supply capability of the flaw signal output of the solid-state imaging device is set small, the flaw signal input / output pin 112
3 can be input via a flip-flop 1124. The defect information acquiring circuit 1036 may be configured to be used also by the defect information refresh circuit 900.

The solid-state image pickup device has been described in the form of a solid-state image pickup device and its peripheral blocks. However, in a so-called one-chip camera in which a flaw correction circuit and other signal processing circuits are integrated, the operation timing is different. The effect of the present invention that noise is not mixed in the video signal is great.

The features of the present invention described above are summarized as follows. In a solid-state imaging device having at least a plurality of pixels having a photoelectric conversion function and operation means for selecting the plurality of pixels and obtaining a video signal, when a pixel has a defect, defect information of the pixel is transmitted. Means for storing the image in association with the pixel are integrally incorporated.

The means for storing the defect information of the pixel in association with the pixel uses a fuse as an example. As a method of providing a fuse, a cut-off type fuse is provided in a path for supplying a signal output to a signal line, and the cut-off type fuse of a defective pixel is cut off. Alternatively, there is a method in which a short-circuit type fuse is provided in parallel with the photodiode, and the short-circuit type fuse of the defective pixel is short-circuited. Or,
Before reading the signal voltage from the photodiode, there is a method of providing a cut-off type fuse in a path for setting the input voltage of the amplifier to a predetermined voltage.

As means for storing the defect information of the pixel in association with the pixel, there is a method using an element in which a PN junction is thermally destroyed. As this method, there is a method in which a laser beam is applied to the photodiode to thermally destroy the PN junction, or a method in which a voltage higher than the breakdown voltage is applied to the photodiode to thermally destroy the PN junction.

Further, the storage means for the defect information in the pixel sets the input voltage of the amplifier in the pixel to a predetermined voltage applied to the signal line after reading out the signal from the photodiode, and reads the signal from the next photodiode. In reading out the signal, there is a method of detecting the output voltage level of the amplifier.

Further, in the solid-state imaging device, when the signal level from the pixel of the solid-state imaging device is at a predetermined level, the pixel information is replaced with the value calculated from the neighboring pixels. Means for storing pixel defect information obtained at a predetermined time in each pixel of the solid-state imaging device; and storing defect information obtained in reading out a signal from each pixel in each pixel again. And means for causing it to be provided.

[0071]

As described above, according to the present invention, a defect correction pulse can be generated by a conventional timing generator because a defective pixel and a normal pixel can be distinguished by a signal level when reading out a signal from the pixel. There is no need to perform this, and no noise is mixed into the video signal. In addition, since the image sensor itself has a memory function, only the image sensor needs to be replaced even in an image pickup device requiring replacement of the image sensor.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing photoelectric conversion characteristics of the solid-state imaging device of FIG.

FIG. 3 is a diagram showing a solid-state imaging device using the solid-state imaging device of FIG. 1;

FIG. 4 is a diagram showing a second embodiment of the present invention.

FIG. 5 is a diagram illustrating an example of a blocking element used in the solid-state imaging device in FIG. 4;

FIG. 6 is a diagram showing an example of a blocking element used in the solid-state imaging device of FIG. 4;

FIG. 7 is an explanatory diagram of a reverse voltage when the solid-state imaging device of FIG.

FIG. 8 is a diagram showing still another embodiment of the present invention.

FIG. 9 is a timing chart shown for explaining the operation of the solid-state imaging device in FIG. 8;

FIG. 10 is a diagram showing a configuration example of a solid-state imaging device using the solid-state imaging device of FIG. 8;

FIG. 11 is a diagram showing still another embodiment of the present invention.

FIG. 12 is a timing chart shown for explaining the operation of the solid-state imaging device in FIG. 11;

13 is a diagram illustrating a configuration example of a solid-state imaging device using the solid-state imaging device in FIG.

[Explanation of symbols]

100, 400, 800, 1100 ... solid-state imaging device, 1
01 photo MOS, 102 row selection transistor, 1
03: fuse, 104a, 104b,... Horizontal selection transistor, 105: vertical shift register, 106: horizontal shift register, 107: electronic shutter shift register.

Claims (6)

[Claims] 1. A solid-state imaging device having at least a plurality of pixels having a photoelectric conversion function and operation means for selecting the plurality of pixels and obtaining a video signal. A solid-state imaging device, wherein a defective pixel storage means for storing defect information of a pixel in association with the pixel is integrated. 2. The solid-state imaging device according to claim 1, wherein the defective pixel storage unit that stores the defect information of the pixel in association with the pixel uses a fuse. 3. A solid-state imaging device according to claim 1, wherein said defective pixel information storage means for storing defect information of said pixel in association with said pixel uses a device in which a PN junction is thermally destroyed. 4. A defective pixel information storing means for storing defect information of a pixel in association with the pixel, utilizing a charge amount accumulated in a gate of an amplification element in a signal charge readout path of the pixel. The solid-state imaging device according to claim 1. 5. At least a plurality of pixels having a photoelectric conversion function and operation means for selecting the plurality of pixels and obtaining a video signal, and when a pixel has a defect, defect information of the pixel And a means for replacing an output with a signal obtained from a neighboring pixel when a signal level from a pixel of the solid-state image sensor is at a predetermined level. A solid-state imaging device comprising: 6. The pixel defect information acquired at a predetermined time,
The solid-state imaging device according to claim 5, further comprising a unit that feeds back to the defect information storage unit.