JP2000059443A - Signal transmitter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal transmitter capable of realizing both high speed operation and low power consumption, while suppressing the increase of current. SOLUTION: Input output circuits 3, 4 are interconnected by transmission lines 6, 6', termination members 5, 7 connect to both ends of the transmission lines 6, 6' in a signal transmitter. When a signal is sent from a 1st input output circuit 3 to a 2nd input output circuit 4 via the transmission lines 6, 6, since the termination member 5 of the 1st input output circuit 3 is disconnected from the transmission line, resulting in the impedance of the transmission line as viewed from a signal output terminal being doubled in comparison with the case that the termination member connects to both ends of the transmission line, a current to be supplied to the transmission line for obtaining a specified level at a signal receiving end is substantially halved and then the power consumption at signal transmission is nearly halved. Moreover, since the termination member is connected around the input output circuit for the signal receiving side at all times, signal reflection at a receiving end is avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for reducing power consumption of data transfer between input / output circuits connected to a transmission line having a terminating member.

[0002]

2. Description of the Related Art There is an IEEE1394 interface as an interface between AV devices such as a digital video camera, a PC, a VTR, and a DVD. This interface is a high-speed serial interface capable of transferring large volumes of data such as moving images in real time, and the demand is rapidly increasing at present. As shown in FIG. 6, the differential signal transmission type I / O and the signal transmission line used in this interface electrically connect both ends of each of the two transmission lines via a resistor.
When a signal is transmitted from the module (chip) 61 to the LSI module (chip) 62, the end A to the end A ′
And a voltage V2 generated between B and B 'is detected by the receiver of the chip 62. When a signal is transmitted from the chip 62 to the chip 61, a current flows from the end B to the end B ′, and a voltage V1 generated between the ends A and A ′ is detected by the receiver of the chip 61. Thus, signal transmission between the chips 61 and 62 becomes possible.

The values of the terminating resistors R1 and R2 are set to the same value as the characteristic impedance Z0 of the transmission lines 6 and 6 '. With such a structure, high-speed data transfer is possible without signal reflection occurring at the end of the transmission line. In addition, when the terminating resistor is provided near the signal receiving end, a high-quality signal can be received at the receiving end. Therefore, when transmitting and receiving a bidirectional signal, the same applies regardless of which signal is transmitted. Terminating resistors are provided at both ends of the transmission line so that transmission and reception can be performed under the above conditions.

[0004]

However, since the terminating resistors are provided at both ends of the transmission line, the impedance of the transmission line as viewed from the transmission end of the signal is Z0 / 2, and the signal generated at the reception end is Z0 / 2. A large amount of current always flows to secure the amplitude V1 or V2, which results in an increase in power consumption.

SUMMARY OF THE INVENTION An object of the present invention is to provide a signal transmission device that matches both data transfer conditions and suppresses an increase in the amount of current in bidirectional data transfer, that is, realizes both high speed and low power consumption. To provide.

[0006]

According to a first aspect of the present invention, there is provided a signal transmission apparatus in which input / output circuits are connected to each other by a transmission line, and terminating members are connected to both ends of the transmission line. When a signal is transmitted from the first input / output circuit to the second input / output circuit via the first input / output circuit, the impedance of the terminal member on the first input / output circuit side is changed.

According to this configuration, when a signal is transmitted from the first input / output circuit to the second input / output circuit, the impedance of the terminating member on the first input / output circuit side is changed (for example, almost infinite). ), The impedance of the transmission line as viewed from the output end is twice as large as that in the case where the terminating members are connected to both ends of the transmission line. In this case, the amount of current flowing through the transmission line is halved, and the power consumption during signal transmission is also halved. In addition, since a terminating member is connected near the input / output circuit that always receives signals, the signal can be prevented from being reflected at the receiving end.

According to a second aspect of the present invention, the change in the impedance of the terminating member is performed based on an output activation signal of the input / output circuit on the signal transmitting side. Thus, the impedance of the terminating member can be controlled without providing a special circuit.

According to a third aspect of the present invention, the impedance of the terminating member is set higher when the output activation signal is activated than when it is inactivated.

According to a fourth aspect of the present invention, in the signal transmission device of the first aspect, the output impedance of the input / output circuit is changed in accordance with the impedance of the terminal member at the same time as the impedance of the terminal member is changed. Let it.
Thus, it is possible to prevent the voltage amplitude at the receiving end from increasing or decreasing with respect to the change in the impedance of the terminating member.

According to a fifth aspect of the present invention, the terminal member is provided on the same chip as the input / output circuit. This eliminates the need to output a control signal to the outside of the chip, and facilitates impedance control of the terminating member.

According to a sixth aspect of the present invention, the signal transmission device has a plurality of signal transmission modes, wherein the plurality of signal transmission modes have different signal transmission rates and have a signal transmission rate of not less than a predetermined value. In the transmission mode, the impedance of the terminating members connected to both ends of the transmission line is not changed. Thus, during relatively slow data transmission, power consumption can be reduced, and ultra-high-speed data transmission can also be performed.

[0013]

FIG. 1 is a block diagram showing an embodiment of the present invention.
This will be described with reference to FIG.

(Embodiment 1) FIG. 1 is a conceptual diagram of a signal transmission device for realizing high-speed and low-power-consumption data transmission in Embodiment 1 of the present invention.

In FIG. 1, reference numeral 1 denotes a first LSI module (first chip), 2 denotes a second LSI module (second chip), and 3 and 4 denote input / output terminals for transferring signals to and from the outside. Output circuits 6, 6 'are transmission lines, 5, 7 are variable terminating resistors whose impedance values can be changed, 8, 9 are state machines for generating signals for controlling the operation state of the chip. When a signal is transmitted from the chip 1 to the chip 2, a current is generated from the input / output circuit 3,
The current flows into the input / output circuit 3 again from the transmission line 6 via the variable termination resistor 7 and the transmission line 6 ′, and the voltage V 2 generated in the variable termination resistor 7 by the current is detected by the input / output circuit 4. Signal transmission becomes possible. The signal transmission from the chip 2 to the chip 1 can be performed in the same procedure only by replacing the chip 1 with the chip 2.

According to the present invention, a chip for transmitting a signal
At the time of signal transmission, one terminal resistor is electrically disconnected from the transmission line. Referring to FIG. 1, when transmitting a signal from the chip 1 to the chip 2, the impedance of the variable terminating resistor 5 is increased, and the variable terminating resistor 5 is electrically disconnected from the transmission lines 6, 6 '. The timing control for increasing the impedance of the terminating resistor is performed by the state machines 8 and 9.
At the time of signal transmission, an output activation signal (dataEn) for permitting the input / output circuits 3 and 4 to output data to the outside.
Is transmitted, and can be easily realized by using the signal.

Conventionally, a terminating resistor R1 = Z at both ends of a transmission line
0 and R2 = Z0 were always connected. For this reason, if it is assumed that V2 = I × R2 is required as a voltage amplitude necessary for receiving signals at the receiving ends B and B ′, there are two current paths (a path through R1 and a path through R2). Therefore, it is necessary to supply a current 2I from the input / output circuit.

On the other hand, according to the present invention, since one terminating resistor is separated from the transmission line at the time of data transmission, there is only one current path, and the voltage amplitude at the receiving ends B and B 'is V2 = I
When × R2 is required, it is only necessary to flow the current I from the input / output circuit, and the current consumption can be reduced by half compared to the conventional case.

FIG. 2 shows the LSI module (chip) of FIG.
1 is a detailed view of FIG. The chip 2 has the same configuration as the chip 1. Hereinafter, the internal operation of the LSI module will be specifically described with reference to FIG. In FIG. 2, reference numeral 21 denotes an output buffer circuit (driver), and reference numeral 22 denotes an input buffer circuit.

The variable terminating resistor 5 comprises a terminating resistor 5b and a switch circuit 5a for electrically disconnecting the terminating resistor 5b from the transmission line 6. The switch circuit 5a includes a transfer gate and an inverter.
Open (Off) when taEn signal is High, conduct (O) when Low
n). Here, the terminating resistor 5
It is desirable that the sum of the value of b and the resistance value of the switch TG in the switch circuit when the switch is on is equal to the characteristic impedance of the transmission line to which the terminal resistance 5b and the switch circuit 4 are connected.

The Data + and Data- signals are complementary to each other in the data signal, and the direction of the current flowing in the transmission line (the direction of exiting from A or the direction of entering) can be controlled by High or Low of Data +. .

DataEn is an output activation signal of the output buffer circuit 21 generated by the state machine 8, and DataEn is
Is High, the output buffer circuit 21 outputs Data + and Dat
Upon receiving the a-signal, the signal can be transmitted to the outside.

Normally, in an output buffer circuit using a current source (here, MP1 and MN1), when the DataEn signal is active (here, High), the current continues to flow constantly. Become active. for that reason,
As shown in FIG. 3, by turning on and off the transfer gate TG of the switch circuit 4 in conjunction with the DataEn signal, the terminating resistor 5b on the transmitting side is disconnected at the time of signal transmission, and the signal transmission is not performed. Then, the termination resistor 5b
Can be connected. In other words, this configuration makes it possible to reduce the current consumption during signal transmission to half.

In this embodiment, the variable terminating resistor 5 is constituted by the switch circuit 5a and the terminating resistor 5b. However, the present invention is not limited to this, and the variable terminating resistor 5 can be realized by using a normal variable resistor having a variable resistance value. Further, in this embodiment, the switch circuit 5a is arranged on the same LSI module (chip) 1 as the output buffer 21 in order to facilitate the control of the switch circuit. However, it is not necessary to arrange the switch circuit 5a on the same chip. Absent. Further, in the present embodiment, a differential interface is taken as an example, but the present invention can be easily extended to a terminal type single-phase interface.

(Embodiment 2) In the configuration of Embodiment 1, sufficiently high-speed data transfer is possible, but for ultra-high-speed data transfer exceeding 400 Mbps,
For reflection of data, it is necessary to use a transmission line in which terminal members are connected to both sides of the transmission line. For example, in IEEE1394,
Modules having different data transmission capabilities are connected.
As shown in FIG. 4, when modules A to D are connected, and the data transmission capacity of module A is 100 Mbps, modules B and C are 400 Mbps, and module D is 200 Mbps, the data transmission between the modules is low. If the transmission rate of the module is not matched, data cannot be transmitted and received. Therefore, a mode for supporting a plurality of data transmission rates is provided. Even in such a case, the module (A to D) has the configuration shown in the block diagram of FIG.

FIG. 5 is a block diagram of the modules A to D of FIG. DataEn is a data enable signal for the output buffer circuit 21a, and SEL is a signal that changes according to the mode signal MOD (0; 1) and controls the switch circuit 5a at the termination and the output buffer circuit 21a. Here, the mode signal MOD (0; 1) is a signal for determining the data transmission rate. The mode signal MOD (0; 1) (sent from the Link layer in IEEE1394) is held in a register (not shown), and the held mode signal MOD (0; 1) is held by a decoder (not shown). Decode and generate signal SEL.

The switch control circuit 62 and the output buffer control circuit (selector) 61 receive the SEL and the DataEn signal, and control ON / OFF of the switch circuit 5a and control of the drive capability of the output buffer circuit 21a according to the respective modes. Do. For example, MOD (0; 1) is a 2-bit signal, (0,0) is 100Mbps,
(0,1) is a data transfer mode of 200 Mbps, (1,0) is 400 Mbps, and (1,1) is a data transfer mode of 800 Mbps. Is assumed to be terminated at both ends. At that time, the decoder responds to the mode signal MOD (0; 1) by the signals shown in (Table 1).
SEL is output, and the mode of the switch circuit 5a and the output buffer circuit 21a is switched according to the SEL signal of 1 or 0.

The switch control circuit 62 receives the SEL signal and DataE
Upon receiving the n signal, the switching signal SW is output to the switch circuit 5a in accordance with the truth table of (Table 2). Only when the SEL signal is 0 (data transfer rate 100 Mbps / 200 Mbps) and the DataEn signal is 1, the terminating resistor 5b is disconnected from the transmission lines 6 and 6 '. Keep it. This results in a data transfer rate of 100/20
In the case of 0 Mbps, power consumption can be reduced by disconnecting the termination unit from the transmission line when outputting data, and when the data transfer rate is extremely high, 400/800 Mbps, it is connected to both ends of the transmission line. By connecting the terminals, ultra-high-speed data transmission is also possible.

An output buffer control circuit (selector)
61 receives the SEL signal and the DataEn signal, and outputs the drive control signal DrvCon to the output buffer circuit 21a according to the truth table of (Table 2). When the SEL signal is 1 and DataEn is 1, the transistors MP1b and MN of the output buffer circuit 21a are
Turn 1b ON. As a result, in the ultra-high-speed data transfer mode, a current required when both ends are terminated can be added, and the voltage amplitude at the receiving end can be set to the same level as at the time of one-side termination.

[0030]

[Table 1]

[0031]

[Table 2]

As described above, according to the present embodiment, by terminating one of the terminating resistors from the transmission line during data transfer, high-speed data transfer of about 100 Mbps to 400 Mbps can be performed.
The amount of current can be reduced. Also, by automatically switching to both ends, ultra-high-speed data transfer exceeding 400 Mbps becomes possible.

In this embodiment, the mode signal MOD
Although (0; 1) is a 2-bit signal, it need not be 2 bits. In the present embodiment, the transistor TG used in the switch circuit 5a and the output buffer circuit 21
Although the gate bias of the current controlling transistors MP1 and MN1 in FIG. 1A is fixed, by controlling the gate bias, it is possible to adjust the resistance value of the termination portion or the amount of output current of the output buffer. further,
Although signals are transmitted differentially in the present embodiment, the present invention can be easily extended to the case where signals are transmitted in a single phase.

[0034]

According to a first aspect of the present invention, there is provided a signal transmission device in which input / output circuits are connected to each other by a transmission line, and a terminal member is connected to both ends of the transmission line. When a signal is transmitted from the first input / output circuit to the second input / output circuit, the impedance of the terminal member on the first input / output circuit side is changed.

According to this configuration, when a signal is transmitted from the first input / output circuit to the second input / output circuit, the impedance of the terminating member on the first input / output circuit side is changed (for example, almost infinite). ), The impedance of the transmission line as viewed from the output end is twice as large as that in the case where the terminating members are connected to both ends of the transmission line. In this case, the amount of current flowing through the transmission line is halved, and the power consumption during signal transmission is also halved. In addition, since a terminating member is connected near the input / output circuit that always receives signals, the signal can be prevented from being reflected at the receiving end.

According to a second aspect of the present invention, the change in the impedance of the terminating member is performed based on an output activation signal of the input / output circuit on the signal transmitting side. Thus, the impedance of the terminating member can be controlled without providing a special circuit.

According to a third aspect of the present invention, the impedance of the terminating member is set higher when the output activation signal is activated than when it is inactivated.

According to a fourth aspect of the present invention, in the signal transmission device according to the first aspect, the output impedance of the input / output circuit is changed according to the impedance of the terminal member at the same time as the impedance of the terminal member is changed. Let it.
Thus, it is possible to prevent the voltage amplitude at the receiving end from increasing or decreasing with respect to the change in the impedance of the terminating member.

According to a fifth aspect of the present invention, the terminal member is provided on the same chip as the input / output circuit. This eliminates the need to output a control signal to the outside of the chip, and facilitates impedance control of the terminating member.

According to a sixth aspect of the present invention, the signal transmission device has a plurality of signal transmission modes, wherein the plurality of signal transmission modes have different signal transmission rates and have a signal transmission rate of a predetermined or higher. In the transmission mode, the impedance of the terminating members connected to both ends of the transmission line is not changed. Thus, during relatively slow data transmission, power consumption can be reduced, and ultra-high-speed data transmission can also be performed.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram of a signal transmission device according to a first embodiment of the present invention.

FIG. 2 is a detailed view of the chip 1 of FIG.

FIG. 3 is a timing chart of a control signal in the signal transmission device according to the embodiment.

FIG. 4 is a diagram showing a connection configuration of modules according to a second embodiment of the present invention.

FIG. 5 is a block diagram of modules AD in FIG. 4;

FIG. 6 is a configuration diagram of a conventional signal transmission device.

[Explanation of symbols]

1 LSI module (chip) 3, 4 I / O circuit 5, 7 Variable terminating resistor 6, 6 'Transmission line 8, 9 State machine Data + Input signal to output buffer Data- Inverted signal of input signal to output buffer DataEn Data enable Signal SEL Switch control circuit and output buffer control circuit control signal SW Switch circuit control signal DrvCon Output buffer circuit control signal

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hironori Akamatsu 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (72) Inventor Gakushi Takahashi 1006 Kadoma, Kazuma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (72) Inventor Hiroshi Terada 1006 Odaka Kazuma, Kadoma City, Osaka Pref. Matsushita Electric Industrial Co., Ltd. 1006 Odakadoma, Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor Yoshihide Komatsu 1006 Odaka, Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. EE17 GG07 HH01 JJ08

Claims (6)

[Claims] 1. A signal transmission device in which input / output circuits are connected to each other by a transmission line, and a terminating member is connected to both ends of the transmission line. A signal transmission apparatus for transmitting a signal to the input / output circuit, wherein the impedance of the terminal member on the first input / output circuit side is changed. 2. The change in impedance of the terminating member is as follows:
2. The signal transmission device according to claim 1, wherein the signal transmission is performed based on an output activation signal of an input / output circuit on the signal transmission side. 3. The signal transmission device according to claim 2, wherein the impedance of the terminating member is set higher when the output activation signal is activated than when the output activation signal is deactivated. 4. The signal transmission device according to claim 1, wherein the output impedance of the input / output circuit is changed in accordance with the impedance of the terminal member at the same time when the impedance of the terminal member is changed. 5. The signal transmission device according to claim 1, wherein the terminal member is provided on the same chip as the input / output circuit. 6. The signal transmission device has a plurality of signal transmission modes, wherein the plurality of signal transmission modes have different signal transmission rates. The signal transmission device according to claim 1, wherein the impedance of the terminating members connected to both ends of the transmission line is not changed.