JP2016082426A - Transmission/reception circuit and control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To quicken a communication speed.SOLUTION: Output nodes N2p, N2n of transmission buffers 25, 26 of a transmission/reception circuit 22 are connected via terminal resistances R1p, R1n to external terminals E1p, E1n. The transmission buffer 25 has transistors T1p, T2p between the output node N2p and wiring PL1, PL2. The wiring PL1 is connected via a switch SW1p to a high potential power supply wiring VDD, and the wiring PL2 is connected via a switch SW2p to lower potential power supply wiring VSS. The transmission buffer 26 has transistors T1n, T2n between the output node N2n and the wiring PL1, PL2. The wiring PL1 is connected via a switch SW1n to the high potential power supply wiring VDD, and the wiring PL2 is connected via a switch SW2n to the low potential power supply wiring VSS. Capacitors C1p and C1n are connected between the wiring PL1 and the low potential power supply wiring VSS.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a transmission / reception circuit and a control method.

  With the improvement in communication speed between two electronic devices, communication using complementary signals has become common. In the case of one-way communication, one electronic device has an output circuit that outputs a complementary signal, and the other electronic device has a receiving circuit that receives the complementary signal. In the case of bidirectional communication, each of the two electronic devices has an output circuit that outputs a complementary signal and a receiving circuit that receives the complementary signal. Such an electronic device has a termination resistor connected to a signal transmission path (see, for example, Patent Documents 1 and 2). The termination resistance suppresses waveform distortion due to signal reflection.

International Publication No. 2011/052141 JP 2009-49672 A

  By the way, the termination resistor connected to the signal line causes an increase in the capacitance value of the parasitic capacitance with respect to the terminal of the transmission / reception circuit. Such a parasitic capacitance becomes a factor that hinders an increase in signal transmission speed.

  According to an aspect of the present invention, the output node is connected to the first external terminal via the first termination resistor, and the output node is connected to the second external terminal via the second termination resistor. A second transmission circuit, wherein the first transmission circuit and the second transmission circuit operate based on the first voltage and the second voltage, respectively, and generate a first drive signal and a second drive signal. A driving circuit; a first switch connected between the first power supply wiring to which the first voltage is applied; and a first wiring; a second power supply wiring to which the second voltage is applied; A second switch connected in between, a first capacitor connected between the second power supply wiring and the first wiring, and a first capacitor connected between the first power supply wiring and the second wiring. Two capacitors, connected between the first wiring and the output node, and connected to the control terminal Having a first transistor drive signal is applied, which is connected between the second wiring and the output node, a second transistor, wherein the second driving signal is applied to the control terminal.

  According to one aspect of the present invention, communication speed can be increased.

It is a schematic explanatory drawing of the system which performs two-way communication. It is explanatory drawing which shows the logic of the various signals in the transmission circuit of 1st Embodiment. (A) is a circuit diagram of the transmission / reception circuit of the first embodiment, and (b) is a circuit diagram of the drive circuit of the first embodiment. It is an equivalent circuit diagram of the transmission circuit of the first embodiment. It is explanatory drawing of the capacitance value in the transmission circuit of 1st Embodiment. It is a timing diagram which shows the various signals in the transmission circuit of 1st Embodiment. It is a circuit diagram of the transmission / reception circuit of 2nd Embodiment. FIG. 6 is a circuit diagram of a drive circuit according to a second embodiment. It is explanatory drawing which shows the logic of the various signals in the transmission circuit of 2nd Embodiment. It is an equivalent circuit diagram of the transmission circuit of the second embodiment. (A) is a block diagram showing a state at the time of transmission, and (b) is a block diagram showing a state at the time of reception. (A) (b) is a schematic explanatory drawing of the communication system of a comparative example. It is a circuit diagram of the transmission circuit of a comparative example. It is explanatory drawing which shows the logic of the various signals in the transmission circuit of a comparative example. It is explanatory drawing of the capacitance value in the transmission circuit of a comparative example.

(Outline of communication system)
As shown in FIG. 1, this communication system includes two electronic devices 11 and 12 and a transmission path 13 that connects the electronic devices 11 and 12 to each other. The external terminals E1p and E1n of the electronic device 11 are connected to the external terminals E2p and E2n of the electronic device 12 through the transmission line 13. The electronic devices 11 and 12 are connected to each other via a transmission line 13 so that they can communicate with each other.

  The electronic device 11 is a host device such as a computer or a digital still camera, and the electronic device 12 is a peripheral device such as a memory card. The transmission path 13 indicates a path for transmitting a signal between the two electronic devices 11 and 12. When the electronic devices 11 and 12 are directly connected to each other, the transmission path 13 is a cable included in the electronic devices 11 and 12, wiring of a circuit board, or the like.

The electronic device 11 includes a control circuit (CPU) 21 and a transmission / reception circuit 22.
The control circuit 21 outputs the transmission data TD and the transmission enable signal TXEN to the transmission / reception circuit 22.

The transmission / reception circuit 22 includes a transmission circuit 23 and a reception circuit 24.
The transmission circuit 23 includes two transmission buffers 25 and 26 and an inverter circuit 27. The transmission buffer 25 is an example of a first transmission circuit, and the transmission buffer 26 is an example of a second transmission circuit.

The inverter circuit 27 outputs inverted data TDx obtained by logically inverting the transmission data TD.
Transmission data TD is supplied to the input terminal of the transmission buffer 25. The output terminal of the transmission buffer 25 is connected to the first terminal of the termination resistor R1p, and the second terminal of the termination resistor R1p is connected to the external terminal E1p. The termination resistor R1p is an example of a first termination resistor. The external terminal E1p is an example of a first external terminal.

  The inverted data TDx is supplied to the input terminal of the transmission buffer 26. The output terminal of the transmission buffer 26 is connected to the first terminal of the termination resistor R1n, and the second terminal of the termination resistor R1n is connected to the external terminal E1n. The termination resistor R1n is an example of a second termination resistor. The external terminal E1n is an example of a second external terminal. The termination resistors R1p and R1n are series termination resistors that match the impedance of the transmission buffers 25 and 26 with the characteristic impedance of the transmission line 13.

  The external terminals E1p and E1n are connected to two input terminals of the receiving circuit 24, respectively. That is, the input terminal of the receiving circuit 24 is connected to the nodes N1p and N1n to which the external terminals E1p and E1n and the termination resistors R1p and R1n are connected. The reception circuit 24 outputs reception data RD corresponding to the levels of the external terminals E1p and E1n to the control circuit 21.

The electronic device 12 has the same members as the electronic device 11. For this reason, about the member of the electronic device 12, the same code | symbol as the electronic device 11 is attached | subjected and description is abbreviate | omitted.
(First embodiment)
Next, a first embodiment of the transmission / reception circuit will be described.

As shown in FIG. 3A, the control circuit 21 outputs transmission data TD, a transmission enable signal TXEN, a termination enable signal TREN, and a switch control signal SWEN.
The transmission buffer 25 includes transistors T1p and T2p connected to the first terminal of the termination resistor R1p, and a drive circuit 25a that drives the transistors T1p and T2p. The transistor T1p is an example of a first transistor, and the transistor T2p is an example of a second transistor.

  The drive circuit 25a is connected to a wiring to which a high potential voltage VDD is applied (hereinafter referred to as a high potential power wiring VDD) and a wiring to which a low potential voltage VSS is applied (hereinafter referred to as a low potential power wiring VSS). The drive circuit 25a operates based on the high potential voltage VDD and the low potential voltage VSS. The drive circuit 25a generates a drive signal D1p for the transistor T1p and a drive signal D2p for the transistor T2p based on the transmission data TD, the transmission enable signal TXEN, and the termination enable signal TREN. The drive signal D1p is an example of a first drive signal, and the drive signal D2p is an example of a second drive signal. The high potential voltage VDD is an example of a first voltage, and the low potential voltage VSS is an example of a second voltage. The high potential power line VDD is an example of a first power line, and the low potential power line VSS is an example of a second power line.

  Transistor T1p is, for example, a P-channel MOS transistor, and transistor T2p is, for example, an N-channel MOS transistor. The source terminal of the transistor T1p is connected to the wiring PL1, the drain terminal of the transistor T1p is connected to the drain terminal of the transistor T2p, and the source terminal of the transistor T2p is connected to the wiring PL2. Although not shown, the back gate terminal of the transistor T1p is connected to the high potential power supply wiring VDD, and the back gate terminal of the transistor T2p is connected to the low potential power supply wiring VSS. A node N2p to which the drain terminal of the transistor T1p and the drain terminal of the transistor T2p are connected is an output terminal of the transmission buffer 25 and is connected to the first terminal of the termination resistor R1p. The wiring PL1 is an example of a first wiring, and the wiring PL2 is an example of a second wiring.

  The wiring PL1 is connected to the first terminal of the switch SW1p, and the second terminal of the switch SW1p is connected to the high potential power wiring VDD. The wiring PL2 is connected to the first terminal of the switch SW2p, and the second terminal of the switch SW2p is connected to the low potential power wiring VSS. The switches SW1p and SW2p are turned on / off based on the switch control signal SWEN. For example, the switches SW1p and SW2p are turned on in response to an H level switch control signal SWEN and turned off in response to an L level switch control signal SWEN. The switch SW1p is an example of a first switch, and the switch SW2p is an example of a second switch.

  A first terminal of the capacitor C1p is connected to the wiring PL1, and a second terminal of the capacitor C1p is connected to the wiring VSS. A first terminal of the capacitor C2p is connected to the wiring VDD, and a second terminal of the capacitor C2p is connected to the wiring PL2. The capacitor C1p is an example of a first capacitor, and the capacitor C2p is an example of a second capacitor.

  The transmission buffer 26 includes transistors T1n and T2n connected to the first terminal of the termination resistor R1n, and a drive circuit 26a that drives the transistors T1n and T2n. The transistor T1n is an example of a first transistor, and the transistor T2n is an example of a second transistor.

  The drive circuit 26a is connected to the high potential power wiring VDD and the low potential power wiring VSS. The drive circuit 26a operates based on the high potential voltage VDD and the low potential voltage VSS. The drive circuit 26a generates a drive signal D1n for the transistor T1n and a drive signal D2n for the transistor T2n based on the inverted data TDx, the transmission enable signal TXEN, and the termination enable signal TREN. The drive signal D1n is an example of a first drive signal, and the drive signal D2n is an example of a second drive signal.

  Transistor T1n is, for example, a P-channel MOS transistor, and transistor T2n is, for example, an N-channel MOS transistor. The source terminal of the transistor T1n is connected to the wiring PL1, the drain terminal of the transistor T1n is connected to the drain terminal of the transistor T2n, and the source terminal of the transistor T2n is connected to the wiring PL2. Although not shown, the back gate terminal of the transistor T1n is connected to the high potential power supply wiring VDD, and the back gate terminal of the transistor T2n is connected to the low potential power supply wiring VSS. A node N2n to which the drain terminal of the transistor T1n and the drain terminal of the transistor T2n are connected is an output terminal of the transmission buffer 26 and is connected to the first terminal of the termination resistor R1n.

  The wiring PL1 is connected to the first terminal of the switch SW1n, and the second terminal of the switch SW1n is connected to the high potential power wiring VDD. The wiring PL2 is connected to the first terminal of the switch SW2n, and the second terminal of the switch SW2n is connected to the low-potential power supply wiring VSS. The switches SW1n and SW2n are turned on / off based on the switch control signal SWEN. For example, the switches SW1n and SW2n are turned on in response to an H level switch control signal SWEN and turned off in response to an L level switch control signal SWEN. The switch SW1n is an example of a first switch, and the switch SW2n is an example of a second switch.

  A first terminal of the capacitor C1n is connected to the wiring PL1, and a second terminal of the capacitor C1n is connected to the wiring VSS. A first terminal of the capacitor C2n is connected to the wiring VDD, and a second terminal of the capacitor C2n is connected to the wiring PL2. The capacitor C1n is an example of a first capacitor, and the capacitor C2n is an example of a second capacitor.

As shown in FIG. 3B, the drive circuit 25a includes an AND circuit 31, an OR circuit 32, a NAND circuit 33, a NOR circuit 34, and inverter circuits 35 and 36.
The termination enable signal TREN is supplied to the inverter circuit 35. The output terminal of the inverter circuit 35 is connected to the input terminal of the AND circuit 31. The transmission data TD is supplied to the NAND circuit 33. A transmission enable signal TXEN is supplied to the input terminal of the NAND circuit 33. The output terminal of the NAND circuit 33 is connected to the input terminal of the AND circuit 31, and the AND circuit 31 outputs the drive signal D1p.

  The transmission enable signal TXEN is supplied to the inverter circuit 36. The output terminal of the inverter circuit 36 is connected to the input terminal of the NOR circuit 34. Transmission data TD is supplied to the input terminal of the NOR circuit 34. The output terminal of the NOR circuit 34 is connected to the input terminal of the OR circuit 32. A termination enable signal TREN is supplied to the input terminal of the OR circuit 32. The OR circuit 32 outputs a drive signal D2p.

FIG. 2 shows logical values of signals in the transmission / reception circuit 22 of the first embodiment.
For example, when transmitting “0”, the control circuit 21 shown in FIG. 3A transmits L level transmission data TD, H level transmission enable signal TXEN, L level termination enable signal TREN, and H level switch control signal SWEN. Is output.

  The switches SW1p and SW2p are turned on in response to the H level switch control signal SWEN. Accordingly, the high potential voltage VDD is supplied to the wiring PL1, and the low potential voltage VSS is supplied to the wiring PL2.

  The drive circuit 25a of the transmission buffer 25 generates drive signals D1p and D2p of a level corresponding to the transmission data TD based on the H level transmission enable signal TXEN and the L level termination enable signal TREN. For example, the drive circuit 25a generates H level drive signals D1p and D2p based on L level transmission data TD. The transistor T1p is turned off in response to the H level drive signal D1p, and the transistor T2p is turned on in response to the H level drive signal D2p. The turned on transistor T2p connects the node N2p to the wiring PL2. Therefore, the transmission buffer 25 drives the external terminal E1p to the low potential voltage VSS level (L level).

  The control circuit 21 outputs H-level transmission data TD, H-level transmission enable signal TXEN, L-level termination enable signal TREN, and H-level switch control signal SWEN when “1” is transmitted. The drive circuit 25a generates L level drive signals D1p and D2p based on the H level transmission data TD. The transistor T1p is turned on in response to the L level drive signal D1p, and the transistor T2p is turned off in response to the L level drive signal D2p. The transistor T1p that is turned on connects the node N2p to the wiring PL1. Therefore, the transmission buffer 25 drives the external terminal E1p to the high potential voltage VDD level (H level).

  Further, at the time of reception, the control circuit 21 outputs an L level transmission enable signal TXEN, an H level termination enable signal TREN, and an L level switch control signal SWEN. The drive circuit 25a generates an L level drive signal D1p and an H level drive signal D2p based on the H level termination enable signal TREN. The transistor T1p is turned on in response to the L level drive signal D1p. The transistor T2p is turned on in response to the drive signal D2p at the H level. At this time, the switches SW1p and SW2p are turned off based on the L level switch control signal SWEN. Drive circuit 25a connects node N2p to wiring PL1 and wiring PL2.

  Further, the control circuit 21 outputs an L level transmission enable signal TXEN, an L level termination enable signal TREN, and an L level switch control signal SWEN during non-communication. The drive circuit 25a generates an H level drive signal D1p and an L level drive signal D2p based on the L level transmission enable signal TXEN and the L level termination enable signal TREN. The transistor T1p is turned off in response to the H level drive signal D1p, and the transistor T2p is turned off in response to the L level drive signal D2p.

  The drive circuit 26a shown in FIG. 3A is the same as the drive circuit 25a. In FIG. 3B, reference numerals for the drive circuit 26a are shown in parentheses. The drive circuit 26a generates drive signals D1n and D2n based on the inverted data TDx, the transmission enable signal TXEN, and the termination enable signal TREN.

(Comparative example)
Next, a communication system of a comparative example will be described.
In the description of the comparative example, the same reference numerals may be used for the same members as those in the above embodiment.

  As shown in FIG. 12A, the two electronic devices 101 and 102 of this communication system are connected to each other via a transmission path 103 so as to communicate with each other. The external terminals E1p and E1n of the electronic device 101 are connected to the external terminals E2p and E2n of the electronic device 102 via the transmission path 103.

  The electronic device 101 has a transmission / reception circuit 110. The electronic device 102 has a transmission / reception circuit similar to the electronic device 101. The electronic device 102 is denoted by the same reference numeral as the transmission / reception circuit of the electronic device 101. Then, the transmission / reception circuit 110 of the electronic device 101 will be described.

  The transmission / reception circuit 110 includes a transmission circuit 111 and a reception circuit 112. The transmission circuit 111 includes two transmission buffers 113 and 114. The output terminals of the transmission buffers 113 and 114 are connected to external terminals E1p and E1n via termination resistors R1p and R1n, respectively. The external terminals E1p and E1n are connected to the input terminal of the receiving circuit 112, and the receiving circuit 112 outputs received data RD corresponding to the levels of the external terminals E1p and E1n.

A termination circuit 115 is connected between the wiring L1 between the external terminal E1p and the termination resistor R1p and between the wiring L2 between the external terminal E1n and the termination resistor R1n.
As shown in FIG. 12B, the termination circuit 115 includes termination resistors R2p and R2n, switches SWC1 and SWC2, and a capacitor Cc. The termination resistor R2p, the switches SWC1 and SWC2, and the termination resistor R2n are connected in series between the wiring L1 and the wiring L2 in this order. When the switches SWC1 and SWC2 are turned on, the termination resistors R2p and R2n terminate between the wiring L1 and the wiring L2, that is, between the external terminals E1p and E2n shown in FIG. A capacitor Cc having one end connected to the node NC between the switches SWC1 and SWC2 and the other end connected to the low-potential power line VSS is a center tap capacitor, and is used as a countermeasure against common mode noise.

As shown in FIG. 13, the control circuit 120 outputs transmission data TD, a transmission enable signal TXEN, and a termination enable signal TREN.
The transmission buffer 113 includes a NAND circuit 121, a NOR circuit 122, an inverter circuit 123, and transistors T101 and T102. Transistor T101 is, for example, a P-channel MOS transistor, and transistor T102 is, for example, an N-channel MOS transistor. The transistors T101 and T102 are connected in series between the high-potential power supply line VDD and the low-potential power supply line VSS, and the node between the transistors T101 and T102 is connected to the termination resistor R1p.

The NAND circuit 121 outputs a drive signal based on the transmission data TD output from the control circuit 120 and the transmission enable signal TXEN.
The inverter circuit 123 outputs a signal obtained by logically inverting the transmission enable signal TXEN output from the control circuit 120. The NOR circuit 122 outputs a drive signal based on the transmission data TD and the output signal of the inverter circuit 123.

A capacitor C31 is connected between the high potential power supply line VDD and the low potential power supply line VSS. The capacitor C31 suppresses voltage fluctuations in the power supply wirings VDD and VSS.
The transmission buffer 114 includes a NAND circuit 131, a NOR circuit 132, an inverter circuit 133, and transistors T111 and T112, which are connected in the same manner as the transmission buffer 113 described above. The capacitor C32 connected between the high potential power supply wiring VDD and the low potential power supply wiring VSS suppresses voltage fluctuations in the power supply wirings VDD and VSS.

  Switches SWC1 and SWC2 shown in FIG. 12B are, for example, N-channel MOS transistors as shown in FIG. The control circuit 120 outputs a switch control signal SWEN having a level corresponding to the operation state (during transmission and reception). The switches SWC1 and SWC2 are turned on / off based on the switch control signal SWEN.

  FIG. 14 shows the logical values of transmission data TD, transmission enable signal TXEN, termination enable signal TREN, and states of external terminals E1p and E1n at the time of “0” transmission, “1”, transmission, reception, and non-communication. Show.

  In the transmission circuit 111 shown in FIG. 13, the terminal capacitances at the external terminals E1p and E1n affect the increase in communication speed. The terminal capacitance at the external terminal E1p includes a parasitic capacitance Cp11 on the line between the external terminal E1p and the termination resistor R1p, and a parasitic capacitance Cp12 on the line between the external terminal E1p and the termination resistor R2p. Similarly, the terminal capacitance at the external terminal E1n includes a parasitic capacitance Cp21 in the wiring L2 between the external terminal E1n and the termination resistor R1n, and a parasitic capacitance Cp22 in a line between the external terminal E1n and the termination resistor R2n.

  FIG. 15 shows the terminal capacitance, the capacitance between the high potential power supply wiring VDD and the low potential power supply wiring VSS (capacitance between power supplies), and the capacitance value of the center tap capacitance (Center-Tap capacitance) during transmission and reception. Has been. “Cptx” is the capacitance value of the parasitic capacitances Cp11 and Cp21 shown in FIG. 12, and “Cptm” is the capacitance value of the parasitic capacitances Cp12 and Cp22. “Cpas” is the capacitance value of the capacitors C31 and C32, and “Ctap” is the capacitance value of the capacitor Cc.

In order to increase the communication speed, it is necessary to reduce the terminal capacity. When the voltage and impedance of the signal are determined, the terminal capacity is an important parameter that determines the upper limit of the communication speed.
In general, it is preferable that the capacitance value of the inter-power source capacitance that suppresses a transient voltage drop and the capacitance value of the center tap capacitance that suppresses common mode noise be larger. However, a capacitor having a large capacity causes an increase in the area of the semiconductor device (chip) on which the transmission / reception circuit is formed, resulting in an increase in cost.

(Function)
Next, the operation of the transmission / reception circuit 22 of the first embodiment will be described.
[When sending]
The control circuit 21 shown in FIG. 3A outputs an H level (“1”) transmission enable signal TXEN and an L level ([0]) termination enable signal TREN. The control circuit 21 outputs an H level switch control signal SWEN. Each switch SW1p, SW2p, SW1n, SW2n is turned on based on an H level switch control signal SWEN.

  The high potential voltage VDD is applied to the wiring PL1 by the switch SW1p that is turned on. Further, the low potential voltage VSS is applied to the wiring PL2 by the switch SW2p that is turned on. The capacitors C1p and C2p include a wiring to which the high potential voltage VDD is applied (high potential power wiring VDD and wiring PL1) and a wiring to which the low potential voltage VSS is applied (low potential power wiring VSS and wiring PL2). Connected between. Therefore, the capacitors C1p and C2p serve as bypass capacitors (capacitance between power supplies) connected between the power supply terminals of the transmission circuit 23.

  Similarly, the high potential voltage VDD is applied to the wiring PL1 by the switch SW1n that is turned on. Further, the low potential voltage VSS is applied to the wiring PL2 by the switch SW2n that is turned on. The capacitors C1n and C2n include a wiring to which the high potential voltage VDD is applied (high potential power wiring VDD and wiring PL1) and a wiring to which the low potential voltage VSS is applied (low potential power wiring VSS and wiring PL2). Connected between. Therefore, the capacitors C1n and C2n function as bypass capacitors (capacitance between power supplies) connected between the power supply terminals of the transmission buffer 26.

  Then, the drive circuit 25a shown in FIG. 3B generates drive signals D1p and D2p based on the transmission data TD. For example, the drive circuit 25a generates L level drive signals D1p and D2p based on the H level transmission data TD. The transistor T1p is turned on based on the L level drive signal D1p, and the transistor T2p is turned off based on the L level drive signal D2p. Accordingly, the transmission circuit 23 outputs the transmission signal TXp at the H level (high potential voltage VDD level) based on the transmission data TD at the H level. Further, the transmission circuit 23 outputs an L level (low potential voltage VSS level) transmission signal TXp based on the L level transmission data TD.

  Similarly, the drive circuit 26a generates drive signals D1n and D2n based on the inverted data TDx. For example, the drive circuit 26a generates H level drive signals D1n and D2n based on the L level inverted data TDx. The transistor T1n is turned off based on the H level drive signal D1n, and the transistor T2n is turned on based on the H level drive signal D2n. Accordingly, the transmission circuit 23 outputs the L level transmission signal TXn based on the L level inverted data TDx (H level transmission data TD). The transmission circuit 23 outputs an H level transmission signal TXn based on the H level inverted data TDx (L level transmission data TD).

  As shown in FIG. 3A, the external terminal E1p is connected to the termination resistor R1p, and the external terminal E1n is connected to the termination resistor R1n. The present embodiment does not include a termination circuit (see FIG. 13) between the external terminals E1p and E1n. Therefore, the parasitic capacitance Cp11 in the wiring between the external terminal E1p and the termination resistor R1p is a terminal capacitance with respect to the external terminal E1p. Similarly, the parasitic capacitance Cp21 in the wiring between the external terminal E1n and the termination resistor R1n is a terminal capacitance with respect to the external terminal E1n. The capacitance values of these parasitic capacitors Cp11 and Cp21 are set to “Cptx”.

  Capacitors C1p and C2p function as bypass capacitors (capacitance between power supplies) connected between power supply terminals of the transmission buffer 25, and capacitors C1n and C2n are bypass capacitors (capacitance between power supplies) connected between power supply terminals of the transmission buffer 26. ) Work as. The capacitance values of the capacitors C1p and C2n are set to “Cpas”, and the capacitance values of the capacitors C2p and C1n are set to ½ of “Ctap”.

  As shown in FIG. 5, the terminal capacitance at the time of transmission is “Cptx”. Therefore, in the transmission / reception circuit 22 (transmission circuit 23) of the present embodiment, the terminal capacitance at the time of transmission is smaller than the terminal capacitance in the transmission circuit 111 shown in FIG. For this reason, it is possible to increase the speed of the transmission signals TXp, TXn in the transmission circuit 23.

  The capacitance value between the power supplies is “2 × Cpas + Ctap”. That is, in the transmission / reception circuit 22 (transmission circuit 23) of the present embodiment, the capacity between power supplies at the time of transmission is larger than the capacity between power supplies in the transmission circuit 111 shown in FIG. Therefore, voltage fluctuations of the high potential voltage VDD and the low potential voltage VSS are suppressed during transmission.

[When receiving]
The control circuit 21 shown in FIG. 3A outputs an L level switch control signal SWEN. Each switch SW1p, SW2p, SW1n, SW2n is turned off based on the L level switch control signal SWEN.

Further, the control circuit 21 outputs an L level (“1”) transmission enable signal TXEN and an H level ([0]) termination enable signal TREN.
The drive circuit 25a generates an L level drive signal D1p and an H level drive signal D2p based on the H level termination enable signal TREN. The transistor T1p is turned on based on the L level drive signal D1p, and the transistor T2p is turned on based on the H level drive signal D2p. The turned on transistor T1p connects the wiring PL1 to the first terminal of the termination resistor R1p. As a result, the capacitor C1p is connected between the low-potential power supply line VSS and the termination resistor R1p. Similarly, the turned-on transistor T2p connects the wiring PL2 to the first terminal of the termination resistor R1p. Thereby, the capacitor C2p is connected between the high-potential power supply wiring VDD and the termination resistor R1p.

  Similarly, the drive circuit 26a generates an L level drive signal D1n and an H level drive signal D2n based on the H level termination enable signal TREN. The transistor T1n is turned on based on the L level drive signal D1n, and the transistor T2n is turned on based on the H level drive signal D2n. The turned-on transistor T1n connects the wiring PL1 to the first terminal of the termination resistor R1n. Thereby, the capacitor C1n is connected between the low-potential power supply line VSS and the termination resistor R1n. Similarly, the turned-on transistor T2n connects the wiring PL2 to the first terminal of the termination resistor R1n. As a result, the capacitor C2n is connected between the high-potential power supply wiring VDD and the termination resistor R1n.

  FIG. 4 is an equivalent circuit of the transmission / reception circuit 22 at the time of reception. In FIG. 4, the receiving circuit 24 and the driving circuits 25a and 26a shown in FIG. Further, the transistors T1p, T2p, T1n, and T2n are shown as on-state switches.

  In FIG. 4, the external terminal E1p is connected to the external terminal E1n via a termination resistor R1p, transistors T1p, T2p (T1n, T2n), and a termination resistor R1n. Therefore, the external terminal E1p and the external terminal E1n are short-circuited by the termination resistors R1p and R1n.

  The node to which the transistor T1p and the transistor T2p are connected is a wiring PL1 shown in FIG. 3A. The wiring PL1 is connected to the first terminals of the capacitors C1p and C1n, and the second terminals of the capacitors C1p and C1n. The terminal is connected to the low potential power wiring VSS. Therefore, the capacitors C1p and C1n function as a center tap capacitance (Center-Tap capacitance) connected between the node between the external terminal E1p and the external terminal E1n and the low potential power supply line VSS.

  The node to which the transistor T1n and the transistor T2n are connected is a wiring PL2 shown in FIG. 3A. The second terminal of the capacitors C2p and C2n is connected to the wiring PL2, and the first terminals of the capacitors C2p and C2n are connected. The terminal is connected to the high potential power wiring VDD. Therefore, the capacitors C2p and C2n function as a center tap capacitance (Center-Tap capacitance) connected between the node between the external terminal E1p and the external terminal E1n and the high potential power supply wiring VDD.

  As shown in FIG. 5, the terminal capacitance at the time of reception is “Cptx”. Therefore, in the transmission / reception circuit 22 of the present embodiment, the terminal capacitance at the time of reception is smaller than the terminal capacitance in the transmission / reception circuit 110 shown in FIG.

  The capacitance value of the center tap capacitance (Center-Tap capacitance) is “2 × Cpas + Ctap”. That is, in the transmission / reception circuit 22 of the present embodiment, the center tap capacitance (Center-Tap capacitance) at the time of reception is larger than the center tap capacitance (capacitor C2) shown in FIG. Therefore, the transmission / reception circuit 22 of the present embodiment suppresses common mode noise during reception as compared with the comparative example.

[Non-communication]
The control circuit 21 shown in FIG. 3A outputs an L level switch control signal SWEN. Each switch SW1p, SW2p, SW1n, SW2n is turned off based on the L level switch control signal SWEN.

  Further, the control circuit 21 outputs an L level (“1”) transmission enable signal TXEN and an L level ([0]) termination enable signal TREN. At this time, the drive circuit 25a generates an H level drive signal D1p and an L level drive signal D2p. The transistor T1p is turned off based on the H level drive signal D1p. The transistor T2p is turned off based on the L level drive signal D2p. Similarly, the drive circuit 26a generates an H level drive signal D1n and an L level drive signal D2n. The transistor T1n is turned off based on the H level drive signal D1n. The transistor T2n is turned off based on the L level drive signal D2n. Therefore, the external terminal E1p and the external terminal E1n are in an open state.

FIG. 6 shows changes in the transmission enable signal TXEN, the termination enable signal TREN, and the switch control signal SWEN by the control circuit 21.
The control circuit 21 changes the state of the transmission / reception circuit 22 from “when receiving” to “when not communicating” and then “when transmitting”. That is, as shown in FIG. 6, after the termination enable signal TREN is lowered from the H level to the L level, the switch control signal SWEN is raised from the L level to the H level. In addition, the control circuit 21 changes the state of the transmission / reception circuit 22 from “at the time of transmission” to “at the time of non-communication” and then “at the time of reception”. That is, as shown in FIG. 6, after the switch control signal SWEN falls from the H level to the L level, the termination enable signal TREN rises from the L level to the H level. In FIG. 6, periods k1 and k2 are “non-communication”. Therefore, the control circuit 21 turns on and off the switches SW1p, SW2p, SW1n, and SW2n with the transistors T1p, T2p, T1n, and T2n of the transmission buffers 25 and 26 turned off. As a result, the control circuit 21 prevents a through current between the high potential power supply wiring VDD and the low potential power supply wiring VSS.

  Then, the transmission enable signal TXEN is set to the H level in the period during which the L level termination enable signal TREN is output. Based on the H level transmission enable signal TXEN, the transmission data TD becomes valid data (Valid Data), and transmission signals TXp and TXn corresponding to the transmission data TD (inverted data TDx) are output. Note that the timing of the transmission enable signal TXEN may be the same as the timing of the switch control signal SWEN. In other words, the switch control signal SWEN may be generated based on the transmission enable signal TXEN. Further, the transmission enable signal TXEN may be applied to each switch SW1p, SW2p, SW1n, SW2n as a switch control signal SWEN.

As described above, according to the present embodiment, the following effects can be obtained.
(1-1) The output nodes N2p and N2n of the transmission buffers 25 and 26 of the transmission / reception circuit 22 are connected to external terminals E1p and E1n via termination resistors R1p and R1n.

  The transmission buffer 25 includes a transistor T1p connected to the output node N2p and the wiring PL1, and a transistor T2p connected to the output node N2p and the wiring PL2. The wiring PL1 is connected to the power supply wiring VDD to which the high potential voltage VDD is supplied via the switch SW1p, and the wiring PL2 is connected to the power supply wiring VSS to which the low potential voltage VSS is supplied via the switch SW2p. A capacitor C1p is connected between the wiring PL1 and the low potential power wiring VSS.

  The transmission buffer 26 includes a transistor T1n connected to the output node N2n and the wiring PL1, and a transistor T2n connected to the output node N2n and the wiring PL2. The wiring PL1 is connected to the power supply wiring VDD to which the high potential voltage VDD is supplied via the switch SW1n, and the wiring PL2 is connected to the power supply wiring VSS to which the low potential voltage VSS is supplied via the switch SW2n. A capacitor C1n is connected between the wiring PL1 and the low potential power wiring VSS.

  At the time of reception, the switches SW1p, SW2p, SW1n, SW2n are turned off, and the wirings PL1, PL2 are disconnected from the high potential power wiring VDD and the low potential power wiring VSS. Then, the transistors T1p, T2p, T1n, T2n are turned on. Thereby, the external terminal E1p is connected to the external terminal E1n via the termination resistors R1p and R1n. One end of capacitors C1p and C1n is connected to the wiring PL1 which is a node between both termination resistors R1p and R1n, and the other end of the capacitors C1p and C1n is connected to the low-potential power supply wiring VSS. Therefore, the capacitors C1p and C1n function as a center tap capacitance (Center-Tap capacitance) connected to an intermediate node between the external terminals E1p and E1n.

  The transmission / reception circuit 22 of this embodiment is not provided with a termination circuit corresponding to the reception circuit 24. For this reason, the terminal capacitance at the time of reception is smaller than the terminal capacitance in the transmission / reception circuit 110 provided with the termination circuit. For this reason, it is possible to increase the speed of the transmission signals TXp, TXn in the transmission circuit 23.

  (1-2) The capacitance value of the center tap capacitance (Center-Tap capacitance) is “2 × Cpas + Ctap”. That is, in the transmission / reception circuit 22 of the present embodiment, the center tap capacitance (Center-Tap capacitance) at the time of reception is larger than the center tap capacitance (capacitor C2) shown in FIG. Therefore, the transmission / reception circuit 22 of the present embodiment can suppress common mode noise during reception more than the comparative example.

  (1-3) A capacitor C1p is connected between the wiring PL1 and the low potential power wiring VSS, and a capacitor C2p is connected between the wiring PL2 and the high potential power wiring VDD. The capacitors C1p and C2p function as inter-power source capacitors when the switches SW1p and SW2p are turned on. Similarly, a capacitor C1n is connected between the wiring PL1 and the low potential power wiring VSS, and a capacitor C2n is connected between the wiring PL2 and the high potential power wiring VDD. The capacitors C1n and C2n function as inter-power source capacitors when the switches SW1n and SW2n are turned on.

  Capacitors C1p and C2p function as bypass capacitors (capacitance between power supplies) connected between power supply terminals of the transmission buffer 25, and capacitors C1n and C2n are bypass capacitors (capacitance between power supplies) connected between power supply terminals of the transmission buffer 26. ) Work as. The capacitance values of the capacitors C1p and C2n are set to “Cpas”, and the capacitance values of the capacitors C2p and C1n are set to ½ of “Ctap”. The capacity value of the inter-power supply capacity is “2 × Cpas + Ctap”. That is, in the transmission / reception circuit 22 (transmission circuit 23) of the present embodiment, the capacity between power supplies at the time of transmission is larger than the capacity between power supplies in the transmission circuit 111 shown in FIG. Therefore, voltage fluctuations of the high potential voltage VDD and the low potential voltage VSS can be suppressed during transmission.

  (1-4) The transmission / reception circuit 22 of the present embodiment is not provided with a termination circuit corresponding to the reception circuit 24. For this reason, the increase in the area required for forming the capacitors C1p, C2p, C1n, and C2n is small as the capacitance value increases. Therefore, an increase in the chip area of the semiconductor device including the transmission / reception circuit 22 can be suppressed.

(Second Embodiment)
Hereinafter, a second embodiment of the transmission / reception circuit will be described.
In this embodiment, the same components as those in the above embodiment may be denoted by the same reference numerals, and all or part of the description thereof may be omitted.

As shown in FIG. 7, the transmission / reception circuit 50 includes a transmission circuit 51 and a reception circuit 24.
The transmission circuit 51 includes two transmission circuits 52 and 53, an inverter circuit 54, and OR circuits 55 and 56.

  The transmission circuit 52 has a plurality (two in this embodiment) of transmission buffers 61 and 62. The transmission buffer 61 is an example of a first transmission circuit, and the transmission buffer 62 is an example of a second transmission circuit. The transmission circuit 53 includes a plurality (two in this embodiment) of transmission buffers 71 and 72. The transmission buffer 71 is an example of a third transmission circuit, and the transmission buffer 72 is an example of a fourth transmission circuit.

  The control circuit 21a outputs transmission data TD, a transmission enable signal TXEN, a termination enable signal TREN, and a switch control signal SWEN. The control circuit 21 a outputs selection signals SEL 1 and SEL 2 corresponding to the transmission buffers 61 and 62 of the transmission circuit 52 and the transmission buffers 71 and 72 of the transmission circuit 53.

  The OR circuit 55 (first OR circuit) outputs a switch control signal SE1 based on the switch control signal SWEN and the selection signal SEL1. The switch control signal SE1 is supplied to the transmission buffers 61 and 71.

  The OR circuit 56 (second OR circuit) outputs a switch control signal SE2 based on the switch control signal SWEN and the selection signal SEL2. The switch control signal SE2 is supplied to the transmission buffers 62 and 72.

  The transmission buffer 61 includes transistors T11p and T12p connected to the first terminal of the termination resistor R1p, and a drive circuit 61a that generates drive signals D11p and D12p for the transistors T11p and T12p. The drive circuit 61a is an example of a first drive circuit.

  The drive circuit 61a is connected to a wiring to which the high potential voltage VDD is applied (high potential power wiring VDD) and a wiring to which the low potential voltage VSS is applied (low potential power wiring VSS). The drive circuit 61a operates based on the high potential voltage VDD and the low potential voltage VSS. The drive circuit 61a generates a drive signal D11p for the transistor T11p and a drive signal D12p for the transistor T12p based on the transmission data TD, the transmission enable signal TXEN, the termination enable signal TREN, and the selection signal SEL1.

  Transistor T11p is, for example, a P-channel MOS transistor, and transistor T12p is, for example, an N-channel MOS transistor. The source terminal of the transistor T11p is connected to the wiring PL1a, the drain terminal of the transistor T11p is connected to the drain terminal of the transistor T12p, and the source terminal of the transistor T12p is connected to the wiring PL2a. Although not shown, the back gate terminal of the transistor T11p is connected to the high potential power supply wiring VDD, and the back gate terminal of the transistor T12p is connected to the low potential power supply wiring VSS. A node N22p to which the drain terminal of the transistor T11p and the drain terminal of the transistor T12p are connected is an output terminal of the transmission buffer 61 and is connected to the first terminal of the termination resistor R1p. The wiring PL1a is an example of a first wiring, and the wiring PL2a is an example of a second wiring.

  The wiring PL1a is connected to the first terminal of the switch SW11p, and the second terminal of the switch SW11p is connected to the high potential power wiring VDD. The wiring PL2a is connected to the first terminal of the switch SW12p, and the second terminal of the switch SW12p is connected to the low potential power supply wiring VSS. The switches SW11p and SW2p are turned on / off based on the switch control signal SE1. For example, the switches SW11p and SW2p are turned on in response to the H level switch control signal SE1 and turned off in response to the L level switch control signal SE1.

  A first terminal of the capacitor C11p is connected to the wiring PL1a, and a second terminal of the capacitor C11p is connected to the wiring VSS. A first terminal of the capacitor C12p is connected to the wiring VDD, and a second terminal of the capacitor C12p is connected to the wiring PL2a.

  The transmission buffer 62 includes transistors T21p and T22p connected to the first terminal of the termination resistor R1p, and a drive circuit 62a that generates drive signals D21p and D22p for the transistors T21p and T22p. The drive circuit 62a is an example of a second drive circuit.

  The drive circuit 62a is connected to a wiring to which the high potential voltage VDD is applied (high potential power wiring VDD) and a wiring to which the low potential voltage VSS is applied (low potential power wiring VSS). The drive circuit 62a operates based on the high potential voltage VDD and the low potential voltage VSS. The drive circuit 62a generates a drive signal D1p for the transistor T21p and a drive signal D2p for the transistor T22p based on the transmission data TD, the transmission enable signal TXEN, the termination enable signal TREN, and the selection signal SEL2.

  Transistor T21p is, for example, a P-channel MOS transistor, and transistor T22p is, for example, an N-channel MOS transistor. The source terminal of the transistor T21p is connected to the wiring PL1b, the drain terminal of the transistor T21p is connected to the drain terminal of the transistor T22p, and the source terminal of the transistor T22p is connected to the wiring PL2b. Although not illustrated, the back gate terminal of the transistor T21p is connected to the high potential power supply wiring VDD, and the back gate terminal of the transistor T22p is connected to the low potential power supply wiring VSS. A node N22p to which the drain terminal of the transistor T21p and the drain terminal of the transistor T22p are connected is an output terminal of the transmission buffer 62, and is connected to the first terminal of the termination resistor R1p. The wiring PL1b is an example of a third wiring, and the wiring PL2b is an example of a fourth wiring.

  The wiring PL1b is connected to the first terminal of the switch SW21p, and the second terminal of the switch SW21p is connected to the high potential power wiring VDD. The wiring PL2b is connected to the first terminal of the switch SW22p, and the second terminal of the switch SW22p is connected to the low potential power supply wiring VSS. The switches SW21p and SW2p are turned on / off based on the switch control signal SE2. For example, the switches SW21p and SW2p are turned on in response to the H level switch control signal SE2, and turned off in response to the L level switch control signal SE2.

  A first terminal of the capacitor C21p is connected to the wiring PL1b, and a second terminal of the capacitor C21p is connected to the wiring VSS. A first terminal of the capacitor C22p is connected to the wiring VDD, and a second terminal of the capacitor C22p is connected to the wiring PL2b.

  The transmission buffer 71 includes transistors T11n and T12n connected to the first terminal of the termination resistor R1n, and a drive circuit 71a that generates drive signals D11n and D12n for the transistors T11n and T12n. The drive circuit 71a is an example of a first drive circuit.

  The drive circuit 71a is connected to a wiring to which the high potential voltage VDD is applied (high potential power wiring VDD) and a wiring to which the low potential voltage VSS is applied (low potential power wiring VSS). The drive circuit 71a operates based on the high potential voltage VDD and the low potential voltage VSS. The drive circuit 71a generates a drive signal D11n for the transistor T11n and a drive signal D12n for the transistor T12n based on the inverted data TDx, the transmission enable signal TXEN, the termination enable signal TREN, and the selection signal SEL1.

  Transistor T11n is, for example, a P-channel MOS transistor, and transistor T12n is, for example, an N-channel MOS transistor. The source terminal of the transistor T11n is connected to the wiring PL1a, the drain terminal of the transistor T11n is connected to the drain terminal of the transistor T12n, and the source terminal of the transistor T12n is connected to the wiring PL2a. Although not shown, the back gate terminal of the transistor T11n is connected to the high potential power supply wiring VDD, and the back gate terminal of the transistor T12n is connected to the low potential power supply wiring VSS. A node N22n to which the drain terminal of the transistor T11n and the drain terminal of the transistor T12n are connected is an output terminal of the transmission buffer 71 and is connected to the first terminal of the termination resistor R1n.

  The wiring PL1a is connected to the first terminal of the switch SW11n, and the second terminal of the switch SW11n is connected to the high potential power wiring VDD. The wiring PL2a is connected to the first terminal of the switch SW12n, and the second terminal of the switch SW12n is connected to the low potential power supply wiring VSS. The switches SW11n and SW2n are turned on / off based on the switch control signal SE1. For example, the switches SW11n and SW2n are turned on in response to the H level switch control signal SE1 and turned off in response to the L level switch control signal SE1.

  A first terminal of the capacitor C11n is connected to the wiring PL1a, and a second terminal of the capacitor C11n is connected to the wiring VSS. A first terminal of the capacitor C12n is connected to the wiring VDD, and a second terminal of the capacitor C12n is connected to the wiring PL2a.

  The transmission buffer 72 includes transistors T21n and T22n connected to the first terminal of the termination resistor R1n, and a drive circuit 72a that generates drive signals D21n and D22n for the transistors T21n and T22n. The drive circuit 72a is an example of a second drive circuit.

  The drive circuit 72a is connected to a wiring to which the high potential voltage VDD is applied (high potential power wiring VDD) and a wiring to which the low potential voltage VSS is applied (low potential power wiring VSS). The drive circuit 72a operates based on the high potential voltage VDD and the low potential voltage VSS. The drive circuit 72a generates a drive signal D1n for the transistor T21n and a drive signal D2n for the transistor T22n based on the inverted data TDx, the transmission enable signal TXEN, the termination enable signal TREN, and the selection signal SEL2.

  Transistor T21n is, for example, a P-channel MOS transistor, and transistor T22n is, for example, an N-channel MOS transistor. The source terminal of the transistor T21n is connected to the wiring PL1b, the drain terminal of the transistor T21n is connected to the drain terminal of the transistor T22n, and the source terminal of the transistor T22n is connected to the wiring PL2b. Although not shown, the back gate terminal of the transistor T21n is connected to the high potential power supply wiring VDD, and the back gate terminal of the transistor T22n is connected to the low potential power supply wiring VSS. A node N22n to which the drain terminal of the transistor T21n and the drain terminal of the transistor T22n are connected is an output terminal of the transmission buffer 72, and is connected to the first terminal of the termination resistor R1n.

  The wiring PL1b is connected to the first terminal of the switch SW21n, and the second terminal of the switch SW21n is connected to the high potential power wiring VDD. The wiring PL2b is connected to the first terminal of the switch SW22n, and the second terminal of the switch SW22n is connected to the low potential power supply wiring VSS. The switches SW21n and SW2n are turned on / off based on the switch control signal SE2. For example, the switches SW21n and SW2n are turned on in response to the H level switch control signal SE2 and turned off in response to the L level switch control signal SE2.

  A first terminal of the capacitor C21n is connected to the wiring PL1b, and a second terminal of the capacitor C21n is connected to the wiring VSS. A first terminal of the capacitor C22n is connected to the wiring VDD, and a second terminal of the capacitor C22n is connected to the wiring PL2b.

As shown in FIG. 8, the drive circuit 61a includes AND circuits 81 and 82, OR circuits 83 and 84, a NAND circuit 85, a NOR circuit 86, and inverter circuits 87, 88, and 89.
The termination enable signal TREN is supplied to the inverter circuit 87. The output terminal of the inverter circuit 87 is connected to the input terminal of the OR circuit 84. The selection signal SEL1 is supplied to the input terminal of the OR circuit 84. The output terminal of the OR circuit 84 is connected to the input terminal of the AND circuit 81.

  The transmission data TD is supplied to the NAND circuit 85. A transmission enable signal TXEN is supplied to the input terminal of the NAND circuit 85. An output terminal of the NAND circuit 85 is connected to an input terminal of the AND circuit 81, and the AND circuit 81 outputs a drive signal D11p.

  The transmission enable signal TXEN is supplied to the inverter circuit 88. The output terminal of the inverter circuit 88 is connected to the input terminal of the NOR circuit 86. Transmission data TD is supplied to the input terminal of the NOR circuit 86. The output terminal of the NOR circuit 86 is connected to the input terminal of the OR circuit 83.

  The selection signal SEL1 is supplied to the inverter circuit 89. The output terminal of the inverter circuit 89 is connected to the input terminal of the AND circuit 82. A termination enable signal TREN is supplied to the input terminal of the AND circuit 82. The output terminal of the AND circuit 82 is connected to the OR circuit 83. The OR circuit 83 outputs a drive signal D12p.

  The drive circuits 62a, 71a, 72a shown in FIG. 7 include the same members as the drive circuit 61a shown in FIG. For this reason, drawings and descriptions showing circuit examples of the drive circuits 62a, 71a, 72a are omitted.

(Function)
Next, the operation of the transmission / reception circuit 50 of the second embodiment will be described.
FIG. 9 shows logical values of signals in the transmission / reception circuit 50 of the second embodiment.

[When sending]
The control circuit 21a shown in FIG. 7 outputs, for example, an L level selection signal SEL1 and an H level selection signal SEL2. For example, at the time of “0” transmission, the control circuit 21a outputs L level transmission data TD, H level transmission enable signal TXEN, L level termination enable signal TREN, and H level switch control signal SWEN.

The OR circuit 55 outputs an H level switch control signal SE1 based on the H level switch control signal SWEN and the L level selection signal SEL1.
The switches SW11p and SW12p of the transmission buffer 61 are turned on in response to the H level switch control signal SE1. Similarly, the switches SW11n and SW12n of the transmission buffer 71 are turned on in response to the H level switch control signal SE1. Accordingly, the high potential voltage VDD is supplied to the wiring PL1a, and the low potential voltage VSS is supplied to the wiring PL2a.

  The capacitors C11p and C12p are connected between the high potential power supply line VDD and the low potential power supply line VSS, respectively. Therefore, the capacitors C11p and C12p function as bypass capacitors (capacitance between power supplies) connected between the power supply terminals of the transmission buffer 61. Similarly, the capacitors C11n and C12n are connected between the high potential power supply line VDD and the low potential power supply line VSS, respectively. Therefore, the capacitors C11n and C12n function as bypass capacitors (capacitance between power supplies) connected between the power supply terminals of the transmission buffer 71.

The OR circuit 56 outputs an H level switch control signal SE2 based on the H level switch control signal SWEN and the H level selection signal SEL2.
The switches SW21p and SW22p of the transmission buffer 62 are turned on in response to the H level switch control signal SE2. Similarly, the switches SW21n and SW22n of the transmission buffer 72 are turned on in response to the H level switch control signal SE2. Accordingly, the high potential voltage VDD is supplied to the wiring PL1b, and the low potential voltage VSS is supplied to the wiring PL2b.

  The capacitors C21p and C22p are connected between the high potential power supply line VDD and the low potential power supply line VSS, respectively. Therefore, the capacitors C21p and C22p function as bypass capacitors (capacitance between power supplies) connected between the power supply terminals of the transmission buffer 62. Similarly, the capacitors C21n and C22n are connected between the high potential power supply line VDD and the low potential power supply line VSS, respectively. Therefore, the capacitors C21n and C22n function as bypass capacitors (capacitance between power supplies) connected between the power supply terminals of the transmission buffer 72.

  The drive circuit 61a of the transmission buffer 61 generates drive signals D11p and D12p at levels corresponding to the transmission data TD based on the transmission enable signal TXEN at H level, the termination enable signal TREN at L level, and the selection signal SEL1 at L level. To do. For example, the drive circuit 61a generates H level drive signals D11p and D12p based on the L level transmission data TD. The transistor T11p is turned off in response to the H level drive signal D11p, and the transistor T12p is turned on in response to the H level drive signal D12p. The turned-on transistor T12p connects the node N21p to the wiring PL2a.

  The drive circuit 62a of the transmission buffer 62 generates drive signals D21p and D22p at levels corresponding to the transmission data TD based on the H level transmission enable signal TXEN, the L level termination enable signal TREN, and the H level selection signal SEL2. To do. For example, the drive circuit 62a generates H level drive signals D21p and D22p based on the L level transmission data TD. The transistor T21p is turned off in response to the H level drive signal D21p, and the transistor T22p is turned on in response to the H level drive signal D22p. The turned-on transistor T22p connects the node N22p to the wiring PL2b.

  Therefore, the transmission circuit 52 drives the external terminal E1p to the low potential voltage VSS level (L level). That is, the transmission circuit 52 outputs the transmission signal TXp at the L level (low potential voltage VSS level) based on the transmission data TD at the L level.

  The drive circuit 71a of the transmission buffer 71 generates drive signals D11n and D12n at levels corresponding to the inverted data TDx based on the H level transmission enable signal TXEN, the L level termination enable signal TREN, and the L level selection signal SEL1. To do. For example, the drive circuit 61a generates L level drive signals D21n and D22n based on the H level inverted data TDx. The transistor T21n is turned on in response to the L level drive signal D21n, and the transistor T22n is turned off in response to the L level drive signal D22n. The turned-on transistor T21n connects the node N21n to the wiring PL1a.

  The drive circuit 72a of the transmission buffer 72 generates drive signals D21n and D22n at levels corresponding to the inverted data TDx based on the H level transmission enable signal TXEN, the L level termination enable signal TREN, and the H level selection signal SEL2. To do. For example, the drive circuit 62a generates L level drive signals D21n and D22n based on the H level inverted data TDx. The transistor T21n is turned on in response to the L level drive signal D21n, and the transistor T22n is turned off in response to the L level drive signal D22n. The turned-on transistor T21n connects the node N22n to the wiring PL1b.

  Therefore, the transmission circuit 53 drives the external terminal E1n to the high potential voltage VDD level (H level). That is, the transmission circuit 53 outputs the transmission signal TXn at the H level (high potential voltage VDD level) based on the inverted data TDx at the H level (transmission data TD at the L level).

  In the transmission buffer 61, the node N21p is connected to the first terminal of the termination resistor R1p. The transistor T11p of the transmission buffer 61 is connected between the node N21p and the wiring PL1a. The wiring PL1a is connected to the high potential power wiring VDD via the switch SW11p. Similarly, in the transmission buffer 62, the node N22p is connected to the first terminal of the termination resistor R1p. The transistor T21p of the transmission buffer 62 is connected between the node N22p and the wiring PL1b. The wiring PL1b is connected to the high potential power wiring VDD through the switch SW21p.

  Therefore, the transistor T11p of the transmission buffer 61 and the transistor T21p of the transmission buffer 62 are connected in parallel to each other between the high potential power supply line VDD and the termination resistor R1p. Thus, by connecting the transistors T11p and T21p in parallel, the resistance value between the high-potential power supply wiring VDD and the termination resistor R1p (the on-resistance value of the transistor) is reduced as compared with the case where one transistor is used. .

  Similarly, the transistor T12p of the transmission buffer 61 and the transistor T22p of the transmission buffer 62 also reduce the resistance value between the termination resistor R1p and the low-potential power supply line VSS. The same applies to the transmission buffers 71 and 72.

Further, the control circuit 21a outputs H-level transmission data TD, H-level transmission enable signal TXEN, and L-level termination enable signal TREN when “1” is transmitted.
The drive circuit 61a generates L level drive signals D11p and D12p based on the H level transmission data TD. The transistor T11p is turned on in response to the L level drive signal D11p, and the transistor T12p is turned off in response to the L level drive signal D12p. Similarly, the drive circuit 62a generates L level drive signals D21p and D22p based on the H level transmission data TD. The transistor T21p is turned on in response to the L level drive signal D21p, and the transistor T22p is turned off in response to the L level drive signal D22p. Therefore, the transmission circuit 52 outputs the transmission signal TXp at the H level (high potential voltage VDD level) based on the transmission data TD at the H level.

  The drive circuit 71a generates H level drive signals D11n and D12n based on the L level inverted data TDx. The transistor T11n is turned off in response to the H level drive signal D11n, and the transistor T12n is turned on in response to the H level drive signal D12n. Similarly, the drive circuit 72a generates H level drive signals D21n and D22n based on the L level inverted data TDx. The transistor T21n is turned off in response to the H level drive signal D21n, and the transistor T22n is turned on in response to the H level drive signal D22n. Therefore, the transmission circuit 53 outputs the transmission signal TXn at the L level (low potential voltage VSSVDD level) based on the inverted data TDx at L level (transmission data TD at H level).

[When receiving]
The control circuit 21a shown in FIG. 7 outputs an L level switch control signal SWEN.
The OR circuit 55 outputs an L level switch control signal SE1 based on the L level switch control signal SWEN and the L level selection signal SEL1. The switches SW11p and SW12p of the transmission buffer 61 are turned off in response to the L level switch control signal SE1. Similarly, the switches SW11n and SW12n of the transmission buffer 71 are turned off in response to the L level switch control signal SE1.

  The OR circuit 56 outputs an H level switch control signal SE2 based on the L level switch control signal SWEN and the H level selection signal SEL2. The switches SW21p and SW22p of the transmission buffer 62 are turned on in response to the H level switch control signal SE2. Similarly, the switches SW21n and SW22n of the transmission buffer 72 are turned on in response to the H level switch control signal SE2.

  The control circuit 21a outputs an L level transmission enable signal TXEN, an H level termination enable signal TREN, an L level selection signal SEL1, and an H level selection signal SEL2.

  The drive circuit 61a generates an L level drive signal D11p and an H level drive signal D12p based on the H level termination enable signal TREN and the L level selection signal SEL1. The transistor T1p is turned on in response to the L level drive signal D1p. The transistor T2p is turned on in response to the drive signal D2p at the H level. Similarly, the drive circuit 71a generates an L level drive signal D11n and an H level drive signal D12n based on the H level termination enable signal TREN and the L level selection signal SEL1. The transistor T11n is turned on based on the L level drive signal D11n, and the transistor T12n is turned on based on the H level drive signal D12n.

  The drive circuit 62a generates an H level drive signal D21p and an L level drive signal D22p based on the H level termination enable signal TREN and the H level selection signal SEL2. The transistor T21p is turned off based on the H level drive signal D21p, and the transistor T22p is turned off based on the H level drive signal D22p. Similarly, the drive circuit 72a generates an H level drive signal D21n and an L level drive signal D22n based on the H level termination enable signal TREN and the H level selection signal SEL2. The transistor T21n is turned off based on the H level drive signal D21n, and the transistor T22n is turned off based on the L level drive signal D22n.

  FIG. 10 is an equivalent circuit of the transmission / reception circuit 22 at the time of reception. In FIG. 10, the receiving circuit 24 and the drive circuits 61a, 62a, 71a, 72a shown in FIG. 7 are omitted. In addition, the transistors T11p, T12p, T11n, and T12n are shown as on-state switches, and the transistors T21p, T22p, T21n, and T22n are shown as off-state switches.

  In FIG. 10, the external terminal E1p is connected to the external terminal E1n via a termination resistor R1p, transistors T11p, T12p (T11n, T12n), and a termination resistor R1n. Therefore, the external terminal E1p and the external terminal E1n are short-circuited by the termination resistors R1p and R1n.

  A node to which the transistor T11p and the transistor T12p are connected is a wiring PL1a shown in FIG. 7. The wiring PL1a is connected to the first terminals of the capacitors C11p and C11n, and the second terminals of the capacitors C11p and C11n are low. It is connected to the potential power supply wiring VSS. Therefore, the capacitors C11p and C11n function as a center tap capacitance (Center-Tap capacitance) connected between the node between the external terminal E1p and the external terminal E1n and the low potential power supply line VSS.

  A node to which the transistor T11n and the transistor T12n are connected is a wiring PL2a shown in FIG. 7. The wiring PL2a is connected to the second terminals of the capacitors C12p and C12n, and the first terminals of the capacitors C12p and C12n are high. It is connected to the potential power supply wiring VDD. Therefore, the capacitors C12p and C12n function as a center tap capacitance (Center-Tap capacitance) connected between the node between the external terminal E1p and the external terminal E1n and the high potential power supply wiring VDD.

  On the other hand, the node to which the transistor T21p and the transistor T22p are connected is a wiring PL1b shown in FIG. 7. The wiring PL1b is connected to the first terminals of the capacitors C21p and C21n, and the second terminals of the capacitors C21p and C21n are low. It is connected to the potential power supply wiring VSS. The wiring PL1b is connected to the switch SW21p. It is connected to the high potential power wiring VDD by SW21n. Therefore, the capacitors C21p and C21n function as bypass capacitors (capacitance between power supplies) connected between the high potential power supply wiring VDD and the low potential power supply wiring VSS.

  A node to which the transistor T21n and the transistor T22n are connected is a wiring PL2b shown in FIG. 7. The wiring PL2b is connected to the second terminals of the capacitors C22p and C22n, and the first terminals of the capacitors C22p and C22n are high. It is connected to the potential power supply wiring VDD. The wiring PL2b is connected to the switch SW22p. It is connected to the low potential power wiring VSS by SW22n. Therefore, the capacitors C22p and C22n function as bypass capacitors (capacitance between power supplies) connected between the high potential power supply wiring VDD and the low potential power supply wiring VSS.

[Non-communication]
The control circuit 21a shown in FIG. 7 outputs an L-level transmission enable signal TXEN, an L-level termination enable signal TREN, and an L-level switch control signal SWEN. The drive circuit 61a generates an H level drive signal D11p and an L level drive signal D12p based on the L level transmission enable signal TXEN and the L level termination enable signal TREN. The transistor T11p is turned off in response to the H level driving signal D11p, and the transistor T12p is turned off in response to the L level driving signal D12p. Similarly, the drive circuit 62a generates an H level drive signal D21p and an L level drive signal D22p based on the L level transmission enable signal TXEN and the L level termination enable signal TREN. The transistor T21p is turned off in response to the H level drive signal D21p, and the transistor T22p is turned off in response to the L level drive signal D22p. Similarly, the drive circuits 71a and 72a generate H level drive signals D11n and D21n and L level drive signals D21n and D22n based on the L level transmission enable signal TXEN and the L level termination enable signal TREN. The transistors T11n and T21n are turned off in response to the H level drive signals D11n and D21n, and the transistors T12n and T22n are turned off in response to the L level drive signals D12n and D22n. Therefore, the external terminal E1p and the external terminal E1n are in an open state.

  That is, as shown in FIG. 11A, at the time of [transmission], the transmission / reception circuit 50 includes a reception circuit 24 and transmission circuits 52 and 53. Further, the transmission / reception circuit 50 includes capacitors C41 and C42 connected by the switches SW41 and SW42 that are turned on between the high-potential power line VDD and the low-potential power line VSS. The switch SW41 is the switch SW11p, SW12p, SW21p, SW22p shown in FIG. The capacitor C41 is the capacitors C11p, C12p, C21p, C22p shown in FIG. That is, the capacitance value of the capacitor C41 is the total value of the capacitors C11p, C12p, C21p, and C22p connected in parallel. Such a capacitor C41 suppresses voltage fluctuations in the power supply wirings VDD and VSS.

  Similarly, the switch SW42 is the switches SW11n, SW12n, SW21n, SW22n shown in FIG. The capacitor C42 is the capacitors C11n, C12n, C21n, C22n shown in FIG. That is, the capacitance value of the capacitor C42 is the total value of the capacitors C11n, C12n, C21n, and C22n connected in parallel. Such a capacitor C42 suppresses voltage fluctuations in the power supply wirings VDD and VSS.

  Then, as shown in FIG. 11B, at the time of reception, the transmission / reception circuit 50 includes a capacitor C51 connected between the high-potential power line VDD and the low-potential power line VSS by the switches SW51 and SW52 that are turned on. , C52. The switch SW51 is the switches SW21p and SW22p that are turned on as shown in FIG. The capacitor C51 is capacitors C21p and C22p shown in FIG. Similarly, as shown in FIG. 10, the switch SW52 is the switches SW21n and SW22n that are turned on, and the capacitor C52 is the capacitors C21p and C22p shown in FIG. That is, as shown in FIG. 7, the capacitors C21p, C22p, C21n, and C22n corresponding to the transmission buffers 62 and 72 function as a bypass capacitor (capacitance between power supplies) between the high potential power supply wiring VDD and the low potential power supply wiring VSS. .

  Further, as shown in FIG. 11B, the transmission / reception circuit 50 includes capacitors C53a and C53b connected to the terminating resistors R1p and R1n by the switch SW53 that is turned on. The switch SW53 is a switch that is turned on [when receiving], that is, the transistors T11p, T12p, T11n, and T12n shown in FIG. The capacitor C53a is a capacitor connected to the termination resistors R1p and R1n by the switched switch SW53, that is, the capacitors C12p and C12n shown in FIG. Similarly, the capacitor C53b is a capacitor connected to the termination resistors R1p and R1n by the switched switch SW53, that is, the capacitors C11p and C11n shown in FIG. These capacitors C11p, C11n, C12p, and C12n function as a center tap capacitance (Center-Tap capacitance).

As described above, according to the present embodiment, the following effects can be obtained.
(2-1) The same effects as (1-1) to (1-4) in the first embodiment are produced.
(2-2) The capacitors C21p, C22p, C21n, and C22n are connected between the high-potential power line VDD and the low-potential power line VSS by the switches SW21p, SW22p, SW21n, and SW22n that are turned on based on the switch control signal SE2. Connected. That is, when the switch control signal SWEN is at L level, the selection signal SEL2 at H level causes the capacitors C21p, C22p, C21n, C22n to act as bypass capacitors (capacitance between power supplies).

  The capacitors C11p, C11n, C12p, and C12n function as center tap capacities (Center-Tap capacities) when the switches SW11p, SW12p, SW11n, and SW12n are turned off based on the switch control signal SE1. That is, when the switch control signal SWEN is at L level, the L level selection signal SEL2 causes the capacitors C11p, C11n, C12p, and C12n to act as a center tap capacitance (Center-Tap capacitance).

  Therefore, the selection signals SEL1 and SEL2 assign the capacitors shown in FIG. 7 to a bypass capacitor (inter-power source capacitance) and a center tap capacitance (Center-Tap capacitance). The capacitor assignment can be changed by setting the levels of the selection signals SEL1 and SEL2.

In addition, you may implement each said embodiment in the following aspects.
In the second embodiment, for example, by setting the selection signals SEL1 and SEL2 to L level (logical value “0”), all the capacitors shown in FIG. Tap capacity).

  In the second embodiment, for example, each of the transmission circuits 52 and 53 is a transmission buffer including three transmission circuits, and the levels of the three selection signals are set as appropriate. Thereby, the allocation of the capacitors can be changed as appropriate.

In the second embodiment, a transmission / reception circuit including a plurality of transmission buffers 61 and 71 may be used. A transmission / reception circuit including a plurality of transmission buffers 62 and 72 may be used.
A transmission / reception circuit including a plurality of transmission buffers 61 and 71 and a plurality of transmission buffers 62 and 72 may be used. In this case, the number of transmission buffers 61 and 71 may be the same as or different from the number of transmission buffers 62 and 72.

The following additional notes are disclosed for each of the above forms.
(Appendix 1)
A first transmission circuit having an output node connected to a first external terminal via a first termination resistor;
A second transmission circuit having an output node connected to a second external terminal via a second termination resistor;
Including
The first transmission circuit and the second transmission circuit are respectively
A drive circuit that operates based on the first voltage and the second voltage and generates a first drive signal and a second drive signal;
A first switch connected between the first power supply wiring to which the first voltage is applied and the first wiring;
A second switch connected between a second power supply line to which the second voltage is applied and a second line;
A first capacitor connected between the second power supply wiring and the first wiring;
A first transistor connected between the first wiring and the output node, the first drive signal being applied to a control terminal;
A second transistor connected between the second wiring and the output node and having the second drive signal applied to a control terminal;
A transmission / reception circuit characterized by comprising:
(Appendix 2)
The drive circuit complementarily drives the first transistor and the second transistor according to the transmission data during transmission based on transmission data, a transmission control signal, and a termination control signal, and the first transistor during reception Generating the first drive signal and the second drive signal that turn on the second transistor;
The transmitter / receiver circuit according to appendix 1, characterized by:
(Appendix 3)
The drive circuit generates the first drive signal and the second drive signal to turn off the first transistor and the second transistor when not communicating;
The transmission / reception circuit according to appendix 2, characterized by:
(Appendix 4)
Each of the first transmission circuit and the second transmission circuit includes a second capacitor connected between the first power supply wiring and the second wiring;
The transmitter / receiver circuit according to any one of appendices 1 to 3, wherein:
(Appendix 5)
The first switch and the second switch are turned on and off based on a switch control signal;
The transmitter / receiver circuit according to any one of appendices 1 to 4, wherein:
(Appendix 6)
The first switch and the second switch are turned on and off based on a transmission control signal;
The transmitter / receiver circuit according to any one of appendices 1 to 4, wherein:
(Appendix 7)
A first transmission circuit and a second transmission circuit whose output nodes are connected to the first external terminal via a first termination resistor;
A third transmission circuit and a fourth transmission circuit, the output node of which is connected to the second external terminal via the second termination resistor;
Including
The first transmission circuit and the third transmission circuit are respectively
A first drive circuit that operates based on the first voltage and the second voltage and generates a first drive signal and a second drive signal;
A first switch connected between the first power supply line to which the first voltage is applied and the first line, and turned on and off based on a first switch control signal;
A second switch connected between a second power supply line to which the second voltage is applied and a second line and turned on and off based on the first switch control signal;
A first capacitor connected between the second power supply wiring and the first wiring;
A first transistor connected between the first wiring and the output node, the first drive signal being applied to a control terminal;
A second transistor connected between the second wiring and the output node and having the second drive signal applied to a control terminal;
Have
The second transmission circuit and the fourth transmission circuit are respectively
A second drive circuit that operates based on the first voltage and the second voltage and generates a third drive signal and a fourth drive signal;
A third switch connected between the first power supply wiring to which the first voltage is applied and the third wiring and turned on / off based on a second switch control signal;
A fourth switch connected between a second power supply line to which the second voltage is applied and a fourth line and turned on and off based on the second switch control signal;
A second capacitor connected between the second power supply wiring and the third wiring;
A third transistor connected between the third wiring and the output node, the third drive signal being applied to a control terminal;
A fourth transistor connected between the fourth wiring and the output node and having the fourth drive signal applied to a control terminal;
A transmission / reception circuit characterized by comprising:
(Appendix 8)
The first driving circuit complementarily drives the first transistor and the second transistor according to the transmission data at the time of transmission based on the transmission data, transmission control signal, and termination control signal, and the first at the time of reception. Generating the first drive signal and the second drive signal for driving the first transistor and the second transistor based on a selection signal;
The second drive circuit complementarily drives the third transistor and the fourth transistor according to the transmission data at the time of transmission based on the transmission data, the transmission control signal, and the termination control signal, and the second at the time of reception. Generating the third drive signal and the fourth drive signal for driving the third transistor and the fourth transistor based on a selection signal;
The transceiver circuit according to appendix 7, characterized by:
(Appendix 9)
A first OR circuit for generating the first switch control signal based on a switch control signal and the first selection signal;
A second OR circuit for generating the second switch control signal based on a switch control signal and the second selection signal;
The transmitter / receiver circuit according to appendix 8, characterized by comprising:
(Appendix 10)
The first drive circuit generates the first drive signal and the second drive signal that turn off the first transistor and the second transistor when not communicating,
The second drive circuit generates the third drive signal and the fourth drive signal to turn off the third transistor and the fourth transistor during non-communication;
10. The transmission / reception circuit according to appendix 8 or 9,
(Appendix 11)
Each of the first transmission circuit and the third transmission circuit has a third capacitor connected between the first power supply wiring and the second wiring;
Each of the second transmission circuit and the fourth transmission circuit includes a fourth capacitor connected between the first power supply wiring and the fourth wiring;
The transceiver circuit according to any one of appendices 7 to 10, characterized by:
(Appendix 12)
The switch control signal is a transmission control signal;
The transceiver circuit according to appendix 9, characterized by:
(Appendix 13)
A first transmission circuit having an output node connected to a first external terminal via a first termination resistor;
A second transmission circuit having an output node connected to a second external terminal via a second termination resistor;
Including
The first transmission circuit and the second transmission circuit are respectively
A first switch connected between the first power supply wiring to which the first voltage is applied and the first wiring;
A second switch connected between the second power supply wiring to which the second voltage is applied and the second wiring;
A first capacitor connected between the second power supply wiring and the first wiring;
A first transistor connected between the first wiring and the output node;
A second transistor connected between the second wiring and the output node;
A control method for controlling a control circuit comprising:
At the time of transmission, the first switch and the second switch are turned on, and the first transistor and the second transistor are complementarily driven according to transmission data,
When receiving, turning off the first switch and the second switch and turning on the first transistor and the second transistor;
A control method characterized by the above.
(Appendix 14)
A first transmission circuit and a second transmission circuit whose output nodes are connected to the first external terminal via a first termination resistor;
A third transmission circuit and a fourth transmission circuit, the output node of which is connected to the second external terminal via the second termination resistor;
Including
The first transmission circuit and the third transmission circuit are respectively
A first drive circuit that operates based on the first voltage and the second voltage and generates a first drive signal and a second drive signal;
A first switch connected between the first power supply line to which the first voltage is applied and the first line, and turned on and off based on a first switch control signal;
A second switch connected between a second power supply line to which the second voltage is applied and a second line and turned on and off based on the first switch control signal;
A first capacitor to which the second power supply wiring and the first wiring are connected;
A first transistor connected between the first wiring and the output node, the first drive signal being applied to a control terminal;
A second transistor connected between the second wiring and the output node and having the second drive signal applied to a control terminal;
Have
The second transmission circuit and the fourth transmission circuit are respectively
A second drive circuit that operates based on the first voltage and the second voltage and generates a third drive signal and a fourth drive signal;
A third switch connected between the first power supply wiring to which the first voltage is applied and the third wiring and turned on / off based on a second switch control signal;
A fourth switch connected between a second power supply line to which the second voltage is applied and a fourth line and turned on and off based on the second switch control signal;
A second capacitor connected between the second power supply wiring and the third wiring;
A third transistor connected between the third wiring and the output node, the third drive signal being applied to a control terminal;
A fourth transistor connected between the fourth wiring and the output node and having the fourth drive signal applied to a control terminal;
A method for controlling a transceiver circuit comprising:
During transmission, the first transistor and the second transistor are complementarily driven according to transmission data, and the third transistor and the fourth transistor are complementarily driven according to the transmission data,
Driving the first transistor and the second transistor based on a first selection signal and driving the third transistor and the fourth transistor based on a second selection signal during reception;
A control method characterized by the above.

25, 26 Transmitter circuit 25a, 26a Drive circuit N2p, N2n Output node E1p, E1n External terminal R1p, R1n Termination resistor VDD High potential voltage VSS Low potential voltage D1p, D1n Drive signal D2p, D2n Drive signal PL1 wiring PL2 wiring SW1p, SW1n Switch SW2p, SW2n Switch C1p, C1n Capacitor C2p, C2n Capacitor T1p, T1n Transistor T2p, T2n Transistor

Claims (10)

A first transmission circuit having an output node connected to a first external terminal via a first termination resistor;
A second transmission circuit having an output node connected to a second external terminal via a second termination resistor;
Including
The first transmission circuit and the second transmission circuit are respectively
A drive circuit that operates based on the first voltage and the second voltage and generates a first drive signal and a second drive signal;
A first switch connected between the first power supply wiring to which the first voltage is applied and the first wiring;
A second switch connected between a second power supply line to which the second voltage is applied and a second line;
A first capacitor connected between the second power supply wiring and the first wiring;
A first transistor connected between the first wiring and the output node, the first drive signal being applied to a control terminal;
A second transistor connected between the second wiring and the output node and having the second drive signal applied to a control terminal;
A transmission / reception circuit characterized by comprising: The drive circuit complementarily drives the first transistor and the second transistor according to the transmission data during transmission based on transmission data, a transmission control signal, and a termination control signal, and the first transistor during reception Generating the first drive signal and the second drive signal that turn on the second transistor;
The transmission / reception circuit according to claim 1. The drive circuit generates the first drive signal and the second drive signal to turn off the first transistor and the second transistor when not communicating;
The transmission / reception circuit according to claim 2. Each of the first transmission circuit and the second transmission circuit includes a second capacitor connected between the first power supply wiring and the second wiring;
The transmission / reception circuit according to any one of claims 1 to 3. The first switch and the second switch are turned on and off based on a switch control signal;
The transmission / reception circuit according to any one of claims 1 to 4. The first switch and the second switch are turned on and off based on a transmission control signal;
The transmission / reception circuit according to any one of claims 1 to 4. A first transmission circuit and a second transmission circuit whose output nodes are connected to the first external terminal via a first termination resistor;
A third transmission circuit and a fourth transmission circuit, the output node of which is connected to the second external terminal via the second termination resistor;
Including
The first transmission circuit and the third transmission circuit are respectively
A first drive circuit that operates based on the first voltage and the second voltage and generates a first drive signal and a second drive signal;
A first switch connected between the first power supply line to which the first voltage is applied and the first line, and turned on and off based on a first switch control signal;
A second switch connected between a second power supply line to which the second voltage is applied and a second line and turned on and off based on the first switch control signal;
A first capacitor connected between the second power supply wiring and the first wiring;
A first transistor connected between the first wiring and the output node, the first drive signal being applied to a control terminal;
A second transistor connected between the second wiring and the output node and having the second drive signal applied to a control terminal;
Have
The second transmission circuit and the fourth transmission circuit are respectively
A second drive circuit that operates based on the first voltage and the second voltage and generates a third drive signal and a fourth drive signal;
A third switch connected between the first power supply wiring to which the first voltage is applied and the third wiring and turned on / off based on a second switch control signal;
A fourth switch connected between a second power supply line to which the second voltage is applied and a fourth line and turned on and off based on the second switch control signal;
A second capacitor connected between the second power supply wiring and the third wiring;
A third transistor connected between the third wiring and the output node, the third drive signal being applied to a control terminal;
A fourth transistor connected between the fourth wiring and the output node and having the fourth drive signal applied to a control terminal;
A transmission / reception circuit characterized by comprising: The first driving circuit complementarily drives the first transistor and the second transistor according to the transmission data at the time of transmission based on the transmission data, transmission control signal, and termination control signal, and the first at the time of reception. Generating the first drive signal and the second drive signal for driving the first transistor and the second transistor based on a selection signal;
The second drive circuit complementarily drives the third transistor and the fourth transistor according to the transmission data at the time of transmission based on the transmission data, the transmission control signal, and the termination control signal, and the second at the time of reception. Generating the third drive signal and the fourth drive signal for driving the third transistor and the fourth transistor based on a selection signal;
The transmission / reception circuit according to claim 7. Each of the first transmission circuit and the third transmission circuit has a third capacitor connected between the first power supply wiring and the second wiring;
Each of the second transmission circuit and the fourth transmission circuit includes a fourth capacitor connected between the first power supply wiring and the fourth wiring;
The transmission / reception circuit according to claim 7 or 8. A first transmission circuit having an output node connected to a first external terminal via a first termination resistor;
A second transmission circuit having an output node connected to a second external terminal via a second termination resistor;
Including
The first transmission circuit and the second transmission circuit are respectively
A first switch connected between the first power supply wiring to which the first voltage is applied and the first wiring;
A second switch connected between the second power supply wiring to which the second voltage is applied and the second wiring;
A first capacitor connected between the second power supply wiring and the first wiring;
A first transistor connected between the first wiring and the output node;
A second transistor connected between the second wiring and the output node;
A control method for controlling a control circuit comprising:
At the time of transmission, the first switch and the second switch are turned on, and the first transistor and the second transistor are complementarily driven according to transmission data,
When receiving, turning off the first switch and the second switch and turning on the first transistor and the second transistor;
A control method characterized by the above.