JP2000059159A - Agc circuit, gain control method therefor and portable terminal equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an AGC(automatic gain control) circuit capable of eliminating the factor of lowering a response speed and performing a high-speed operation by simple constitution. SOLUTION: At the point of time at which the gain of an AGC amplifier 1 becomes maximum, the output of an integration means 9 is apparently turned to a clipped state. By the action of an output changeover means 14, signals inputted to the integration means 9 are switched from the output of a multiplication means 6 to '0'. Thus, inside the integration means 9, an integrated value at the point of time at which the gain of the AGC amplifier 1 becomes maximum is held. When the input analog signal level of the AGC amplifier 1 becomes high, the output of the multiplication means 6 is inputted to the integration means 9 and the integration means 9 starts integration from the integrated value corresponding to the actual input analog signal level of the AGC amplifier 1. Thus, timewise waste in the response of an AGC loop is eliminated and the high-speed operation is made possible.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic gain control (AGC) circuit and a gain control method suitable for use in, for example, a portable terminal device for digital mobile communication.
The present invention relates to an AGC circuit which enables high-speed operation by eliminating a factor for reducing a response speed, and a gain control method thereof.

[0002]

2. Description of the Related Art In digital mobile communication, when fading or the like occurs in a transmission path, the level of a received signal is reduced.
A GC circuit is required.

FIG. 3 shows a block diagram of a conventional AGC circuit, which will be described. This AGC circuit is an AGC circuit to which an input analog signal and an output of the D / A converter 12 are input.
An amplifier 1, a demodulator 2 to which an output of the AGC amplifier 1 is input, an A / D converter 3 to which an output of the demodulator 2 is input,
An absolute value detection circuit 4 to which an output of the A / D converter is input;
A subtractor 5 to which the output of the absolute value detection circuit 4 and the reference value are input, and a multiplier 6 to which the output of the subtractor 5 and the coefficient ε are input
And an integrator 9 to which the output of the multiplier 6 is input, and an integrator 9
And an adder 10 to which the output of and 2i / 2 are input,
And the D / A converter 12 to which the output of the selector 11 is inputted.

The AGC amplifier 1 has a dynamic range of several tens of dB, and controls the gain in accordance with the gain control voltage Vc output from the D / A converter 12 to keep the amplitude of the input analog signal constant. To Demodulator 2
Demodulates a signal output from the AGC amplifier 1 to extract and output an in-phase component and a quadrature component.
The A / D converter 3 converts an in-phase component and a quadrature component, which are analog signals output from the demodulator 2, into a digital signal and outputs the digital signal.

The absolute value detection circuit 4 detects the envelope by detecting the absolute value of the digital output of the A / D converter 3. The subtracter 5 subtracts this envelope signal level from a reference value which is a predetermined level, and outputs an error a. The multiplier 6 has a coefficient ε (0, 0) that determines the band of the feedback loop of the AGC circuit, that is, the loop band.
<Ε <1) and the error a are multiplied and output. Where ε
Is increased, the error a is output from the multiplier 6 almost as it is, so that a quick feedback response is possible.
However, the operation becomes unstable. Conversely, when ε is reduced, the response becomes slow, but the operation becomes stable.

The integrator 9 is composed of an adder 8 and a delay unit 7 for delaying the output of the adder 8 and inputting it to the adder 8, and integrates the output of the multiplier 6. Here, the error a
Is smaller than the original error a multiplied by ε, “a × ε”
Are added little by little so that the error a of the output of the subtractor 5 becomes zero. Here, when the assumed input signal level to the AGC amplifier 1 is the minimum, the gain control voltage Vc is the maximum (A
Assuming that the gain of the GC amplifier 1 is maximum, the output bits of the integrator 9 at this time are all "1" except for the sign bit (MSB: most significant bit). Depending on the response speed of the AGC loop, when all the output bits of the integrator 9 become "1" except for the sign bit, the error a is not "0". Therefore, the output of the multiplier 6 does not become “0”, and if the bit numbers of the adder 8 and the integrator 9 are the same, the adder 8 may overflow.

In order to prevent the overflow of the adder 8, if the number of bits of the multiplier 6 is i, the number of bits of the adder 8 and the delay 7 is one more than the number of bits of the multiplier 6. And set to i + 1 bits. Therefore, the number of bits of the integrator 9 is i + 1 bits, and the output of the integrator 9 operates within a range of ± 2 i -1 around 0.

[0008] The adder 10 adds 2i / 2 (=
2i-1), the operating range becomes -2i-1 to
+ 2i-1 is converted to 0-2i. The number of output bits of the selector 11 is i bits. When the most significant bit of the output of the adder 10 is “0”, the remaining bits excluding the most significant bit of the output of the adder 10 are output as they are, When the most significant bit of the output of 10 becomes "1", 2i-1 is output by setting all output bits to "1".
The output of the integrator 9 is clipped.

The D / A converter 10 outputs the output of the selector 11 to A
Gain control voltage Vc for controlling the gain of GC amplifier 1
Convert to The gain control voltage Vc controls the gain of the AGC amplifier 1 according to the output level of the A / D converter 10, and keeps the input level to the demodulator 2 constant.

[0010]

SUMMARY OF THE INVENTION The aforementioned conventional A
In the GC circuit, when the most significant bit of the output of the adder 10 becomes "1", all the output bits of the selector 11 become "1". However, depending on the response speed of the AGC loop,
Until the error a becomes 0, the integrator 9 continues to integrate the output of the multiplier 6, and the integrated value is different from the output signal level of the A / D converter 3 and the input signal level of the AGC amplifier 1 at that time. It becomes an unrelated value (a value larger than the output of the selector 11).

From the state where all the output bits of the selector 11 are "1" (when the gain control voltage Vc is the maximum),
When the input signal level of the G amplifier 1 increases, the error a becomes a negative value, and the AGC circuit operates in a direction to decrease the gain of the AGC amplifier 1. That is, it operates in the direction of decreasing the integrated value of the integrator 9. However, since the integrated value of the integrator 9 at this time is a value irrelevant to the input signal level of the AGC amplifier 1 (a value larger than the output of the selector 11), the integrated value is larger than the value of the output of the selector 11. Since the AGC circuit operates in the direction of decreasing the integrated value, time is wasted, which causes a reduction in the response speed of the AGC loop.

In digital mobile communication, since there is a fluctuation of 50 to 60 dB in a large dynamic range, the fluctuation must always be followed. As described above, when the AGC loop band is widened by increasing ε, the tracking speed is fast. However, when an extreme fluctuation enters, the overshoot, that is, the tracking is lost, and the error a cannot be brought close to 0. Or When ε is reduced, stable operation is obtained, but it cannot follow a sudden change. For this reason, within the range where the AGC loop operates stably, it is necessary to increase ε as much as possible and to increase the response speed of the AGC loop. However, there is a problem that the response speed of the AGC loop cannot be increased because of the factor of reducing the response speed of the AGC loop.

[0013] Accordingly, the present invention provides an AGC circuit and a gain control method thereof that enable high-speed operation by eliminating a factor that slows down the response speed of the AGC loop due to factors other than the coefficient ε that determines the loop band. With the goal. Another object of the present invention is to realize the AGC circuit and its gain control method with a simple configuration without increasing the hardware scale.

[0014]

According to the present invention, in order to solve the above-mentioned problems, an AGC amplifier, a demodulator for demodulating an output signal of the AGC amplifier, and an A / D converter for digitizing an output of the demodulator are provided. An envelope detector for detecting an envelope of an output of the A / D converter; an error calculator for calculating an error between a detection output of the envelope detector and a reference value; An AGC circuit comprising: a multiplying means for multiplying a coefficient that determines the following equation; an integrating means for integrating the output of the multiplying means; and a control voltage generating means for generating a gain control voltage of the AGC amplifier from the output of the integrating means. The output level determining means for determining whether the output signal level has reached a predetermined level, the positive / negative determining means for determining whether the output signal of the multiplying means is positive or negative, and the output signal level of the integrating means are predetermined. Clipping means for clipping the output of the integrating means when the output level determining means determines that the output level has reached the predetermined level; and output level determining means for determining that the output signal level of the integrating means has reached a predetermined level. Holding means for holding the integrated value of the integration means when the determination is made and the positive / negative determination means determines that the output signal of the multiplication means is positive. With this configuration, the output of the integrator is clipped when the gain of the AGC amplifier is maximized, and when the output of the integrator is clipped, the output of the multiplier is positive in the integrator. In this case, control can be performed so that integration is not performed, and integration is performed when negative.

In this AGC circuit, the holding means can be configured to hold the integrated value of the integrating means by switching the output of the multiplying means to "0". Further, in this AGC circuit, the positive / negative determining means can be constituted by an inverter for inverting the most significant bit of the output of the multiplying means.

Further, according to the present invention, in order to solve the above-mentioned problems, an AGC amplifier, a demodulator for demodulating an output signal of the AGC amplifier, and an A / A for digitizing an output of the demodulator are provided.
A D converter, an envelope detector for detecting an envelope of an output of the A / D converter, an error detector for calculating an error between a detection output of the envelope detector and a reference value, Multiplying means for multiplying by a coefficient for determining a response speed; integrating means for integrating the output of the multiplying means;
In an AGC circuit having a control voltage generating means for generating a gain control voltage for an amplifier, it is determined whether or not the output signal level of the integrating means has reached a predetermined level, and whether the output signal of the multiplying means is positive or negative. Is determined, the output of the integrating means is clipped when it is determined that the output signal level of the integrating means has reached a predetermined level, and that the output signal level of the integrating means has reached a predetermined level. When the determination is made and the output signal of the multiplying means is determined to be positive, the integrated value of the integrating means is held. With this configuration, the output of the integrator is clipped when the gain of the AGC amplifier is maximized, and when the output of the integrator is clipped, the output of the multiplier is positive in the integrator. In this case, control can be performed so that integration is not performed, and integration is performed when negative.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is directed to an AGC amplifier whose gain is controlled so that an output signal level with respect to an input analog signal is constant,
A demodulator for demodulating an output signal of the C amplifier, an A / D converter for digitizing an output of the demodulator, an envelope detecting means for detecting an envelope of an output of the A / D converter, and the envelope Error detecting means for calculating an error between the detection output of the line detecting means and a reference value, multiplying means for multiplying the error by a coefficient that determines a response speed, integrating means for integrating the output of the multiplying means, and the integrating means Control voltage generating means for generating a gain control voltage of the AGC amplifier from the output of the AGC amplifier.
In the C circuit, output level determining means for determining whether or not the output signal level of the integrating means has reached a predetermined level; positive / negative determining means for determining whether the output signal of the multiplying means is positive or negative; Clipping means for clipping the output of the integrating means when the output level determining means determines that the output signal level of the means has reached a predetermined level; and the output signal level of the integrating means is predetermined. Holding means for holding the integrated value of the integrating means when the output level determining means determines that the output signal has reached the level and the positive / negative determining means determines that the output signal of the multiplying means is positive. When the gain of the AGC amplifier becomes maximum, the output of the integrating means is clipped, and when the output of the integrating means is clipped, In the accumulating means has the effect that the output of the multiplication means without accumulation in the case of positive, performing the integration in the case of negative.

According to a second aspect of the present invention, in the first aspect of the present invention, the holding means switches the signal input to the integrating means from the output of the multiplying means to "0", thereby providing the integrating means. , And the output of the multiplying means is not input to the integrating means.
By inputting "0", there is an effect that the integrated value of the integrating means is held.

According to a third aspect of the present invention, in the first aspect of the present invention, the positive / negative determining means is constituted by an inverter for inverting the sign bit of the output of the multiplying means. Has the effect of determining whether the output of the multiplying means is positive or negative.

The invention described in claim 4 of the present invention is characterized in that
A C amplifier, a demodulator for demodulating an output signal of the AGC amplifier, an A / D converter for digitizing an output of the demodulator,
Envelope detection means for detecting the envelope of the output of the A / D converter; error calculation means for calculating an error between the detection output of the envelope detection means and a reference value; and a coefficient for determining a response speed for the calculated error AGC comprising: multiplying means for multiplying the multiplying factor; integrating means for integrating the output of the multiplying means; and control voltage generating means for generating a gain control voltage for the AGC amplifier from the output of the integrating means.
In the circuit, it is determined whether or not the output signal level of the integrating means has reached a predetermined level, and the sign of the output signal of the multiplying means is determined, so that the output signal level of the integrating means has reached a predetermined level. The output of the integrating means is clipped when it is determined that the output has reached the predetermined level, and when the output signal of the multiplying means is determined to be positive, the output of the integrating means is determined. The output of the integration means is clipped when the gain of the AGC amplifier is maximized, and the integrated value is held.
When the output of the integrating means is clipped, the integration is not performed when the output of the multiplying means is positive in the integrating means.
In the case of a negative value, it has the effect of performing integration.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
FIG. 3 is a block diagram showing an AGC circuit according to the embodiment. In this figure, parts corresponding to those of the conventional example shown in FIG. 3 are denoted by the same reference numerals. In FIG. 1, A
The configurations and operations of the GC amplifier 1, the demodulator 2, and the A / D converter 3 are the same as those of the conventional example shown in FIG.

The envelope detector 4 detects the envelope of the digital output of the A / D converter 3. The subtraction means 5 subtracts the output of the envelope detection means 4 from a reference value which is a predetermined level, and outputs an error a. Multiplication means 6
Multiplies the error a by a coefficient ε that determines the band of the feedback loop of the AGC circuit, that is, the loop band.

The output of the multiplying means 6 is sent to the output switching means 14 and the positive / negative determining means 13. The positive / negative determining means 13 determines whether the output of the multiplying means 6 is a positive value or a negative value, and supplies the output to the output switching means 14. Output switching means 14
Is based on the output of the positive / negative determining means 13 and the determination output of the output level determining means 17 described later,
Select the output and output.

The delay means 16 is provided to match the timing of integration by the integration means 9 described later with the timing of output by the output switching means 14. The accumulating means 9 includes the adding means 8
And a delay means 7 for delaying the output of the addition means 8 and inputting it to the addition means 8. For each delay time of the delay means 7, the output of the delay means 16 is “a × ε” or “ Integrate "0".

Here, assuming that the output of the delay means 7 is b and the output of the output switching means 14 is "a.times..epsilon.", The output of the integrating means 9 is b + (a.times..epsilon.). With this value, the most significant bit (MSB) of the output of the adding means 10 described later becomes “1”, and the output of the output switching means 14 changes from “a × ε” to “0”.
In addition, within the delay time of the delay means 7, ie,
Is switched by the time until the next integration is performed, the output of the integration means 9 changes from “b + (a × ε)” to “b”. Will be different from the integrated value at. To avoid this, a delay means 16 similar to the delay means 7 is provided, and the timing of integration by the integration means 9 and the timing of output by the output switching means 14 are matched.

The delay means 16 delays the output of the output switching means 14 for a predetermined time and provides the output to the integrating means 9. The integrating means 9 includes an adding means 8 and a delaying means 7 for delaying the output of the adding means 8 and inputting the output to the adding means 8.
“A × ε” or “0” which is the output of the delay means 16 is integrated. Here, assuming that the number of bits of the multiplication means 6 is i bits, the number of bits of each of the addition means 8 and the delay means 7 is i
As the +1 bit, overflow of the adding means 8 is prevented. Therefore, the number of bits of the integrating means 9 is i + 1 bits, and the output 0 of the integrating means 9 operates in a range of ± 2 ^{i-1 at} the center. The adding means 10 outputs 2 ⁱ /
By adding 2, the operating range becomes ^-2i-1 to + ^2i-1.
From converted to 0~2 ^i.

The output of the adding means 10 is sent to an output switching means 11 and an output level judging means 17. The output level determining means 17 determines whether the most significant bit of the output of the adding means 10 is "0" or "1", and supplies the output to the output switching means 11 and the output switching means 14. The number of output bits of the output switching means 11 is i + 1 bits. When the most significant bit of the output of the adding means 10 is determined to be "0", the adder 10
The remaining bits excluding the most significant bit of the output are output as they are, and when it is determined to be “1”, all the output bits are set to “1”, thereby outputting 2i−1 and apparently
The output of the integrating means 9 is clipped. D / A conversion means 12
Converts the output of the output switching means 11 into a gain control voltage Vc for controlling the gain of the AGC amplifier 1.

Next, the operation of the AGC circuit shown in FIG. 1 will be described. As described above, the output of the integrating means 9 operates within a range of ± 2i-1 centered on 0. The adding means 10 is the integrating means 9
By adding 2i / 2 to the output of
Conversion from 2i-1 to + 2i-1 to 0 to 2i. Addition means 10
When the output level exceeds 2i-1, that is, the adding means
When the most significant bit of the output of 10 becomes "1", the output of the output switching means 11 becomes 2i-1 according to the judgment output of the output level judging means 17. At this time, since the gain control voltage Vc supplied from the D / A conversion means 12 to the AGC amplifier 1 becomes maximum, the gain of the AGC amplifier 1 becomes maximum.

The judgment output of the output level judgment means 17 is also supplied to the output switching means 14. The output switching means 14 is also supplied with the judgment output of the sign judgment means 13. The positive / negative determining means 13 determines whether the value to be integrated next by the integrating means 9 is positive or negative based on the most significant bit which is the sign bit of the output of the multiplying means 6. That is,
When the most significant bit which is the sign bit of the output of the multiplying means 6 is "0", it is determined to be positive, and when this most significant bit is "1", it is determined to be negative. Therefore, AG
Even if the gain of the C amplifier 1 is maximized, if the digital output level of the A / D converter 3 is not increased due to the response speed of the AGC loop, the output level of the envelope detection means 4 is equal to or lower than the reference value. And the error a becomes a positive value.

The output switching means 14 receives from the output level determining means a determination output indicating that the output level of the adding means 10 exceeds 2i-1 and the most significant bit is "1", When the determination output indicating that the value to be integrated is positive is received from the positive / negative determination means 13, the output is switched from “a × ε”, which is the output of the multiplication means 6, to “0”.

The output of the output switching means 14 is input to the integrating means 9 via the delay means 16. At this time, since "0" is input to the integrating means 9, the actual integrated value at the time when the gain of the AGC amplifier 1 becomes maximum is held in the integrating means 9. (However, as described above, the output of the adding means 10 has 2i / 2 added to the integrated value and is apparently clipped).

Next, from the time when the gain control voltage Vc is the maximum,
When the level of the input analog signal of the AGC amplifier 1 increases, the AGC circuit operates in the direction of decreasing the gain of the AGC amplifier 1, that is, in the direction of decreasing the integrated value of the integrating means 9. At this time, the input level of the subtraction means 5, that is, the output of the digital output of the A / D converter 3 detected by the envelope detection means 4 becomes a value larger than the reference value. a becomes negative. Accordingly, the output of the multiplying means 6 also becomes negative, and the judgment output of the sign judgment means 13 changes from a positive judgment to a negative judgment. Output switching means
When the determination output is received, the switch 14 switches the output from “0” to the output of the multiplication means 6.

Therefore, the output of the multiplying means 6 is input to the integrating means 9. As described above, at this point, the integrating means 9
Is the integrated value at the time when the gain of the AGC amplifier 1 is maximized. In the integrating means 9, since the input signal is a negative value, the integrated value decreases. As the integrated value keeps decreasing, the output of the adding means 10 keeps decreasing. When the output level of the adding means 10 becomes 2i-1 or less and the most significant bit becomes "0" by the output level determining means 17, the output of the output switching means 11 is determined by the determined output.
Is switched from 2i-1 to the value of the output of the adding means 10 excluding the most significant bit.

As described above, according to the present embodiment, AG
When the gain of the C amplifier 1 reaches the maximum, the integrating means 9
Is output in a clipped state, but the integrated value at that time is held in the integrating means 9. When the input analog signal level of the AGC amplifier 1 increases, the integration means 9 starts integration from the integrated value corresponding to the actual input analog signal level of the AGC amplifier 1. There is no time waste in the response of the AGC loop, and there is no factor that slows the response speed of the AGC loop other than the coefficient ε that determines the response speed of the AGC loop.

(Second Embodiment) FIG. 2 shows a second embodiment of the present invention.
FIG. 3 is a block diagram showing an AGC circuit according to the embodiment. In this figure, the same reference numerals are given to parts corresponding to the parts of the first embodiment shown in FIG. 2, the configuration and operation of the AGC amplifier 1, the demodulator 2, and the A / D converter 3 are the same as those of the conventional example shown in FIG.

In FIG. 2, the absolute value detection circuit 4 has an A /
By detecting the absolute value of the digital output of the D converter 3, the envelope is detected. The subtracter 5 subtracts the output of the absolute value detection circuit 4 from a reference value which is a predetermined level, and outputs an error a. The multiplier 6 multiplies the error a by a coefficient ε that determines the band of the feedback loop of the AGC circuit.

The inverter 13 inverts the most significant bit of the output of the multiplier 6. The AND gate 14 performs a logical OR operation on the output of the inverter 13 and the most significant bit of the output of the adder 10 described later. The selector 15 selects and outputs “0” or the output of the multiplier 6 based on the output of the AND gate 14.

The delay unit 16 is provided to match the integration timing of the integrator 9 described later with the output timing of the selector 14. The integrator 9 includes an adder 8 and a delay unit 7 that delays the output of the adder 8 and inputs the output to the adder 8. For each delay time of the delay unit 7, the output of the delay unit 16 is used. A certain “a × ε” or “0” is integrated.

Here, assuming that the output of the delay unit 7 is b and the output of the selector 14 is “a × ε”, the output of the integrator 9 is
b + (a × ε). An adder described later is used for this value.
The most significant bit (MSB) of the output of 10 becomes “1” and the output of the selector 14 changes from “a × ε” to “0” within the delay time of the delay unit 7, that is, the integrator 9 , The output of the integrator 9 changes from “b + (a × ε)” to “b”, and the integrated value when the output of the selector 14 is switched is Will be different. In order to avoid this, a delay device 16 similar to the delay device 7 is provided, and the integration timing of the integrator 9 and the selector
Adjust the output timing of 14.

The delay unit 16 delays the output of the selector 15 for a predetermined time and supplies the output to the integrator 9. The integrator 9
It comprises an adder 8 and a delay unit 7 for delaying the output of the adder 8 and inputting it to the adder 8. The adder 8 integrates the output of the delay unit 16, that is, “a × ε” or “0”. Go. here,
Assuming that the number of bits of the multiplier 6 is i, the number of bits of each of the adder 8 and the delay 7 is i + 1, thereby preventing overflow of the adder 8. Therefore, the integrator 9
Is i + 1 bits, and the output of the integrator 9 is 0
And operates within a range of ± 2 ^i-1 . The adder 10 converts the operating range from −2 ⁱ⁻¹ to +2 ⁱ⁻¹ to 0 to 2 ⁱ by adding 2 ⁱ / 2 to the output of the integrator 9.

The output of the adder 10 is sent to the selector 11.
The most significant bit of the output of the adder 10 is sent to the selector 11 and the AND gate 14. The number of output bits of the selector 11 is i bits. When the most significant bit of the output of the adder 10 is “0”, the remaining bits excluding the most significant bit of the output of the adder 10 are output as they are, and “1” is output. In the case of "", all output bits are set to "1" to output 2i-1 and apparently clip the output of the integrator 9. D / A
The converter 12 converts the output of the selector 11 into a gain control voltage Vc for controlling the gain of the AGC amplifier 1.

Next, the operation of the AGC circuit shown in FIG. 2 will be described. As described above, the output of the integrator 9 operates in a range of ± 2i-1 with 0 as the center. The adder 10 adds 2i / 2 to the output of the integrator 9 to increase the operating range to -2i-1.
From + 2i-1 to 0-2i. When the output level of the adder 10 exceeds 2i-1, that is, when the most significant bit of the output of the adder 10 becomes "1", the output of the selector 11 becomes 2i-1. At this time, the AGC
Since the gain control voltage Vc supplied to the amplifier 1 becomes the maximum, the gain of the AGC amplifier 1 becomes the maximum.

The most significant bit "1" of the adder 10 is also supplied to the AND gate 14. The output of the inverter 13 is also supplied to the AND gate 14. The inverter 13 determines whether the value integrated by the integrator 9 is positive or negative, based on the most significant bit, which is the sign bit of the multiplier 6. That is, when the output of the multiplier 6 is positive (the most significant bit is “0”), it is inverted to output “1”,
When the output of the multiplier 6 is negative (the most significant bit is "1"), the output is inverted and "0" is output.

Therefore, even if the gain of the AGC amplifier 1 is maximized, if the digital output level of the A / D converter 3 is not increased due to the response speed of the AGC loop, the output of the absolute value detection circuit 4 The level falls below the reference value, and the error a becomes a positive value. In this case, the output of the inverter 13 becomes "1". As a result, the output level of the AND gate 14 becomes "1", so that the output of the selector 15 switches from the output of the multiplier 6 to "0".

The output of the selector 15 is input to the integrator 9 via the delay unit 16. At this time, since “0” is input to the integrator 9, the AGC amplifier 1
The actual integrated value at the time when the gain becomes maximum is held (however, as described above, the output of the adder 10 is added with 2i / 2 to the integrated value and apparently clipped. There).

Next, from the time when the gain control voltage Vc is the maximum,
When the level of the input analog signal of the AGC amplifier 1 increases, the AGC circuit operates in the direction of decreasing the gain of the AGC amplifier 1, that is, in the direction of decreasing the integrated value of the integrator 9. At this time, the input level of the subtractor 5, that is, A /
Since the digital output of the D converter 3 detected by the absolute value detection circuit 4 is larger than the reference value, the error a output from the subtractor 6 becomes negative. Therefore, since the output of the multiplier 6 also becomes negative, the judgment output of the inverter 13 becomes “1”.
From "1" to "0". Since the output level of the AND gate 14 changes from "1" to "0", the output of the selector 15 is switched from "0" to the output of the multiplier 6. Be replaced.

Therefore, the output of the multiplier 6 is input to the integrator 9. As described above, the integrated value of the integrator 9 at this time is the integrated value at the time when the gain of the AGC amplifier 1 is maximized. In the integrator 9, since the input signal has a negative value, the integrated value decreases. If the integrated value keeps falling,
The output of the adder 10 also keeps decreasing. When the output level becomes 2i-1 or less and the most significant bit becomes "0", the output of the selector 11 changes from 2i-1 to the value of the output of the adder 10 excluding the most significant bit. It switches to.

As described above, according to the present embodiment, AG
When the gain of the C amplifier 1 is maximized, the output of the integrator 9 is apparently clipped, but the integrated value at that point is held in the integrator 9. When the input analog signal level of the AGC amplifier 1 increases, the integrator 9 starts integration from the integrated value corresponding to the actual input analog signal level of the AGC amplifier 1, so that the AGC loop is compared with the conventional example. There is no time waste in the response of the AGC loop, and there is no factor that slows the response speed of the AGC loop other than the coefficient ε that determines the response speed of the AGC loop. Further, an AGC circuit can be realized with a simple configuration in which an inverter 13, an AND gate 14, a selector 15, and a delay unit 16 are added to the circuit of the conventional example shown in FIG.

[0050]

As described above in detail, according to the AGC circuit and the gain control method of the present invention, when it is determined that the output signal level of the integrating means has reached a predetermined level. Clipping the output of the integrating means, determining that the output signal level of the integrating means has reached a predetermined level, and determining that the output signal of the multiplying means is positive, Since the integrated value is held, when the input analog signal level of the AGC amplifier increases, the integrating means starts the integration from the integrated value corresponding to the actual input analog signal level of the AGC amplifier. Therefore, the response of the AGC loop is not wasted in time, and high-speed operation is possible.

The AGC circuit according to the present invention can be realized without increasing the scale of hardware by simply adding a simple logic circuit to the conventional AGC circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram of an AGC circuit according to a first embodiment of the present invention;

FIG. 2 is a block diagram of an AGC circuit according to a second embodiment of the present invention;

FIG. 3 is a block diagram of a conventional AGC circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 AGC amplifier 2 Demodulator 3 A / D converter 4 Envelope detection means, absolute value detection circuit 5 Subtraction means, subtracter 6 Multiplication means, multiplier 7 Delay means, delay device 8 Addition means, adder 9 Integration means, Integrator 10 Adder, Adder 11 Output switch, Selector 12 D / A converter, D / A converter 13 Positive / negative determiner, Inverter 14 Output switch, AND gate 15 Selector 16 Delayer, Delayer

Claims (5)

[Claims] An AGC amplifier whose gain is controlled so that an output signal level with respect to an input analog signal is constant, a demodulator for demodulating an output signal of the AGC amplifier,
An A / D converter for digitizing an output of the demodulator;
Envelope detection means for detecting an envelope of the output of the A / D converter; error calculation means for calculating an error between a detection output of the envelope detection means and a reference value; and a coefficient for determining a response speed for the error Multiplying means, a multiplying means for multiplying the output of the multiplying means, and the AG from the output of the multiplying means.
An AGC circuit comprising control voltage generating means for generating a gain control voltage for a C amplifier, wherein: an output level determining means for determining whether an output signal level of the integrating means has reached a predetermined level;
Positive / negative determining means for determining whether the output signal of the multiplying means is positive or negative, and outputting the output of the integrating means when the output level determining means determines that the output signal level of the integrating means has reached a predetermined level. Clipping means for clipping, the output level determining means determines that the output signal level of the integrating means has reached a predetermined level,
And an holding means for holding the integrated value of the integrating means when the positive / negative determining means determines that the output signal of the multiplying means is positive. 2. The apparatus according to claim 1, wherein said holding means holds an integrated value of said integrating means by switching a signal input to said integrating means from an output of said multiplying means to "0". AGC circuit. 3. The AGC circuit according to claim 1, wherein said positive / negative judging means comprises an inverter for inverting a sign bit of an output of said multiplying means. 4. An AGC amplifier whose gain is controlled so that an output signal level with respect to an input analog signal is constant, and a demodulator for demodulating an output signal of the AGC amplifier.
An A / D converter for digitizing an output of the demodulator;
Envelope detection means for detecting an envelope of the output of the A / D converter; error calculation means for calculating an error between a detection output of the envelope detection means and a reference value; and a coefficient for determining a response speed for the error Multiplying means, a multiplying means for multiplying the output of the multiplying means, and the AG from the output of the multiplying means.
An AGC circuit comprising: a control voltage generating means for generating a gain control voltage for a C amplifier; determining whether an output signal level of the integrating means has reached a predetermined level, The sign of the signal is determined, and when it is determined that the signal has reached the predetermined level, the output of the integrating means is clipped, it is determined that the signal has reached the predetermined level, and A gain control method for an AGC circuit, wherein the integrated value of the integrating means is held when it is determined that the output signal is positive. 5. A portable terminal device using the AGC circuit according to claim 1.