JP2000058876A - Schottky barrier semiconductor device and fabrication thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a Schottky barrier semiconductor device which can be driven at voltage while saving power and in which forward voltage is lowered while suppressing leak current in reverse direction, and a fabrication method thereof. SOLUTION: A lightly doped A lightly doped first conductivity type is grown epitaxially on a heavily doped first conductivity type (n+ type) semiconductor substrate 1. A second conductivity type (p+ type) semiconductor region 6 is provided on the surface of the semiconductor layer 2 at least across two regions and a metal layer 3 for forming a Schottky barrier is provided on the surface of the semiconductor layer 2 in the operating region. A heavily doped first conductivity type buried layer 7 is formed on the semiconductor substrate 1 side of the first conductivity type semiconductor layer 2, i.e., the operating region, where the semiconductor region 6 is nor formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a Schottky barrier semiconductor device in which a metal layer for forming a Schottky barrier is provided on a semiconductor layer serving as an operation layer on a semiconductor substrate, and a method of manufacturing the same. More specifically, the present invention relates to a Schottky barrier semiconductor device having a small leakage current and a low forward voltage, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Schottky barrier diodes (SB)
D) is widely used in high frequency rectifier circuits because of its high switching characteristics and small forward loss. A conventional SBD has, for example, a structure as shown in a sectional explanatory view of FIG. That is, in FIG. 5, reference numeral 1 denotes an n ^{+ type} semiconductor substrate made of, for example, silicon.
Reference numeral 2 denotes a semiconductor layer epitaxially grown on the semiconductor substrate 1 and serves as, for example, an n ⁻ -type operation layer. Reference numeral 3 denotes a metal layer formed of molybdenum (Mo) or the like, forming a Schottky barrier. This is a guard ring formed to diffuse the p ^{+ -type} dopant to the surface side of the semiconductor layer 2 in the vicinity and to improve the breakdown voltage at the periphery of the Schottky junction. Reference numeral 5 denotes a thermal oxidation method or C
This is an insulating film made of, for example, SiO ₂ formed by the VD method or the like.

[0003] characteristics of the leakage current I _R of the forward voltage V _F and reverse SBD obtained by the Schottky junction between the metal layer 3 and the semiconductor layer 2, the intrinsic barrier value of the metal material and the semiconductor layer , As shown in FIG. As a metal material for obtaining this type of Schottky junction, Ti or M is preferable in terms of ease of handling, economy and reliability.
Although o and the like are used practically, the forward voltage and the reverse leakage current are determined according to the barrier value of those materials. And, there is a reciprocal relationship between the forward voltage and the reverse leakage current, a material having a small leak current has a high forward voltage, and a material having a low forward voltage has a large reverse leak current, Both the leakage current and the forward voltage cannot be reduced.

On the other hand, Japanese Patent Publication No. 59-35183 discloses a structure as shown in FIG. 7 in order to increase the reverse breakdown voltage of a Schottky barrier semiconductor device by lowering the reverse leakage current. ing. That is,
In FIG. 7, reference numerals 1 to 5 denote the same parts as in FIG. 5, and reference numeral 6 denotes ap ^{+ type} semiconductor region provided in an island or strip shape on the surface of the n ^{− type} semiconductor layer 2 serving as an operation layer. In this structure, the breakdown voltage is improved by reducing the reverse leakage current by the depletion layer formed on the second side.

[0005]

As described above, the conventional Schottky barrier characteristics using a practical metal material for forming a Schottky barrier are characterized by the characteristics of the forward voltage and the leak current according to the material. And their reciprocal properties cannot be avoided. Further, when a semiconductor region having a conductivity type different from that of the semiconductor layer (for example, a p-type region with respect to the n-type semiconductor layer) is formed on the surface of the semiconductor layer serving as the above-mentioned operation layer in order to reduce the leakage current in the reverse direction, Since the shape region does not become an operation region, the area of the operation region of the semiconductor layer is reduced. When the area is reduced, the series resistance between the metal layer and the electrode provided on the back surface of the semiconductor substrate increases, and the forward voltage eventually increases. The Schottky barrier semiconductor device is characterized in that its forward voltage is low, but with the recent trend toward smaller and lighter electronic devices and lower power consumption with lower power consumption, without increasing the chip area, the forward voltage and There is a need for a high performance Schottky barrier semiconductor device in which both the reverse leakage currents are further reduced.

As disclosed in Japanese Patent Publication No. 59-35183, for example, one of the problems is to increase the reverse breakdown voltage in the related art. It is necessary to increase the distance between the lower end of the diffusion region and the lower end of the semiconductor layer 2. Therefore, there is a problem that the forward series resistance is further increased and the forward voltage is increased. On the other hand, in recent years, Schottky barrier semiconductor devices are often used together with ICs at a low voltage on the secondary side of a power supply, and the reverse breakdown voltage only needs to satisfy several tens of volts, for example, about 30 volts. In addition, with the power saving and low voltage driving of electronic devices, there is a demand for a Schottky barrier semiconductor device having a lower forward voltage and a smaller leak current.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and a Schottky barrier semiconductor device capable of driving at a low voltage with a low power consumption while reducing a leakage current in a reverse direction and having a low forward voltage. The purpose is to provide the manufacturing method.

[0008]

A Schottky barrier semiconductor device according to the present invention comprises a semiconductor substrate of a first conductivity type having a high impurity concentration and a semiconductor of a first conductivity type having a low impurity concentration epitaxially grown on the semiconductor substrate. A layer, a semiconductor region of the second conductivity type provided adjacent to at least two or more regions on the surface side of the semiconductor layer, and a shot provided on the surface of the semiconductor layer and the semiconductor region of the second conductivity type. A metal layer forming a key barrier;
A buried region of the first conductivity type having a high impurity concentration is formed on the semiconductor substrate side of the semiconductor layer of the first conductivity type, which is an operation region without forming the semiconductor region of the conductivity type.

With this structure, the semiconductor layer of the second conductivity type is formed in the semiconductor layer of the first conductivity type serving as the operation layer, so that the depletion layer prevents the leakage current in the reverse direction and causes leakage. The current can be suppressed, and the low-impurity-concentration semiconductor layer serving as an operation region has a high-impurity-concentration buried region provided on the lower surface side, so that the thickness of the low-impurity-concentration semiconductor layer is reduced. The series resistance is reduced, and the forward voltage can be reduced.

The method of manufacturing a Schottky barrier semiconductor device according to the present invention comprises the steps of: (a) selectively introducing a first conductivity type impurity into a surface of a high impurity concentration first conductivity type semiconductor substrate;
A semiconductor layer of a first conductivity type having a low impurity concentration is epitaxially grown on the surface of the semiconductor substrate, and the first introduced semiconductor layer is introduced.
Forming a buried region having a high impurity concentration due to the rise of the conductivity type impurity, and (c) covering a portion corresponding to a place where the first conductivity type impurity is introduced into the semiconductor substrate on the surface of the epitaxially grown semiconductor layer. By forming a mask and introducing impurities of the second conductivity type, two or more semiconductor regions of the second conductivity type adjacent to the surface side of the semiconductor layer at a position sandwiching the portion where the buried region is formed are formed. Forming (d)
A metal layer for forming a Schottky barrier is provided on surfaces of the semiconductor layer and the semiconductor region of the second conductivity type.

The distance between the adjacent second conductivity type semiconductor regions, the bottom surface of the second conductivity type semiconductor region, and the first
Forming the semiconductor region of the second conductivity type so that the ratio to the interval between the bottom surfaces of the semiconductor layers of the conductivity type is 1: 1 to 2 provides a depletion layer for preventing leakage current to the maximum, The semiconductor layer of the first conductivity type has a minimum thickness that can withstand a desired breakdown voltage, and can further reduce the series resistance while further preventing leakage current, thereby contributing to lowering the forward voltage.

[0012]

Next, a Schottky barrier semiconductor device of the present invention and a method of manufacturing the same will be described with reference to the drawings.

A Schottky barrier semiconductor device according to the present invention, as shown in FIG. 1A, is a semiconductor substrate of a first conductivity type having a high impurity concentration of, for example, an n ^{+ type.} A semiconductor layer 2 of a first conductivity type having a low impurity concentration of n ^{− type} is epitaxially grown on the semiconductor layer 1, and at least two or more regions are formed on the surface side of the semiconductor layer 2.
A semiconductor region 6 of the p ^{+ -type} second conductivity type is provided adjacently, and a metal layer 3 forming a Schottky barrier is provided on the surface of the operation region of the semiconductor layer 2. Then, the buried region 7 of the first conductivity type having a high impurity concentration is formed on the semiconductor substrate 1 side of the semiconductor layer 2 of the first conductivity type, which is an operation region without forming the semiconductor region 6 of the adjacent second conductivity type. Have been.

The semiconductor substrate 1 has, for example, an impurity concentration of 1
× 10¹⁹cm^-3Degree n⁺Made of mold silicon, thickness
Are formed, for example, in the order of 200 to 250 μm.
The semiconductor layer 2 provided on the semiconductor substrate 1 has a high impurity concentration.
The degree is, for example, 1 × 10^Fifteencm ^-3Degree n^-Mold of silicon
The semiconductor layer is formed to a thickness of, for example, about 4 to 6.5 μm.
TAXIAL has been growing.

An outer peripheral portion of a portion to be an operation region of the semiconductor layer 2
Guard ring 4 on the surface of⁺1.5-2μ shaped area
It is provided at a depth of about m. This guard ring 4
At the same time, a flat surface as shown in FIG.
As the front view shows, p ⁺Semiconductor region 6
(In the figure, nine are shown,
Actually, about several hundred pieces are formed). This p⁺Semiconductor of shape
The area 6 may be not a matrix but a strip.
By providing them in a matrix, the area of the operating region can be reduced.
Maximize depletion in the operating region while minimizing
It is preferable because it can be expanded to the limit. Of the semiconductor region 6
Has a size of, for example, about 2 μm square and a depth of
Is formed to the same depth as 1.5 to 2 μm as guard ring 4
Is done. In addition, the interval w is the distance between adjacent semiconductor regions 6.
The width is formed to the extent that the depletion layer of the pn junction is in contact.
If the width of the depletion layer is about 1.5 μm,
It is formed to have a thickness of about 3.5 μm. On the other hand, p⁺Semiconductor territory
As the thickness (depth) d of the semiconductor layer 2 below the region 6 is larger,
Withstand voltage can be increased, but withstand voltage of several tens of volts can be obtained.
It is preferable to form it to a minimum depth of
Good. Specifically, the spread of the depletion layer (about 1.5 μm)
Degree), a thickness of about 1 to 3 μm is secured below.
As described above, it is formed to be about 2.5 to 4.5 μm.
You. That is, p⁺The distance w between the semiconductor regions 6⁺
Is smaller than the depth d of the semiconductor layer 2 below the semiconductor region 6 having a rectangular shape.
It is preferably formed so as to be about 1: 1-2.
No.

The buried region 7 has a high impurity concentration of about 1 × 10 ¹⁶ to 1 × 10 ¹⁸ cm ^-3 on the lower surface of the semiconductor layer 2 in the gap between the p ^{+ -type} semiconductor regions 6, that is, on the semiconductor substrate 1 side. It is formed so that its height is about 1 to 1.5 μm in concentration. As a result, the distance h between the surface of the semiconductor layer 2 in the operation region A and the surface of the buried region 7 having a high impurity concentration sandwiched between the p ^{+ -type} semiconductor regions 6 is equal to the distance between the surface of the p ^{+ -type} semiconductor region 6 and the semiconductor. It is smaller by about 1 to 1.5 μm than the distance g from the upper surface of the substrate 1. The buried region 7 is formed, for example, in the semiconductor layer 2
Prior to epitaxial growth of n-type impurities, an n-type impurity is ion-implanted into the portion of the surface of the semiconductor substrate 1 by ion implantation or the like.
By introducing at a rate of about × 10 ¹⁶ to 1 × 10 ²⁰ cm ⁻² and epitaxially growing the semiconductor layer 2,
During the epitaxial growth, impurities are diffused into the epitaxially grown layer to form a buried layer 7 having a high impurity concentration.

The metal layer 3 is for forming a semiconductor layer and a Schottky barrier (Schottky junction), p ⁺
Region A of the semiconductor layer 2 in which the semiconductor region 6 in the shape of
An insulating film 5 is formed outside a part of the guard ring 4 on the outer periphery of the semiconductor device, and the surface (including the p ^{+ -type} semiconductor region 6) of 0.5 is formed on the surface of the operation region A by sputtering, vacuum deposition, or the like. It is formed to a thickness of about 1 μm. As described above, the metal layer 3 has a different barrier value depending on the material. For example, titanium (Ti) or molybdenum (M
o) and the like are used. An unillustrated overmetal such as silver (Ag) or aluminum (Al) is further provided on the surface of the metal layer 3 to a thickness of about 1 to 5 μm by a method such as sputtering or vacuum deposition. They are completely electrically connected to form electrode pads. Although not shown, an electrode made of Ni, Au, or the like is formed on the back surface of the semiconductor substrate 1.

Next, a method of manufacturing the Schottky barrier semiconductor device shown in FIG. 1 will be described with reference to FIG.

First, as shown in FIG. 2A, for example, an SiO ₂ film or the like is formed on a surface of an n ^{+ type} semiconductor substrate having an impurity concentration of about 1 × 10 ¹⁹ cm ^-3 by a CVD method or the like. Then, a mask 15 having an opening at a portion corresponding to an operation region sandwiched between p ^{+ -type} semiconductor regions 6 to be formed later is formed, and an n-type impurity 16 such as phosphorus (P) is formed.
1 × 10 ¹⁶ to 1 × 10 ²⁰ c by ion implantation
It is introduced at a rate of about m ^-2 .

Next, as shown in FIG.
1 × 10 on the surface of the conductive substrate 1^Fifteencm ^-3Degree n^-Type
Epitaxy of the recon semiconductor layer to a thickness of about 4 to 6.5 μm
Shall grow. This epitaxial growth is 1100
It is carried out at about 1200 ° C. for about 10 to 30 minutes.
The impurities introduced during the epitaxial growth
16 diffuses into the growing semiconductor layer 2 and¹⁶~ 1
× 10¹⁸cm^-3Buried region 7 of about high impurity concentration is formed
Is done.

Then, as shown in FIG. 2C, an insulating film made of SiO ₂ or the like is provided on the surface of the semiconductor layer 2 by a CVD method or the like, and only the portion where the second conductivity type semiconductor region 6 is formed is formed. By forming an open mask 11 and introducing and diffusing impurities such as boron (B), p
^{The + type} semiconductor region 6 is formed so that its depth is about 1.5 to 2 μm and its size is about 2 μm square.

After that, the mask 11 is removed to expose n
A metal forming a Schottky barrier, for example, Ti or Mo, is formed on the surfaces of the ^{− type} semiconductor layer 2 and the p ^{+ type} semiconductor region 6 to a thickness of about 0.5 to 1 μm by sputtering, and is formed around the guard ring 4. 1 by forming a metal layer 3 by patterning so as to cover
Are obtained.
Thereafter, although not shown, an overcoat film of Ag or Al is further provided on the front surface side, and electrodes made of Ni or Au are formed on the back surface of the semiconductor substrate 1 by sputtering or the like.

[0023] Figure 3 the relationship between the forward current I _F for the forward voltage V _F of the Schottky barrier diode having a structure shown in FIG. 1, the leakage current I _R for the reverse voltage V _R
Is shown in FIG. 4 as a characteristic P of the present invention in comparison with a characteristic Q1 of the conventional structure shown in FIG. 5 and a characteristic Q2 of the structure shown in FIG. As can be seen from FIG. 3, as for the forward voltage, the characteristic Q2 of the conventional structure shown in FIG. Even if it increases, the rise of the forward voltage does not become so large. Further, as is apparent from FIG. 4, the characteristic P of the leakage current with respect to the reverse voltage is almost the same as the characteristic Q2 of the conventional structure shown in FIG. 7, and the leakage current maintains a high characteristic. I know you are.

According to the present invention, since a plurality of semiconductor regions 6 of the second conductivity type are provided adjacent to each other on the surface of the semiconductor layer of the first conductivity type serving as the operation layer, a depletion layer formed therebetween is formed. Accordingly, the leakage current with respect to the reverse voltage can be prevented, and the leakage current in the reverse direction can be extremely reduced. On the other hand, the semiconductor layer 2 of the first conductivity type, which is the operation region A sandwiched between the semiconductor regions 6 of the second conductivity type, has a buried region 7 of a high impurity concentration provided on the bottom side thereof. The semiconductor layer 2 having a large resistance between electrodes provided above and below the structure to be formed becomes thin, and the series resistance becomes small. Therefore, even if the area is reduced and the series resistance is increased by providing the second conductivity type semiconductor region 6, the increase in the series resistance can be offset to reduce the series resistance. As a result, a Schottky barrier semiconductor device capable of reducing the forward voltage while reducing the leak current is obtained.

Further, according to the manufacturing method of the present invention, the high-resistance semiconductor layer in the operation region can be easily thinned without adding a special step such as etching, and the series resistance can be reduced.

[0026]

According to the present invention, a plurality of semiconductor regions of the second conductivity type are provided adjacent to each other in the semiconductor layer of the first conductivity type serving as the operation layer. A current can be prevented, and an increase in resistance due to a decrease in the area of the operation region due to the provision of the semiconductor region of the second conductivity type is reduced by reducing the thickness of the operation region of the semiconductor layer of the first conductivity type. , The series resistance can be reduced, and the forward voltage can be reduced. As a result, a high-performance Schottky barrier semiconductor device having a low forward voltage and a small leakage current can be obtained, which greatly contributes to a reduction in the weight, size, and power consumption of electronic devices.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of one embodiment of a Schottky barrier semiconductor device of the present invention.

FIG. 2 is an explanatory sectional view showing a manufacturing process of the Schottky barrier semiconductor device of FIG. 1;

FIG. 3 shows V _F − of the Schottky barrier semiconductor device of FIG. 1;
It is a figure which shows _IF characteristic.

FIG. 4 is a graph showing the relationship between V _R − of the Schottky barrier semiconductor device in FIG. 1 _;
It is a figure which shows an _IR characteristic.

FIG. 5 is an explanatory sectional view of a conventional Schottky barrier semiconductor device.

6 is a graph showing the relationship between the leakage current I _R of the barrier values and the forward voltage V _F and the reverse direction between the semiconductor layer and the metal layer.

FIG. 7 is an explanatory sectional view of another structure of a conventional Schottky barrier semiconductor device.

[Explanation of symbols]

1 semiconductor substrate 2 n ^- -type semiconductor layer 3 a metal layer 6 p ⁺ -type semiconductor region 7 buried region

Claims (3)

[Claims] 1. A semiconductor substrate of a first conductivity type having a high impurity concentration, a semiconductor layer of a first conductivity type having a low impurity concentration epitaxially grown on the semiconductor substrate, and at least two or more semiconductor layers on the surface side of the semiconductor layer. A semiconductor layer of a second conductivity type provided adjacently over the region, and a metal layer forming a Schottky barrier provided on the surface of the semiconductor layer and the semiconductor region of the second conductivity type; A Schottky barrier semiconductor device in which a first conductivity type buried region having a high impurity concentration is formed on the semiconductor substrate side of a first conductivity type semiconductor layer which is an operation region without forming a conductivity type semiconductor region. (A) selectively introducing a first conductivity type impurity into a surface of a first conductivity type semiconductor substrate having a high impurity concentration;
(B) epitaxially growing a low impurity concentration first conductivity type semiconductor layer on the surface of the semiconductor substrate, and forming a high impurity concentration buried region by rising of the introduced first conductivity type impurity; A buried region is formed by forming a mask on a surface of the epitaxially grown semiconductor layer and covering a portion corresponding to a place where the first conductivity type impurity is introduced into the semiconductor substrate and introducing a second conductivity type impurity. Forming two or more semiconductor regions of the second conductivity type adjacent to the surface side of the semiconductor layer at a place sandwiching the portion where
(D) A method of manufacturing a Schottky barrier semiconductor device, comprising: providing a metal layer for forming a Schottky barrier on surfaces of the semiconductor layer and the second conductivity type semiconductor region. 3. A ratio of the distance between the adjacent second conductivity type semiconductor regions and the distance between the bottom surface of the second conductivity type semiconductor region and the bottom surface of the first conductivity type semiconductor layer is 1: 1 to 1: 1. 3. The method of manufacturing a Schottky barrier semiconductor device according to claim 2, wherein the semiconductor region of the second conductivity type is formed so as to be 2.