JP2000058717A - Flat semiconductor device and converter using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method by which a highly reliable flat semiconductor device can be realized at a low cost. SOLUTION: A semiconductor device is constituted by incorporating at least one or more semiconductor elements 1 having at least first main electrodes 4 on first main surfaces, and second main electrodes 5 on second main surfaces in a flat package. In the flat package, a pair of main electrode plates exposed on both surfaces are electrically insulated from each other by means of an insulating outer casing. The outer peripheral surface parts of the semiconductor elements 1 which are not faced to intermediate electrode plates 2 and 3 and at least parts of the side faces of the electrode plates 2 and 3 are compactly sealed with an electrical insulating material 6. Therefor, the manufacturing cost of a flat type semiconductor device can be reduced without spoiling the reliability of the device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat type semiconductor device, and more particularly, to a flat type semiconductor device capable of realizing high reliability at low cost and a converter using the same.

[0002]

2. Description of the Related Art The technology of power electronics, which controls the main circuit current by making full use of the technology of semiconductor electronics, has been applied in a wide range of fields, and its application is being expanded. As power semiconductor elements, thyristors, optical thyristors, GTO (Gate Turn-off) thyristors, GCT (Gate Commutated Turn-off) thyristors, insulated gate bipolar transistors (hereinafter abbreviated as IGBTs) and MOS type MOS control devices There are a field effect transistor (hereinafter abbreviated as MOSFET), a diode, and the like. In these semiconductor devices, a first main electrode (cathode electrode, emitter electrode) is generally provided on a first main surface.
And a control electrode, and another second main electrode (anode electrode, collector electrode) is formed on the second main surface side.

In a high-power semiconductor device such as a GTO or an optical thyristor, elements are packaged for each wafer. Both main electrodes of the above-mentioned element are structured to be in pressure contact with a pair of external main electrodes of the package via an intermediate electrode plate (heat buffer electrode plate) made of Mo or W, which is suitable for pressurization. A flat structure is common.

On the other hand, in IGBTs and the like, a plurality of chips have been mounted so far mainly in a package form of an electrode connection system using wires, which is called a module type structure. In the case of such a modular package, heat generated inside the element is released only from one side of the package, that is, only from the collector side directly mounted on the metal base, so that the thermal resistance is generally large and can be mounted in one package. The number of chips (calorific value or current capacity) was limited. Recently, in order to deal with such a problem and respond to the demand for large capacity, a plurality of IGBT elements are incorporated in parallel in a flat package similar to the above-mentioned GTO, optical thyristor, etc. package and formed on the main surface thereof. Attention has been paid to a flat semiconductor device having a multi-chip parallel type pressure contact structure in which the emitter electrode and the collector electrode are brought into surface contact with a pair of external main electrode plates provided on the package side and are drawn out. According to the flat package structure, 1) the connection of the main electrode is not wire-bonded, thereby improving the connection reliability, and 2) the inductance and resistance of the connection conductor are smaller than those of the conventional module type package. 3) Since the semiconductor chip can be cooled from both sides, the cooling efficiency can be improved, and the like can be expected.

[0005]

In a conventional flat type semiconductor device, as shown in FIG. 10, in order to protect a built-in semiconductor element (not shown), the inside of the package is hermetically sealed (hermetic structure). (For example, see JP-A-7-6
6228, JP-A-7-254669, JP-A-8-33033
No. 8, etc.). Specifically, the external main electrode plates 4 and 5
A metal flange 32 between the
33, and the inside is hermetically sealed. Although the moisture tight reliability of the flat semiconductor device is ensured by this hermetic sealing structure, there is a problem that the cost of the hermetically sealed parts itself and the operation cost for hermetic sealing are high.

Further, in the semiconductor device described above, it is necessary to secure a creepage distance outside the package of a predetermined length or more in accordance with the withstand voltage of the element in order to guarantee the insulation properties outside the package for a long time. For this reason, a method of increasing the external creepage distance by performing complicated shape processing on the outer portion (A portion in FIG. 10) of the ceramic outer cylinder 31 is generally used. However, since ceramics are generally very hard and difficult-to-process materials, such complicated shape processing of ceramics is expensive and one of the major factors for increasing package cost.

The withstand voltage of semiconductor devices tends to be higher in the future. In particular, the flat semiconductor device is strongly required to have a large capacity, and the withstand voltage of devices is becoming remarkable. In a modular package,
In order to secure insulation (ground insulation performance) between the heat sink and the element exposed to the outside of the package and to deal with the problem of discharge between the mounting wiring inside the package, etc., and to reduce the size of the package, Filling the inside with gel ensures insulation reliability. On the other hand, in the case of an element having a flat structure, it is sufficient that insulation between the main electrodes can be ensured when the element is turned off. Until now, it has basically been dealt with by securing a space distance. However, in the future,
As the breakdown voltage of the device is further increased, it is becoming a very difficult task to secure the breakdown voltage around the semiconductor device including the mounting structure (prevent discharge) and to secure the insulation reliability.

Further, in a flat semiconductor device of a type in which multiple chips are mounted in parallel, as disclosed in, for example, Japanese Patent Application Laid-Open No. 7-94673 and Fuji Times, Vol. 69, No. 5 (1996), Although frame components for positioning each chip are used, the mounting density is reduced by these members. In order to make the size of the flat type semiconductor device as small as possible and to increase the conversion capacity, it is necessary to further improve the mounting density of the built-in semiconductor elements. Further, since extra individual parts for positioning are required and the number of parts is increased, there is a problem to be improved in terms of assembling workability, parts cost, and the like.

SUMMARY OF THE INVENTION It is an object of the present invention to secure the moisture resistance reliability and insulation reliability of a flat type semiconductor device, to reduce the mounting cost, to improve the mounting density of elements, It is an object of the present invention to provide a method for realizing miniaturization, improvement of assembly workability, and the like. A second object is to provide a highly reliable and inexpensive large-capacity converter by using the semiconductor device obtained as described above.

[0010]

The object of the present invention is to provide at least one semiconductor having at least a first main electrode on a first main surface and a second main electrode on a second main surface between a pair of main electrode plates. In a semiconductor device incorporating a device, a separate intermediate electrode plate is provided for each semiconductor device between two main electrodes of the semiconductor device and a main electrode plate facing the same, and the intermediate electrode plate and the The problem can be solved by using an assembly structure (chip carrier structure) of a semiconductor element and an intermediate electrode plate in which at least a part of a side surface of the intermediate electrode plate that is not opposed to the outer peripheral portion is sealed with an electrically insulating material.

Further, by using a non-hermetic structure of a resin component as an electrically insulating outer cylinder that insulates and seals between a pair of main electrode plates exposed on both surfaces, further reduction in cost can be realized.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A typical embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows an example of a semiconductor device in which a semiconductor element 1 is mounted between a pair of main electrode plates 4 and 5, and two main electrodes of the semiconductor element 1 and respective opposing opposing electrodes. Each of the semiconductor elements is mounted between the main electrode plates 4 and 5 with individual intermediate electrode plates 2 and 3 interposed therebetween. The Al electrode of the first main electrode of the semiconductor element 1 and the Mo intermediate electrode plate 2 having the Au plating layer formed on the surface on the first main electrode side are joined via a joining layer. Similarly, the Ag electrode of the second main electrode of the semiconductor element 1 and the A
g Between the Mo intermediate electrode plate 3 on which the plating layer is formed, Ag
Are bonded via a bonding layer of Before assembling the semiconductor element 1 and the intermediate electrode plates 2 and 3 between the main electrode plates 4 and 5, the intermediate electrode plate 2
A liquid silicone resin 6 was applied so as to seal at least a part of the outer peripheral portion not opposed to and the side surfaces of the intermediate electrode plates 2 and 3, and was heated and cured at 150 ° C. Thus, a chip carrier structure (assembly structure) including the semiconductor element 1 and the intermediate electrode plates 2 and 3 is formed. The outer peripheral portion of the semiconductor element surface not facing the intermediate electrode plate includes the side surface of the semiconductor element.

The chip carrier structure (assembly structure) composed of the semiconductor element 1 and the intermediate electrode plates 2 and 3 sealed with an electrically insulating material is a very compact and simple structure, and is an inexpensive insulating material sealing type. Semiconductor device can be realized. It is desirable that the size of the chip carrier structure in the plane direction is as compact as possible, substantially equal to the size of the semiconductor element. More specifically,
It is preferable that the maximum outer diameter area of the carrier is about 1.4 times or less the semiconductor element area and about 1.2 times or less the side dimension.

From the viewpoint of handling during the manufacture of the semiconductor element 1 and protection from the external environment, it is preferable that the semiconductor element 1 is used in a form in which the semiconductor element is protected by a resin.

In FIG. 1, intermediate electrode plates 2 and 3 serving as electrodes exposed on the surface of the chip carrier structure and main electrode plates 4 and 5 are shown.
The semiconductor device is incorporated in the flat semiconductor device so as to be in direct contact with each other. In order to reduce the contact thermal resistance and the contact electric resistance of the semiconductor device as much as possible, it is preferable to make direct contact.

FIG. 2 shows a side view of the semiconductor device 1 and the semiconductor device 1.
Of a chip carrier in which at least a part of an outer peripheral portion of the first main electrode surface not facing the intermediate electrode plate 2 and at least a part of a side surface of the intermediate electrode plate 2 interposed on the first main electrode side is sealed with a silicone-modified resin 6. An example is shown. The first main electrode of the semiconductor element 1 and the intermediate electrode plate 2 on the first main electrode side are joined, and the second main electrode of the semiconductor element 1 and the intermediate electrode plate on the second main electrode side are joined. No connection is made between the three. In this embodiment, since the intermediate electrode plate 3 is used as a common substrate for the plurality of semiconductor elements 1, the chip carrier has the above-described configuration. When a large number of the above-described chip carriers are mounted, it is preferable that the insulating materials on the side surfaces of the chip carriers are abutted against each other without any gap as shown in the drawing.

FIGS. 3A and 3B show the side surface of the semiconductor element 1, the outer peripheral portion of the first main electrode surface of the semiconductor element 1 which does not face the intermediate electrode plate 2, and the first main electrode, as in FIG. As another example of the chip carrier in which at least a part of the side surface of the intermediate electrode plate 2 interposed on the side is sealed with an electrically insulating material 6, an intermediate electrode plate 3 on the second main electrode side is provided for each semiconductor element 1. 2 shows an example in which it is divided individually.

FIG. 3 (a) shows an electric insulating material 6 in which a slurry obtained by kneading ceramic powder of silica, zirconia, magnesia or the like with water is injected using a mold, cast and cured at room temperature, as shown in the figure. The resulting ceramic-sealed chip carrier is excellent in electrical insulation and heat resistance. FIG. 3B shows an electrically insulating material 6.
Are examples of materials mainly composed of glass or crystallized glass. Lead-based paste glass (main component: PbO-Si
O ₂ —Al ₂ O ₃ ) is applied, and 780 to 85 in an oxygen atmosphere.
It is configured by performing a heat treatment at 0 ° C. for 40 minutes to form a glass film 7 fired by glass. The material is ZnO
-B ₂ O ₃ -SiO ₂ based glass, PbO-Al ₂ O ₃ -Si
A glass having a thermal expansion coefficient as close as possible to that of a semiconductor element and melting at a low temperature, such as an O ₂ -based glass and a ZnO—B ₂ O ₃ —SiO ₂ -based crystallized glass, is desirable. Further, it is preferable to use glass having as little alkali impurities as possible. In particular, when used under severe use conditions that require high environmental resistance, an inorganic material based airtight material having excellent heat resistance is preferable.

FIG. 4 is a side view of the semiconductor element 1, an outer peripheral portion of the first main electrode surface of the semiconductor element 1 not facing the intermediate electrode plate 2, and a side surface of the intermediate electrode plate 2 interposed on the second main electrode side. 2 shows an example of a form of a chip carrier in which at least a part of the chip carrier is sealed with an electrically insulating material 6. The first main electrode of the semiconductor element 1 and the intermediate electrode plate 2 on the first main electrode side are not joined. The feature of this structure is that only the peripheral portion of the semiconductor element is insulated and sealed, and only the most important part for ensuring the insulation around the semiconductor element is sealed. Even with this shape, insulation reliability can be sufficiently ensured, and there is no problem.

However, in the above case, since the surface of the semiconductor element is not completely sealed, in order to ensure moisture resistance reliability, a pair of main electrode plates exposed on both surfaces of the flat type semiconductor device are externally insulated. It is necessary to make the insulating outer cylinder made of ceramics and to hermetically seal it. It is of course possible to use the chip carrier of the completely sealed type of the insulating material of the present invention, and to further hermetically seal the insulating outer cylinder portion. When hermetic sealing is indispensable, at least a part of an electrically insulating outer cylinder that insulates and seals a pair of common main electrode plates exposed on both surfaces is made of a resin component. A composite insulating outer cylinder made of a material-based dense insulating component and a resin component, and hermetically sealed with the inorganic dense insulating component, may have a structure that ensures a sufficient external creepage distance at the resin component. This is an effective method. That is, by separating the function of the material for hermetic sealing and the material for securing the insulation distance (creepage distance), high long-term reliability and low cost can be realized. The present invention achieves a cost reduction by realizing a complicated shape portion by using a resin component which is easy to process and mold, and by sufficiently securing an external insulation distance of the semiconductor device.

As a specific embodiment, for example, an outer cylinder ring made of a polyphenylene sulfide resin (with a tracking resistance of 600 V or more) previously molded by injection molding is attached to the outside of a simple cylindrical outer cylinder made of ceramics with a silicone adhesive. Glued to the part. As a result, the specified value of the external creepage distance can be secured sufficiently, and sufficient reliability was confirmed in the acceleration test. As another method, an example in which the resin outer ring as described above is divided into two parts will be described. The split parts are fitted together at their ends. The division is not limited to the two in this example,
What is necessary is just to divide | segment according to the shape of the ceramic outer cylinder part combined so that an assembly may become easy. In the composite insulating outer cylinder of the insulating outer cylinder component such as ceramics and the resin component as described above, a composite insulating outer cylinder may be formed before the element is incorporated, or as in the above embodiment. After the element is assembled and sealed, the resin portion may be manufactured by potting, fitting / adhering, or the like. Also, the resin portion may of course be shaped to cover the entire surface of the ceramic component.
In this case, cracking of the ceramic due to impact during handling,
It also has the effect of preventing crossing, and is more preferable.

As a characteristic required for the above resin-based material, it is desirable that the tracking resistance (CTI value) is 400 V or more, more preferably 600 V or more. It is preferable to use a UL94V-0 level flame retardant. In terms of thermo-mechanical properties, it is preferable that the material be a material system having high mechanical strength and fracture toughness and capable of adjusting the coefficient of thermal expansion to an optimum value determined in consideration of other mounting materials and mounting forms. In the case of integrally integrating with an electrically insulated outer cylinder part such as ceramics, it is preferable that the thermal expansion coefficient is as close as possible to that of the ceramic parts. As a specific material, it is preferable to use a silicone-based or fluorine-based elastomer in addition to a thermosetting resin such as an epoxy-based or phenol-based resin. An engineering plastic thermoplastic resin such as polyphenylene sulfide (PPS), aromatic polyamide, and thermoplastic polyimide can also be used.
Furthermore, those obtained by compounding various fillers with these materials can also be used. Since it is a resin component, the shape of the external creeping surface can be designed relatively freely as compared with the conventional ceramic component, so that there is an advantage that the restriction on the design for securing the external creeping distance can be reduced.

In addition to the potting shown in the above example, the resin component can be manufactured by injection molding, transfer molding, compression molding, powder sintering, or the like. What is necessary is just to select the optimal method according to it. In particular, in order to integrally mold a resin component directly on a ceramic outer cylinder using potting, thermosetting materials such as silicone, urethane, polystyrene, polybutadiene, and elastomers composed of these copolymers, and epoxy and phenolic resins It is preferred to use When a preformed resin part is bonded to an electrically insulating outer cylinder part such as ceramics or an electrode material by integrating it, a silicone-based, fluorine-based, or epoxy-based rubber is used as the adhesive. Is preferable because the stress can be relaxed.

On the other hand, materials used for ceramic outer cylinder parts include ordinary porcelain such as feldspar-like ordinary porcelain, cristobalite porcelain, alumina-containing porcelain, and alumina-containing cristobalite porcelain, and alumina, magnesia, beryllia, steatite, forsterite, and corde. It is preferable to use a glass-based material such as glass ceramics, borosilicate glass, quartz glass, high silicate glass, etc., in addition to a material mainly containing yerite, mullite, zircon, zirconia, or the like. When joining the inorganic material-based electrically insulating outer cylinder component and the resin component, it is also an effective method to increase the bonding strength with the resin component by making the surface of the inorganic material-based electrically insulating outer cylinder component uneven. For this purpose, the surface of the inorganic material-based electrically insulating outer cylinder is intentionally left with irregularities depending on the sintering conditions, or sandblasting, liquid honing, or the like after normal sintering.
It is effective to easily process using techniques such as etching, chemical grinding, and electrolytic grinding.

FIG. 5A shows an embodiment of a double resin filling structure. After the first insulating sealing material 6 is formed, the second insulating sealing material 8 is filled. By changing the physical properties of the first insulating sealing material 6 and the second insulating sealing material 8, it becomes possible to select a chip carrier structure that maintains a stress state optimal for the use conditions of the semiconductor device. For example, by setting the Young's modulus of the second sealing material to be lower than the Young's modulus of the first sealing material, the stress generated on the semiconductor element surface is reduced, and the insulating property of the second sealing material is reduced. , It is possible to select a combination that can ensure workability. Specifically, the first sealing material can be a silicone resin, and the second sealing material can be a silicone rubber or a silicone gel. Since gel alone cannot provide moldability, another frame material is required to maintain the shape as the first sealing material. It is not so preferable as one insulating material.

FIG. 5B shows another embodiment of the double resin filling structure. The first insulating sealing material 9 (for example, an engineering plastic resin) is mainly used as a frame for filling the second insulating sealing material 9 (silicone resin), and is used as a part of the chip carrier as it is. It is an example. For example, by changing the physical properties of the first insulating sealing material 9 and the second insulating sealing material 8, a structure that is stable against external stress on the chip carrier can be realized.

FIG. 6 shows an embodiment of a chip carrier when a semiconductor element having a first main electrode and a control electrode (gate electrode) on a first main surface is incorporated (FIG. 1 + FIG. 5 + gate wiring). FIG. 6A shows an example in which a gate extraction pin 10 is joined to a gate control electrode formed in the center of the semiconductor element 1. The pin 10 for taking out the gate is provided with a head processing 11 whose tip on the chip side is larger in diameter than the pin. The side surface of the semiconductor element 1 and the outer peripheral portion of the first main electrode surface that is not in contact with the intermediate electrode plate 2 and the side surface of the intermediate electrode plate 3 on the second main electrode side with the first sealing material 6 (phenol resin). At least a part is uniformly sealed, and the remaining part is filled with the second sealing material 8 (silicone gel) to obtain a completely sealed chip carrier.

FIG. 6B shows an example in which a gate wiring 13 is formed by wire bonding on a gate control electrode 12 formed in a peripheral portion of the semiconductor element 1. First sealing material 6
The side surface of the semiconductor element 1 and the outer peripheral portion of the first main electrode surface that is not in contact with the intermediate electrode plate 2 and at least a part of the side surface of the intermediate electrode plate 3 on the second main electrode side are made uniform with (epoxy resin). Seal, and further, a second sealing material 8 (silicone rubber)
Is filled in the remaining portion to obtain a completely sealed chip carrier.

FIG. 6C shows another embodiment in which a gate wiring 13 is formed by wire bonding on a gate control electrode 12 formed on the periphery of the semiconductor element 1. An epoxy resin was filled with quartz powder, and a composite material having a reduced thermal expansion was used as an insulating sealing material. The side surface of the semiconductor element 1, the outer peripheral portion of the first main electrode surface that is not in contact with the intermediate electrode plate 2, at least a part of the side surface of the intermediate electrode plates 2 and 3, and the wire drawing portion are uniformly made of the composite resin. To obtain a completely sealed chip carrier.

As the sealing resin of an organic material, an electrically insulating resin such as an epoxy resin, a phenol resin, and a polyester resin is suitable, and a thermosetting resin having a composition which is gradually cured by heating is preferable. In particular, those based on epoxy resin are suitable, and curing agents, catalysts, pigments, fillers, and additives can be used for improving / retaining properties as required. In particular, by using a low thermal expansion inorganic material powder such as crystalline and fusible silica powder and alumina powder as the filler, the thermal expansion coefficient of the composite material of the resin and the powder can be reduced by using a semiconductor chip or an intermediate electrode plate. Since the coefficient of thermal expansion can be approximated, reliability with respect to a temperature cycle is improved. Generally, it is preferably contained in an amount of about 60% or more of the entire resin composition, and particularly preferably in the range of 7 to 9% by weight. Further, by increasing the amount of the inorganic filler, it is possible to reduce the amount of water absorption and improve the resin strength. Further, the epoxy resin composition used in the present invention may contain a silicone oil and a rubber component such as silicone rubber or synthetic rubber in addition to the above-mentioned additives to reduce stress or improve moisture resistance reliability. And an ion trapping agent such as hydrotalcite.

The workability such as flowability, low-temperature curing property, defoaming property, low thixotropy, and mold release property when molding using a mold is improved, and low thermal expansion and low content of impurity ions are included. For such requirements, an optimal resin or a composite resin can be selected. It is also possible to reduce the stress by using silicone rubber or silicone-modified resin to improve the thermal shock resistance.

It is of course possible to use a thermoplastic resin, and as the material, thermoplastic polyimide, aromatic polyamide, polyamideimide resin, polyetheretherketone (PEEK), PPO, PPS, liquid crystal polymer, etc. can be used. However, it is necessary to heat and melt and inject, and care must be taken when handling.

In addition to the thermosetting resin, an ultraviolet curable resin,
A semiconductor device using an active energy ray-curable resin such as an electron beam-curable resin that is cured by an active energy ray can also be used depending on the application, process conditions, and the like. Typical compositions of the active energy ray-curable resin include alkyd resin having an unsaturated group such as acrylic acid group, allyl group, itaconic acid group, conjugated double bond, etc., acrylic resin,
Urethane resin, polyurethane resin, epoxy resin and the like can be mentioned.

The sealing of the semiconductor element using the organic resin composition is not particularly limited, and can be performed by a known molding method such as ordinary transfer molding. Furthermore, in order to reduce the size and thickness, save labor, and reduce the number of processes,
There is also a method in which a semiconductor element is mounted on an intermediate electrode plate and bonded, and a resin is dropped and coated. In order to improve workability, a method of applying a thermosetting resin to a predetermined position with an automatic dispenser or the like and then thermosetting the resin is preferable. Furthermore, with the semiconductor element and the intermediate electrode plate set in the frame for the sealing operation, the liquid sealing resin is poured over the entire surface of the frame and degassed in a vacuum, thereby achieving good sealing without bubbles. Can be.

FIG. 7 shows an example in which the present invention is applied to a reverse conduction type switching device incorporating a flywheel diode (FWD) connected in anti-parallel with a switching device using an IGBT. The figure shows only a partial cross section of the cross section of the flat type semiconductor device from the outermost part to the middle toward the center. The IGBT chip 14 has an emitter electrode formed on almost the entire first main surface on the upper surface side and a collector electrode on the second main surface on the lower surface side, and further has a control electrode (gate electrode) on the first main surface. Are formed. In the FWD chip 15, an anode electrode is formed on the upper surface side of the silicon substrate, and a cathode electrode is formed on the lower surface side.
In each of these semiconductor chips, intermediate electrodes 2 and 3 made of Mo, which perform both heat radiation and electrical connection, are joined to the respective main electrodes on the chip, and these are further connected to the first main electrode plate 4 (C
u) and the second main electrode plate 5 (Cu). Further, the wiring 13 is drawn out from the gate electrode of the IGBT chip 14 by wire bonding, and further connected to the gate electrode wiring 16 formed on the main electrode plate 5. The semiconductor chips 14 and 15 and the intermediate electrode plates 2 and 3 have a structure sealed with a silicone resin 6.

FIG. 7 shows a case where the insulating outer cylinder is made of resin and has a non-hermetic structure (non-hermetic structure, non-sealed structure), that is, a pair of external main electrode plates 4 and 5.
This shows an example in which the outer space is sealed by an outer cylinder 17 made of an aromatic polyamide. A sealing structure in which the external main electrode plates 4 and 5 and the insulating outer cylinder 17 are bonded with an organic adhesive 19 is provided. Further, a metal wiring 20 fixed with an adhesive is formed on the insulating outer cylinder 17, so that the gate electrode wiring 16 is drawn out of the package. In the case of the seal structure of the bonding portion 19 of the present embodiment, when the semiconductor device is used under pressure, the direction in which the bonding portion is always pressed to make the seal stronger is preferable. It is preferable to use an adhesive having a large elastic deformability as the adhesive can cope with a change in the distance between the main electrodes during pressurization and deformation during use. Compared to the case of a conventional ceramic outer cylinder part, when resin is used, it is possible to easily increase the outer surface unevenness to increase the edge surface distance. Further, a resin device having an insulating outer cylinder made of resin is not so fragile as to ceramics against shocks, so that the semiconductor device has excellent shock resistance reliability.

According to the method of the present invention, a flat semiconductor device in which a large number of semiconductor elements are juxtaposed and incorporated between a pair of main electrode plates, or a semiconductor element wafer in which the semiconductor elements have at least one PN junction is used. The present invention can be applied to any system such as a flat semiconductor device. In addition to the above embodiments, a flat semiconductor device including only a switching element such as an IGBT without a diode, a flat diode device in which only a plurality of diode chips are mounted in a flat package, and the like are of course effective. . The present invention is intended for general semiconductor devices having at least a first main electrode on a first main surface and a second main electrode on a second main surface, and is an insulated gate transistor (MOS transistor) other than an IGBT.
And IGCT (Insulated Gate Controlled Thyristor)
The present invention can be similarly applied to a semiconductor element with a control electrode such as an insulated gate thyristor (MOS control thyristor), a GTO thyristor, a GCT thyristor, an optical thyristor, a thyristor, and a diode having no control electrode. Further, the present invention relates to SiC, GaN other than Si elements.
It is similarly effective in the case of using compound semiconductor elements such as these and in their new use environment (for example, high-temperature environment).

By using the flat type semiconductor device of the present invention, it is possible to realize a large-capacity converter whose converter cost is greatly reduced. FIG. 8 is a configuration circuit diagram of one bridge in which the IGBT flat semiconductor device according to the present invention is applied to a power converter as a main conversion element. I to be the main conversion element
The GBT 21 and the diode 22 are arranged in anti-parallel, and have a configuration in which n units are connected in series. These I
The GBT 21 and the diode 22 represent a flat semiconductor device in which a number of semiconductor chips according to the embodiment of the present invention are mounted in parallel. In the case of the reverse conducting IGBT flat type semiconductor device of the above embodiment, the IGBT 21 and the diode 22 in the drawing are collectively housed in one package. This is provided with a snubber circuit 23 and a current limiting circuit. FIG. 9 shows the configuration of a self-excited converter in which the three-phase bridge of FIG. 8 is multiplexed by four. The flat semiconductor device of the present invention is mounted in a so-called stack structure in which a plurality of the semiconductor devices are connected in series with a water-cooled electrode interposed therebetween so as to be in surface contact with the outside of the main electrode plate, and the entire stack is pressurized at once.

The flat semiconductor device of the present invention is not particularly limited to the above example, and is particularly suitable for a self-excited large-capacity converter used in a power system or a large-capacity converter used as a converter for a mill. It can also be used for power generation, substation facilities in buildings, substation facilities for railways, sodium-sulfur (NaS) battery systems, converters for vehicles, and the like.

[0041]

By using the chip carrier structure (assembly structure) of the semiconductor element sealed with the insulating material of the present invention and the intermediate electrode plate, it is possible to improve the moisture resistance reliability, insulation reliability, etc., and to improve the mounting unit. The miniaturization and the mounting density can be improved, and these can be realized at low cost.

In a flat semiconductor device in which a large number of semiconductor elements are mounted in parallel between a pair of main electrode plates, each semiconductor element has a small chip carrier structure.
The workability (handling property) at the time of assembly is improved, and the repair on a chip carrier basis becomes very easy. Stability is improved from the viewpoint of protection from an external environment during and after manufacturing. Therefore, the flat type semiconductor device according to the present invention can realize a reduction in component cost, an assembly cost, and the like as a semiconductor device and an improvement in yield while ensuring high reliability.

In a flat semiconductor device incorporating a chip carrier in which the entire surface of a semiconductor element is completely sealed, a non-hermetic structure can be obtained. By changing from conventional ceramics to inexpensive resins and the like, even lower cost is possible.

By using the flat semiconductor device of the present invention having the above-described features, the cost of the converter system can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing another embodiment of the present invention.

FIG. 3 is a diagram showing another embodiment of the present invention.

FIG. 4 is a diagram showing another embodiment of the present invention.

FIG. 5 is a diagram showing another embodiment of the present invention.

FIG. 6 is a diagram showing another embodiment of the present invention in which a control terminal is formed.

FIG. 7 is a diagram illustrating an all-resin outer cylinder part and a mounting form thereof.

FIG. 8 is a configuration circuit diagram of one bridge using the semiconductor device of the present invention.

9 is a configuration diagram of a self-excited converter in which the three-phase bridge of FIG. 8 is multiplexed by four.

FIG. 10 shows a conventional flat semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor element, 2,3 ... Intermediate electrode, 4,5 ... Main electrode plate, 6,7 ... Electrically insulating material, 8 ... Second electrically insulating material, 9 ... Electrically insulating material, 10 ... Pin, 11 pin head, 12 gate control electrode, 13 gate wiring, 14
IGBT, 15: flywheel diode, 16: gate electrode wiring, 17: insulating cylinder, 19: organic adhesive, 2
0: metal wiring, 21: IGBT, 22: diode, 2
3: snubber circuit, 31: ceramic parts, 32, 33
... metal flange.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Mamoru Sawahata 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside the Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Mitsuru Hasegawa 7-1-1 Omika-cho, Hitachi City, Ibaraki Prefecture No. 1 F term in Hitachi Research Laboratory, Hitachi, Ltd. F-term (reference) 4M109 AA01 CA01 CA02 CA05 CA21 CA22 DB02 DB10 EA02 EA10 EA11 EA12 EA18 EA20 EB02 EB04 EB08 EB12 EB18 EB19 EC04 EC09 GA10 5F005 AE09 AF01 AF02 GA01 GA03 GA04

Claims (14)

[Claims] A flat package in which a pair of main electrode plates exposed on both sides are externally insulated by an insulating outer cylinder, at least a first main electrode on a first main surface, and a second main electrode on a second main surface. A semiconductor device incorporating at least one or more semiconductor elements having a main electrode, wherein a separate intermediate element is provided for each of the semiconductor elements between two main electrodes of the semiconductor element and the main electrode plate opposed thereto. A flat type wherein an electrode plate is interposed, and an outer peripheral portion of the semiconductor element surface not facing the intermediate electrode plate and at least a part of a side surface of the intermediate electrode plate are sealed with an electrically insulating material. Semiconductor device. 2. A flat package in which a pair of main electrode plates exposed on both sides are externally insulated by an insulating outer cylinder, at least a first main electrode on a first main surface and a second main electrode on a second main surface. A semiconductor device incorporating at least one or more semiconductor elements having a main electrode, wherein at least a first intermediate electrode is provided between the main electrode of the semiconductor element and the main electrode plate facing the semiconductor element. An electrode plate is interposed, a side surface of the semiconductor element, an outer peripheral portion of the first main electrode surface of the semiconductor element not facing the intermediate electrode plate, and at least a side surface of the intermediate electrode plate interposed on the first main electrode side. A flat semiconductor device, a part of which is sealed with an electrically insulating material. 3. A flat package in which a pair of main electrode plates exposed on both sides are externally insulated by an insulating outer cylinder, at least a first main electrode on a first main surface and a second main electrode on a second main surface. A semiconductor device incorporating at least one or more semiconductor elements having a main electrode, wherein a separate intermediate element is provided for each of the semiconductor elements between two main electrodes of the semiconductor element and the main electrode plate opposed thereto. An electrode plate is interposed, a side surface of the semiconductor element, an outer peripheral portion of the first main electrode surface of the semiconductor element not facing the intermediate electrode plate, and at least a side surface of the intermediate electrode plate interposed on the second main electrode side. A flat semiconductor device, a part of which is sealed with an electrically insulating material. 4. The flat semiconductor device according to claim 1, wherein at least a second main electrode of the main electrodes of the semiconductor element is joined to an intermediate electrode plate facing the second main electrode. 5. The flat type semiconductor device according to claim 1, wherein at least a first main electrode of the main electrodes of the semiconductor element is joined to an intermediate electrode plate facing the first main electrode. 6. The flat semiconductor device according to claim 1, wherein said electrically insulating material is a material having moldability. 7. The flat semiconductor device according to claim 1, wherein said electrically insulating material is a material mainly composed of a thermosetting or thermoplastic resin. 8. The method according to claim 1, wherein said electrically insulating material is a composite material of a thermosetting resin and an inorganic material powder.
8. The flat semiconductor device according to any one of claims 7 to 7. 9. The flat semiconductor device according to claim 1, wherein said electrically insulating material is a material mainly composed of glass or ceramics. 10. The semiconductor device and the structure integrated with the intermediate electrode plate, which are sealed with the electrically insulating material, have a planar size substantially equal to the size of the semiconductor device. Item 10. The flat semiconductor device according to any one of Items 1 to 9. 11. The flat type semiconductor device according to claim 1, wherein an insulating outer cylinder for externally insulating between a pair of main electrode plates exposed on both surfaces of said flat type semiconductor device is made of resin. Semiconductor device. 12. A flat package in which a pair of main electrode plates exposed on both sides are externally insulated by an insulating outer cylinder.
A semiconductor device incorporating at least one or more semiconductor elements having at least a first main electrode on a first main surface and a second main electrode on a second main surface, comprising two main electrodes of the semiconductor element and A separate intermediate electrode plate is provided for each of the semiconductor elements between the main electrode plate and the outer peripheral portion of the semiconductor element surface that does not face the intermediate electrode plate, and a side surface of the intermediate electrode plate. A power converter characterized in that a flat semiconductor device at least partially sealed with an electrically insulating material is used as a main conversion element. 13. A flat package in which a pair of main electrode plates exposed on both sides are externally insulated by an insulating outer cylinder.
A semiconductor device incorporating at least one semiconductor element having at least a first main electrode on a first main surface and a second main electrode on a second main surface, wherein the semiconductor element has a main electrode facing the main electrode. A separate intermediate electrode plate is interposed at least on the first main electrode side between the main electrode plate and a side surface of the semiconductor element,
A flat type in which an outer peripheral portion of the first main electrode surface of the semiconductor element not facing the intermediate electrode plate and at least a part of a side surface of the intermediate electrode plate interposed on the first main electrode side are sealed with an electrically insulating material. A power converter using a semiconductor device as a main conversion element. 14. A flat package wherein a pair of main electrode plates exposed on both sides are externally insulated by an insulating outer cylinder.
A semiconductor device incorporating at least one or more semiconductor elements having at least a first main electrode on a first main surface and a second main electrode on a second main surface, comprising two main electrodes of the semiconductor element and A separate intermediate electrode plate for each of the semiconductor elements is interposed between the main electrode plate and the side opposite to the main electrode plate, and the outer periphery of the first main electrode surface of the semiconductor element which is not opposed to the intermediate electrode plate. A power converter using a flat semiconductor device in which a portion and at least a part of a side surface of an intermediate electrode plate interposed on a second main electrode side are sealed with an electrically insulating material as a main conversion element.