JP2000058670A - Input/output protection device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a current from concentrating to a contact hole and a field edge, when a bipolar operation current is drawn out. SOLUTION: An N+ diffused layer 22, which is to be a drain, is covered with an N-type well 52, while an N+ diffused layer 23 which is to be a source is covered with an N-type well 2. Covering the N+ diffused layer 23 with the N-type well 2 allows the N-type well 2 to operate as a resistor, so that a current is prevented from concentrating at a part 56 immediately below a contact hole 31 and a field edge 55, when a bipolar operation current 7 caused by a parasitic bipolar transistor is pulled out.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output protection device, and more particularly to a complementary metal-oxide semiconductor (CMOS).
The present invention relates to an input / output protection device for protecting an integrated circuit (al-oxide semiconductor) from electrostatic discharge (hereinafter referred to as ESD).

[0002]

2. Description of the Related Art Input / output protection devices for protecting integrated circuits from ESD are known. In recent years, a semiconductor element used as an input / output protection device has been required to receive a voltage higher than an internal operating voltage as an input / output.

[0003] When such a semiconductor element receives a voltage higher than the internal operating voltage from the outside, one of the important issues is how to protect the semiconductor element.

[0004] The protection can be achieved by forming the gate oxide film of the element thicker than before.

For example, by forming a thick gate oxide film, the internal operating voltage is 3.3 V and the external operating voltage is 5.0 V.
The element is not destroyed even when the signal is input.

A conventional input / output protection device using such a thick gate oxide film will be described below.

FIG. 6 is a circuit diagram of an example of a conventional protection device, FIG. 7 is a sectional view of the device, and FIG. 8 is a plan view (including a perspective view) of the device. 8 is a sectional view taken along line AA ′ of FIG.
It is.

Referring to FIG. 6, a conventional protection device 11 is configured by connecting, for example, NMOSFETs 12 and 13 in series.

The source of the FET 12 is connected to a power line (V
DD) 14, and the source of the FET 13 is connected to a ground line (GND) 15. On the other hand, the drain of the FET 12 and the drain of the FET 13 are commonly connected, and the input terminal 16 is connected to the common connection point together with the gates of the FETs 12 and 13.

FIG. 6 also shows a device to be protected (hereinafter referred to as an internal circuit) 101 which is protected by the protection device 11 for convenience.

The internal circuit 101 is, for example, a CMOS.
It is configured by an integrated circuit 102, and is configured such that a signal input from the input terminal 16 is input to the CMOS integrated circuit 102 via a voltage conversion circuit (hereinafter, referred to as a level shifter) 103.

For example, VDD is 3.3 V, and therefore, the CMOS integrated circuit 102 operates at 3.3 V. When a 5.0 V signal is input from the input terminal 16, the level shifter 103 sets 5.0 V. 0V is converted to 3.3V and supplied to the CMOS integrated circuit 102.

The NMOSFET 12 of the protection device 11
Reference numeral 13 denotes a thick gate oxide film MO in which a field oxide film is used as a gate oxide film and the gate oxide film is formed thicker than before.
It is composed of SFET.

FIG. 7 shows the structure of the NMOSFET 13. In the structure of the NMOSFET 12, the drain and the source are exchanged, and the power supply line (VDD) and the ground line (GN
If D) is replaced, the structure will be the same as that of the NMOSFET 13, so illustration and description are omitted.

Referring to FIG. 7, protection device 11 includes a P-type silicon substrate 21 and a diffusion layer 22 formed on substrate 21.
To 24, field oxide films 25 to 28, and diffusion layer 22
An insulating interlayer film 29 formed in the field oxide films 25 to 28; contact holes 30 to 32 penetrating the insulating interlayer film 29 and electrically connected to the diffusion layers 22 to 24, respectively; 30 to 32 are electrically connected to metal wirings 33 to 35, respectively.

The field oxide films 25 to 28 and the insulating interlayer film 29 constitute a gate oxide film.

As shown in FIG. 7, by forming this gate oxide film thicker than before, it is possible to withstand a voltage higher than the internal operating voltage.

For example, when VDD is 3.3 V and it is necessary to receive 5.0 V as an input voltage, this 5.0 V
It is possible to increase the thickness of the gate oxide film so that the element is not destroyed even when the input is made. The gate oxide film shown in FIG.

Here, the diffusion layer 22 is
, The diffusion layer 23 constitutes a source, and the metal wiring 33 constitutes a gate. The metal wirings 34 and 35 are connected to VSS
(Ground potential), the metal wires 33 are connected to the input terminals 16 respectively.

In FIG. 8, the same components as those in FIG. 7 are denoted by the same reference numerals. Also, in FIG.
Although portions other than 35 and the insulating interlayer film 29 are displayed in a transparent manner, they are indicated by solid lines for convenience.

FIG. 9 is an equivalent circuit diagram of the protection circuit 11.
As shown in FIG.
This is equivalent to a serial connection of P.I.

The diffusion layer 22 corresponds to the collector of the NPN transistor 42, the diffusion layer 23 corresponds to the emitter, and the P-type silicon substrate 21 corresponds to the base.

This thick gate oxide film MOSFET 12,1
According to the protection device 11 using the NPN transistor 3, when high-voltage static electricity is applied to the drain portion, the parasitic NPN transistor (NP
The N-transistors 41 and 42) operate to release electric charges and protect the internal circuit 101.

More specifically, referring to FIG. 7, a bipolar operation current 36 flows from diffusion layer 22 to diffusion layer 23,
This current 36 protects the internal circuit 101. In addition,
A technique similar to this conventional technique is disclosed in Japanese Patent Application Laid-Open No. 3-76153.

However, recent LSIs (Large Sc)
The tendency of the integrated circuit is that the diffusion layer is becoming shallower, and when the parasitic NPN transistor is turned on, current paths concentrate on the edge 37 of the diffusion layer 22 and directly below the contact 38, causing thermal destruction. There was a disadvantage.

Therefore, another protection device for solving this drawback has been disclosed. FIG. 10 is a sectional view of another conventional protection device, and FIG. 11 is a plan view (including a perspective view) of the protection device. FIG. 10 is a sectional view taken along the line BB ′ of FIG.

In FIGS. 10 and 11, the same components as those in the above-described example (FIGS. 7 and 8) are denoted by the same reference numerals, and description thereof will be omitted. Also, the circuit diagram of the protection device and the internal circuit is the same as that of FIG.

The structure of the protection device will be described. Referring to FIG. 10, another conventional protection device 51 is different from protection device 11 described above in that an N-type well (well) 52 is provided.
Is added.

That is, a protective MO using a thick gate oxide film
In contrast to the SFET configuration, the protection device 51 includes a drain portion of the protection element (that is, the diffusion layer 22) in the N-type well 52.
It is structured to cover with.

When a high voltage static electricity is applied to the drain portion, the protection device 51 operates a parasitic NPN transistor to release charges and protect the internal circuit 101.

If there is no conventional N-type well, as described above, there is a disadvantage that when the parasitic NPN transistor is turned ON, current paths are concentrated on the edge 37 of the diffusion layer 22 and directly below the contact 38 and are destroyed. However, according to the protection device 51, the current path is dispersed by adding the N-type well 52.
ET12, 13) are protected.

Next, the protection device 51 will be described in detail.
FIG. 12 is an equivalent circuit diagram of the protection device 51. The same components as those in the equivalent circuit diagram of FIG.
The description is omitted.

The difference between the equivalent circuit diagram of FIG. 12 and the equivalent circuit diagram of FIG. 9 is that drain-side well resistances 53 and 54 are connected between the collectors and bases of the transistors 41 and 42.

Referring to FIG. 6, an input terminal 16 connected to the outside has a thick gate oxide film N as an ESD protection element.
MOSFETs 12 and 13 are formed. When very high voltage static electricity is applied to the input terminal 16 with respect to the ground line 15, for example, the thick gate oxide film NMOSFET 13 used for protection is turned on to release electric charges to the ground line 15, and the internal circuit 101 It is configured to be protected.

Next, this thick gate oxide film NMOSFET 1
The configuration and operation of the devices 2 and 13 will be described with reference to FIG.

The N + diffusion layer 22 on the drain side is completely covered with an N-type well 52.

The operation of this protection element is the same as that of a bipolar transistor using the N-type well 52 covering the N + diffusion layer 22 as a collector, the N + diffusion layer 23 as an emitter, and the P-type silicon substrate 21 as a base.

That is, when a voltage higher than the junction breakdown voltage between the N-type well 52 covering the N + diffusion layer 22 and the P-type silicon substrate 21 is applied to the N + diffusion layer 22, avalanche destruction occurs and the hole substrate is damaged. An electric current 61 flows through the substrate resistance 62 to the P + diffusion layer 24 having a substrate contact, thereby increasing the potential near the N + diffusion layer 23 equivalent to the emitter, thereby causing the electron flow 63 from the N + diffusion layer 23 to rise. Is injected, and the electron flow 63 flows toward the N-type well 52 covering the N + diffusion layer 22 equivalent to the collector.

This electron flow 63 is applied to the N + diffusion layer 22
Is accelerated by a high electric field during bonding between the N-type well 52 covering the P-type silicon substrate 21 and the P-type silicon substrate 21 to cause collision ionization,
Further, a positive feedback that the hole substrate current 61 is increased occurs.

The operation current 64 generated by the parasitic bipolar transistor allows the charge to be released even if a large charge is input.
1 can be protected from damage.

Next, the reason why the N-type well 52 is added to the above configuration will be described. According to the present protection device 51, the N-type well 52 enters the N-type well 52.
Operate as a resistor, so that when the parasitic NPN transistor is turned on, the current path does not concentrate on the portion 38 directly below the contact or on the edge 37 of the diffusion layer 22.

For this reason, the protection element (NMOSFET 1
2, 13) operate stably, and the desired ES
D tolerance is obtained.

An example of this type of protection device is disclosed in
No. 0-4144 (hereinafter referred to as Document 1). This includes a silicon substrate, a well layer formed on the silicon substrate, and first and second layers formed on the well layer.
A diffusion region, third and fourth diffusion regions formed on the silicon substrate outside the well layer, and a gate covering the silicon substrate between the third diffusion region and the well layer; A CMOS transistor is formed by combining the diffusion regions, and a parasitic silicon controlled rectifier is formed.

Another example of this kind of protection device is disclosed in
Japanese Patent Application Laid-Open No. 34967/1994 and Japanese Patent Application Laid-Open No. 6-125040 (hereinafter referred to as Documents 2 and 3).

[0045]

However, the above-described protection device 51 has a bipolar operation current 64 with reference to FIG.
The current 64 is concentrated on the contact hole 31 and the field edge 55 at the time of extracting the protection element (NM).
There is a disadvantage that the OSFETs 12, 13) are easily broken. On the other hand, means for solving this drawback is not disclosed in the above-mentioned documents 1 to 3.

Accordingly, an object of the present invention is to provide an input / output protection device which can prevent a current from concentrating on a contact hole or a field edge when extracting a bipolar operation current.

[0047]

According to the present invention, there is provided an input / output protection device provided on an input or output terminal side of a protected circuit, wherein the input / output protection device includes a silicon substrate; A first well layer formed on the silicon substrate, a first diffusion layer formed on the first well layer, and a second well formed on the silicon substrate outside the first well layer A second diffusion layer formed in the second well layer; and a second diffusion layer formed in the silicon substrate outside the second well layer, the first well layer being formed from the first well layer more than the second well layer. And a third diffusion layer disposed at a distant position.

According to the present invention, by covering the first diffusion layer with the first well layer, the protection element can be operated without breaking the drain, and at the same time, the second diffusion layer is covered with the second well layer. By covering with a well layer, it is possible to prevent current from concentrating on a contact hole or a field edge when extracting a bipolar operation current. This can prevent the protection element from being destroyed.

[0049]

Embodiments of the present invention will be described below with reference to the accompanying drawings. First, a first embodiment will be described. FIG. 1 is a sectional view of a first embodiment of an input / output protection device according to the present invention, and FIG. 2 is a plan view (including a perspective view) of the device. In addition, CC ′ of FIG.
FIG. 1 is a sectional view.

In FIGS. 1 and 2, the same components as those in the above-described example (FIGS. 10 and 11) are denoted by the same reference numerals, and the description thereof will be omitted. Also, the circuit diagram of the protection device and the internal circuit is the same as that of FIG.

First, the overall configuration will be described in detail again. The overall circuit diagram is similar to that of FIG.
The internal configuration of T12 and T13 is different from the conventional one.

Referring to FIG. 6, a protection circuit 11 is connected to an input side of an internal circuit 101 which is a circuit to be protected.

The protection circuit 11 has a power supply voltage VD
When D is 3.3 V, the device is configured by an element that needs to receive an input voltage of 5.0 V. To satisfy this requirement, the gate oxide film is configured to be thick as described in the conventional example.

Now, at the input terminal 16 of the protection circuit 11, 5.
When a 0V signal is input, the NMOSFE
T13 does not turn on. Therefore, the 5.0 V signal passes through the NMOSFETs 12 and 13 and passes through the level shifter 10.
3 is input.

The level shifter 103 receives the input 5.0 V
Is converted to a 3.3V signal and the CMOSFET 10
Enter 2

The CMOSFET 102 performs a normal operation by the input 3.3 V signal.

On the other hand, 5.
When static electricity at a voltage much higher than 0 V is applied,
The NMOSFET 13 turns on.

Therefore, the charge due to the static electricity is the NMOSFE
It escapes to the ground line 24 via the drain and source of T13.

Thus, the internal circuit 101 is protected from static electricity.

Next, the protection circuit 11 will be described. Referring to FIG. 1, the input / output protection device 1 is a conventional protection device 5.
1 (see FIG. 10) is that an N-type well 2 is added.

Although the input terminal 16 is shown as an example in FIG. 6, the present invention is not limited to this, and the present invention can be applied even if the terminal 16 is an output terminal.

The input / output protection device 1 is a conventional protection device 5
1 is characterized in that the entire N + diffusion layer 23 on the source side is covered with an N-type well 2.

Next, the operation and functional features of the input / output protection device 1 will be described in detail. FIG. 3 is an equivalent circuit diagram of the protection device 1. The same components as those in the equivalent circuit diagram of FIG. 12 are denoted by the same reference numerals, and description thereof will be omitted.

The difference between the equivalent circuit of FIG. 3 and the equivalent circuit of FIG. 12 is that the source side well resistors 4 and 5 are connected between the emitter of the transistor 41 and the power supply VDD and between the emitter of the transistor 42 and the ground. .

Referring to FIG. 1, the operation of the protection element of the present input / output protection device 1 is based on N-type well 5 covering N + diffusion layer 22.
2 is a collector, the N-type well 2 covering the N + diffusion layer 23 is an emitter, and the same operation as the bipolar transistor based on the P-type silicon substrate 21 is performed.

That is, N covering the N + diffusion layer 22
When a voltage higher than the junction withstand voltage between the mold well 52 and the P-type silicon substrate 21 is applied to the N + diffusion layer 22, avalanche destruction occurs, and the hole substrate current 61 becomes the substrate resistance 62.
Flow through the P + diffusion layer 24 having a substrate contact through the N + diffusion layer 24, thereby increasing the potential near the N + diffusion layer 23 equivalent to the emitter. Is implanted to cover the N + diffusion layer 22 equivalent to the collector.
Flows towards

The electron flow 6 is accelerated by a high electric field during the junction between the N-type well 52 covering the N + diffusion layer 22 and the P-type silicon substrate 21 to cause collision ionization, and further increases the hole substrate current 61. Positive feedback occurs.

The operating current 7 generated by the parasitic bipolar transistor allows the electric charge to escape even when a large electric charge enters the input, thereby preventing the internal circuit 101 from being destroyed.

On the other hand, since the N + diffusion layer 23 on the source side is covered with the N-type well 2, the operation as the resistance of the N-type well 2 causes the portion 56 immediately below the contact hole 31 and the field edge 55 when the bipolar operation current 7 is extracted. Current can be prevented from being concentrated on the substrate.

Next, a second embodiment of the present invention will be described. Referring to FIG. 1, if the entire N + diffusion layer 23 is covered with the N-type well 2 as in the first embodiment, the efficiency of injection of the electron flow 6 is reduced. Has a drawback in that the effect of pulling out the protective element is reduced and the resistance of the protection element is reduced. The second embodiment aims at eliminating this drawback.

FIG. 4 shows a second embodiment of the input / output protection device according to the present invention.
FIG. 5 is a plan view (including a perspective view) of the device. FIG. 4 is a sectional view taken along line DD ′ of FIG.
It is.

In FIGS. 4 and 5, the same components as those in the above-described example (FIGS. 1 and 2) are denoted by the same reference numerals, and description thereof will be omitted. Also, the circuit diagram of the protection device and the internal circuit is the same as that of FIG.

Referring to FIG. 4, the input / output protection device 8 differs from protection device 1 (see FIG. 1) in that the size of N-type well 2 is changed so that a part of N + diffusion layer 23 is exposed. It is a point that has been reduced. This N-type well is indicated by 2 '.

More specifically, the field edge 55 on the side of the source-side N + diffusion layer 23 facing the drain and the contact hole 31 are covered with the N-type well 2 ', and a part of the source-side N + diffusion layer 23 is formed. Is characterized in that it is exposed.

Referring to FIG. 5, the portion where N + diffusion layer 23 is exposed is substantially the left half of N + diffusion layer 23 excluding contact hole 31.

Next, the operation and functional characteristics of the protection device 8 will be described in detail. The equivalent circuit of the protection device 8 is the protection device 1
Is omitted since it is the same as the equivalent circuit (FIG. 3).

Referring to FIG. 4, the operation of the protection element of input / output protection device 8 is based on N-type well 5 covering N + diffusion layer 22.
2 is the collector, the N + diffusion layer 23 and the N-type well 2 'partially covering the N + diffusion layer 23 are the emitter, and the same operation as the bipolar transistor based on the P-type silicon substrate 21 is performed.

That is, the N covering the N + diffusion layer 22
When a voltage higher than the junction withstand voltage between the mold well 52 and the P-type silicon substrate 21 is applied to the N + diffusion layer 22, avalanche destruction occurs, and the hole substrate current 61 becomes the substrate resistance 62.
Flows through the P + diffusion layer 24 which is in contact with the substrate through the N + diffusion layer 23, thereby increasing the potential of the N + diffusion layer 23 equivalent to the emitter and the potential near the N-type well 2 'partially covering the N + diffusion layer 23. The electron flow 9 is injected from the N-type well 2 ′ partially covering the diffusion layer 23 and the N + diffusion layer 23, and flows toward the N-type well 52 covering the N + diffusion layer 22 equivalent to a collector.

This electron flow 9 is accelerated by a high electric field during the junction between the N-type well 52 covering the N + diffusion layer 22 and the P-type silicon substrate 21 to cause impact ionization, and further increases the hole substrate current 61. Positive feedback occurs.

The operation current 10 by the parasitic bipolar transistor allows the electric charge to escape even if a large electric charge enters the input.
Can be prevented from being destroyed.

On the other hand, since the N + diffusion layer 23 which is a high-concentration layer is partially exposed, the efficiency of injection of the electron flow 9 is hardly reduced, and the bipolar operation current 10 is reduced to the bipolar operation current 64 of the conventional protection device 51. And almost the same.

Therefore, it is possible to solve the drawback of the first embodiment in which the effect of extracting the electric charge is reduced and the resistance of the protection element is reduced.

Further, comparing the forward rise voltage between the case where the N-type well 2 ′ and the P-type silicon substrate 21 are joined and the case where the N + diffusion layer 23 and the P-type silicon substrate 21 are joined together, Well 2 'and P-type silicon substrate 2
1, the rising voltage is lower. First, the electron flow 9 flows from the N-type well 2 'that partially covers the N + diffusion layer 23, and then the electron flow 9 flows from the N + diffusion layer 23 to the N-type. It will flow toward the well 52.

This means that the next bipolar operation start time will be earlier than in the case of the electron flow 9 only from the N + diffusion layer 23 (see the conventional protection device 51 of FIG. 10), whereby the start-up time will be increased. It is possible to react as a protection element even to a rapid surge.

[0085]

According to the present invention, there is provided an input / output protection device provided on an input or output terminal side of a circuit to be protected, wherein the input / output protection device is a silicon substrate and a first substrate formed on the silicon substrate. A first well layer, a first diffusion layer formed in the first well layer, a second well layer formed in the silicon substrate outside the first well layer, and a second well layer A second diffusion layer formed on the silicon substrate outside the second well layer;
And the third diffusion layer disposed farther from the first well layer than the first well layer. Therefore, the current concentrates on the contact hole and the field edge when extracting the bipolar operation current. Can be prevented. Thereby, the destruction of the protection element can be prevented.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a first embodiment of an input / output protection device according to the present invention.

FIG. 2 is a plan view (including a perspective view) of the apparatus.

FIG. 3 is an equivalent circuit diagram of the device.

FIG. 4 is a sectional view of a second embodiment of the device.

FIG. 5 is a plan view (including a perspective view) of the apparatus.

FIG. 6 is a circuit diagram of an example of a conventional protection device.

FIG. 7 is a sectional view of the same device.

FIG. 8 is a plan view (including a perspective view) of the device.

FIG. 9 is an equivalent circuit of the protection circuit 11.

10 is a sectional view of the protection device 51. FIG.

11 is a plan view (including a perspective view) of the protection device 51. FIG.

FIG. 12 is an equivalent circuit diagram of the protection device 51.

[Explanation of symbols]

 1,8 Input / output protection device 2,2 ', 52 N-type well 12,13 NMOS FEET 21 P-type silicon substrate 22-24 Diffusion layer 25-28 Field oxide film 29 Insulating interlayer film 30-32 Contact hole 33-35 Metal wiring

Claims (14)

[Claims] An input / output protection device provided on an input or output terminal side of a protected circuit, comprising: a silicon substrate; a first well layer formed on the silicon substrate; A first diffusion layer formed, a second well layer formed on the silicon substrate outside the first well layer, a second diffusion layer formed on the second well layer, A third diffusion layer formed on the silicon substrate outside the second well layer, the third diffusion layer being located farther from the first well layer than the second well layer. Output protection device. 2. The method according to claim 1, wherein the first substrate is formed on the silicon substrate.
A first and a second field oxide film sandwiching the diffusion layer; a third field oxide film formed on the silicon substrate and sandwiching the second diffusion layer with the second field oxide film; A fourth field oxide film formed on the silicon substrate and sandwiching the third diffusion layer with the third field oxide film; an insulating interlayer film covering the first to fourth field oxide films; First to third contact holes penetrating an insulating interlayer film and electrically connected to the first to third diffusion layers, respectively;
The first electrically connected to each of the third contact holes
2. The input / output protection device according to claim 1, further comprising: a third metal wiring. 3. The first diffusion layer is entirely covered by the first well layer, and the second diffusion layer is entirely covered by the second well layer. The input / output protection device according to claim 1, wherein the input / output protection device is provided. 4. The first diffusion layer is entirely covered by the first well layer, and the second diffusion layer is partially covered by the second well layer. The input / output protection device according to claim 1, wherein the input / output protection device is covered. 5. The second diffusion layer extends from a field edge of the second diffusion layer facing the first diffusion layer to a portion where the second contact hole is electrically connected.
The input / output protection device according to claim 4, wherein the input / output protection device is covered with the well layer. 6. The input / output protection device according to claim 1, wherein the silicon substrate is a one conductivity type silicon substrate. 7. The first and second well layers and the first and second diffusion layers are opposite conductivity type well layers, and the third diffusion layer is the one conductivity type diffusion layer. The input / output protection device according to claim 6, wherein: 8. The semiconductor device according to claim 2, wherein said first to fourth field oxide films are used as gate oxide films.
The input / output protection device according to any one of claims 1 to 7. 9. The input / output protection device according to claim 2, wherein a power supply voltage is applied to said first metal wiring, and said second and third metal wirings are grounded. . 10. A thick gate oxide NMOSFET having a drain as the first diffusion layer, a source as the second diffusion layer, and a gate as the first metal wiring. 10. The input / output protection device according to any one of claims 9 to 9. 11. A first thick gate oxide film NMOS comprising two thick gate oxide film NMOSFETs connected in series.
The power supply voltage is applied to the source of the FET, the drain is connected to the input or output terminal, and the drain of the second thick gate oxide NMOSFET is commonly connected to the drain of the first thick gate oxide NMOSFET; 11. The input / output protection device according to claim 10, wherein a source is grounded, and gates of said first and second thick gate oxide NMOSFETs are commonly connected to respective drains. 12. The input / output protection device according to claim 1, wherein said silicon substrate is a P-type silicon substrate. 13. The input / output protection device according to claim 1, wherein said protected circuit is a CMOS integrated circuit. 14. The input / output protection device according to claim 13, wherein voltage conversion means is provided between said CMOS integrated circuit and said input / output protection device.