JP2000058663A - Integrated bias circuit element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable integrating and forming an FET while maintaining characteristic of an HBT, by using a crystal growth substrate which is laminated and formed for the HBT (hetero bipolar transistor) and using a part of a layer of the crystal growth layer as a channel layer of the FET. SOLUTION: By using a crystal growth substrate which is laminated and formed for an HBT, etching is performed from the upper surface of the crystal growth layer as far as a GaAs collector layer 9 is exposed. An insulating region 24 is formed in a GaAs base layer 8 and a GaAs contact layer 10 so as to reach an undoped GaAs buffer layer 11 by using ion implantation, and an HBT region and an FET region are electrically insulated and isolated. A channel layer of the FET region is formed by using any one out of an AlGaAs emitter layer 7, the GaAs collector layer 9 and the GaAs contact layer 10 in the crystal growth layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bias circuit device, and more particularly to an integrated bias circuit device in which a hetero bipolar transistor and a field effect transistor are formed on the same substrate.

[0002]

2. Description of the Related Art As shown in FIG. 8, a bias circuit used in a cellular phone or the like is an AlGaAs / GaAs heterobipolar transistor (hereinafter referred to as "HBT") T.
r1 and Tr2 are formed by connecting them in two stages.
Since Tr2 and Tr2 have the same crystal structure, they can be formed as integrated circuits on the same substrate. In such a bias circuit, the threshold voltage of each of the transistors Tr1 and Tr2 is about 1.35 V determined by the band gap of AlGaAs / GaAs, so that the control voltage Vpc is at least 2.7 V (1.35 V ×
The voltage of 2) was required. On the other hand, a power supply voltage of 3 V is becoming standard as a power supply for mobile phones and the like.
When a power supply voltage of 3 V is used as Vpc, it becomes difficult to supply a voltage of 2.7 V or more to Vpc when the battery is consumed and the voltage decreases, and the output voltage Vout
However, there is a problem that the temperature is reduced.

On the other hand, the present inventors, as Tr,
By using a field effect transistor (hereinafter referred to as "FET") capable of controlling the threshold voltage low instead of the HBT, the required control voltage Vpc can be sufficiently reduced with respect to the power supply voltage of 3V. It was proposed that it would be possible.

[0004]

The HBT and the FET are:
Because of the different crystal structures, it was not possible to form an integrated circuit on the same substrate, and it was necessary to manufacture it as a separate element and incorporate it into the circuit. For this reason, the size of the circuit cannot be reduced, and it has been particularly difficult to use it for a circuit element of a mobile phone in which reduction in size and weight is essential. Therefore, the present invention
It is an object of the present invention to provide a bias circuit element in which an HBT and an FET are integrally formed on the same substrate.

[0005]

The inventors of the present invention have conducted intensive studies and have found that a crystal growth substrate laminated for HBT is used and a part of the crystal growth layer is used as a channel layer of an FET. As a result, it has been found that FETs can be integratedly formed while maintaining the characteristics of the HBT, and the present invention has been completed.

That is, the present invention relates to a bias circuit element in which a hetero-bipolar transistor and a field-effect transistor are integrated on a GaAs substrate, wherein the hetero-bipolar transistor is composed of at least the GaAs.
a GaAs buffer layer formed on an s substrate;
a GaAs collector contact layer formed on the s buffer layer, a GaAs collector layer formed on the GaAs collector contact layer, a GaAs base layer formed on the GaAs collector layer, and formed on the GaAs base layer AlGaAs emitter layer and the AlGaAs
A field effect transistor formed of a crystal growth layer including an InGaAs emitter contact layer formed on the emitter layer, wherein the field effect transistor is insulated from a part of the crystal growth layer electrically insulated from the hetero bipolar transistor. An integrated bias circuit element, wherein any one of the AlGaAs emitter layer, the GaAs collector layer, and the GaAs collector contact layer in the crystal growth layer is formed as a channel layer. HB
Since T and FET have different element structures, it has been difficult to integrate them on the same substrate. However, as in the present invention, the emitter layer and the like constituting the HBT are used as the channel layer of the FET. Thereby, the HBT and the FET can be formed on the same substrate. As a result, the size and weight of the bias circuit element can be reduced.

[0007] The field-effect transistor is composed of the AlG
The AlGa in the recess provided in the InGaAs emitter contact layer so that the aAs emitter layer is exposed.
A gate electrode formed on the surface of the As emitter layer; and a source electrode and a drain electrode formed on the InGaAs emitter contact layer on both sides of the gate electrode, wherein the AlGaAs emitter layer serves as a channel layer. A characteristic integrated type bias circuit element may be used.
In this way, by using the emitter layer of the HBT as the channel layer of the FET, an integrated bias circuit element can be formed.

The GaAs collector contact layer is provided between the GaAs buffer layer and the GaAs buffer layer.
A crystal growth layer that includes a collector contact layer and is electrically insulated from the heterobipolar transistor;
The aAs collector contact layer is removed so as to be exposed.
The GaAs is exposed so that the As collector contact layer is exposed.
a gate electrode formed on the surface of the channel GaAs collector contact layer in a recess provided in the s collector contact layer;
The integrated bias circuit element may include a source electrode and a drain electrode formed on the As collector contact layer, and the channel GaAs collector contact layer may be used as a channel layer. Thus, HBT
By using the collector contact layer as the channel layer of the FET, an integrated bias circuit element can be formed. In particular, in such a structure, G having a relatively high electron mobility is used.
Since the aAs layer can be used as a channel layer, the FET can operate at high speed.

The GaAs collector contact layer further includes a channel GaAs between the channel GaAs collector contact layer and the GaAs buffer layer.
The integrated bias circuit element may include a GaAs buried layer of a conductivity type opposite to that of the collector contact layer. By providing such a buried layer, the parasitic capacitance can be reduced and high-speed operation can be performed.

[0010] The GaAs collector layer is formed of the GaAs.
A GaAs buried layer having a conductivity type opposite to that of the GaAs collector layer and a GaAs collector layer for a channel having a higher carrier concentration than the GaAs collector layer, and are electrically insulated from the hetero bipolar transistor; The grown crystal growth layer is removed so that the channel GaAs collector layer is exposed, and the field-effect transistor includes a gate electrode formed on the channel GaAs collector layer and the gate electrode on both sides of the gate electrode. An integrated bias circuit element including a source electrode and a drain electrode formed on a GaAs collector layer for a channel and using the GaAs collector layer for a channel as a channel layer may be used. In such a structure, the channel layer can be formed from a GaAs layer and the FE
Since the amount of etching for forming T is small, the surface of the bias circuit element can be flattened.

The above-mentioned field effect transistor may be a MES type field effect transistor whose gate electrode is made of a metal electrode.

In the above-mentioned field effect transistor, the gate electrode of the field effect transistor has a conductivity type opposite to that of the channel layer.
It may be a junction field effect transistor including an s electrode layer and a metal electrode layer laminated thereon.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 An HBT bias circuit according to a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows an FET according to the present invention.
FIG. 3 is a circuit diagram of a bias circuit composed of a HBT and an HBT.
1 is FET, 2 is HBT, 3 is Vcc (power supply voltage), 4
Is Vpc (power control voltage), 5 is Vout
(Output voltage). FIG. 2 shows an FET portion of the integrated bias circuit element forming the bias circuit of FIG. 1. In FIG. 2, reference numeral 6 denotes a GaAs emitter contact layer;
lGaAs emitter layer, 8 is a GaAs base layer, 9 is G
An aAs collector layer 10 is a GaAs collector contact layer, and 11 is a GaAs buffer layer.

The bias circuit according to the present embodiment is obtained by replacing Tr1 of the conventional bias circuit shown in FIG. 8 with an FET from an HBT. The FET has a low gain at a low frequency of several hundred MHz or less as compared with the HBT, and the input terminal (gate) is capacitive and almost no gate current flows. As compared with the case, it is easier to suppress the oscillation.

By controlling the threshold voltage (Vth) of the FET, Vpc can be set to an arbitrary value. That is, the voltage at point A in FIG. 1 is set to about 1.35 V when the high-output transistor connected to Vout operates in class AB.
Is designed to be near -1.35V, the value of Vpc for obtaining the voltage at the point A is about 0V. As a result, even when the power supply voltage is used as a bias circuit of a mobile phone where the power supply voltage of 3 V is becoming mainstream, a sufficient margin can be obtained as compared with the conventional structure, and sufficient operation can be performed even when the power supply voltage decreases. Can be secured.

Next, FIG. 2 is a sectional view of an element in which an HBT and an FET are integratedly formed on the same substrate using a part of a crystal growth substrate for producing an HBT (a GaAs substrate is omitted).
To manufacture the integrated bias circuit according to the present embodiment,
Basically, a crystal growth substrate on which a crystal is grown to produce an HBT is used. Table 1 shows the structure of such a crystal growth substrate.

[0017]

[Table 1]

In the FET shown in FIG. 2, a part of the crystal growth substrate shown in Table 1 is electrically insulated from the HBT formation region, and the FET is formed in that part. Specifically, the crystal growth layer is etched from the upper surface until the GaAs collector layer 9 is exposed, and the GaAs base layer 9 and the GaAs collector layer 1 are further etched.
0, an insulating region 24 is formed by ion implantation so as to reach the undoped GaAs buffer layer 11;
The T region and the FET region are electrically insulated and separated. Note that it is also possible to perform insulation isolation between elements only by an ion implantation step without using an etching step as in this embodiment.

Subsequently, the InGaAs emitter contact layer 6 is etched to form a recess so that the AlGaAs emitter layer 7 is exposed.

Subsequently, a gate metal electrode 21 of, for example, Ti / Al or the like is formed on the AlGaAs emitter layer 7 in the recess by using the same process as that of a normal FET manufacturing method, and the gate electrode 21 is sandwiched. On the emitter contact layer 6, a source electrode 22 made of, for example, WSi, and a drain electrode 2
3 are formed respectively.

In this structure, the AlGaAs emitter layer 7 and the GaAs base layer 8 form a pn junction,
A depletion layer extends from the junction to the AlGaAs emitter layer 7. Therefore, the AlGaAs emitter layer 7 is used as a channel layer, the GaAs base layer 8 is used as a substitute for the p-type buried layer, and a depletion layer extending just below the gate electrode 21 and a depletion layer extending from the above-described junction to the AlGaAs emitter layer 7. The use of the AlGaAs emitter layer 7 of the HBT as the channel region makes it possible to form an FET using the AlGaAs emitter layer 7 of the HBT.

Finally, the HBT and F which are insulated from each other are
The ET is connected to the ET with, for example, an Al wiring or the like so as to have the circuit configuration shown in FIG. 1, and an integrated bias circuit element integrated on a GaAs substrate can be obtained. In addition, HB
T is formed according to a general manufacturing process.

As described above, by forming an FET using a part of the crystal growth layer used for the HBT, the HBT and the FBT are formed.
It is possible to form an integrated bias circuit in which ET and ET are formed on the same substrate. Therefore, by using such an integrated bias circuit, the circuit structure of FIG. 1 can be formed as an integrated circuit element, and the size and weight of a mobile phone or the like can be reduced.

Embodiment 2 FIG. The integrated bias circuit element according to the second embodiment is formed using the HBT crystal growth layers shown in Table 2.

[0025]

[Table 2]

In the HBT structure according to the present embodiment, the collector contact layer 10 further has a channel collector contact layer 12 between itself and the buffer layer 11 in the HBT structure of the first embodiment. I have. Since the collector contact layer 12 for the channel has the same conductivity type as the collector contact layer 10 and a small thickness, it is considered to be integral with the collector contact layer 10 and does not particularly affect the device characteristics of the HBT.

FIG. 3 is a sectional view of an element in which an HBT and an FET are integratedly formed on the same substrate using a part of a crystal growth substrate for producing an HBT. In the present embodiment, the crystal growth substrate in the FET formation portion is removed by etching until the collector contact layer 10 is exposed, and the insulating region 2 is formed by ion implantation.
4 to electrically insulate the HBT from the FET. Further, a recess is formed in the collector contact layer 10 so that the channel collector contact layer 12 is exposed.

Subsequently, as in the first embodiment, the gate electrode 2 is formed on the channel collector contact layer 12 in the recess.
1 are formed, and a source electrode 22 and a drain electrode 23 are formed on the collector contact layer 10 on both sides thereof, thereby completing an integrated bias circuit element.

In the FET shown in FIG. 3, since the lower portion of the channel collector contact layer 12 is an undoped GaAs layer, the channel collector contact layer 12 can be used as a channel layer of the FET.

As described above, by forming an FET using a part of the crystal growth layer used for the HBT, the HBT and the FBT are formed.
An integrated bias circuit in which the ET and the ET are formed on the same substrate can be formed, and the size and weight can be reduced. In particular, in the FET according to the present embodiment, a GaAs layer having higher electron mobility than the AlGaAs layer can be used as the channel layer, so that the element characteristics of the FET can be improved.

Embodiment 3 In the present embodiment, as shown in Table 3, between the buffer layer 11 and the channel contact layer 12 of the crystal growth substrate used in the second embodiment.
Further, a substrate provided with a p-type buried layer 13 is used.

[0032]

[Table 3]

When the p-type buried layer 13 is provided at such a position, the p-type buried layer 13 substantially
And does not affect the characteristics of the HBT.

On the other hand, the FET is formed by the same steps as in the second embodiment, and has a structure as shown in FIG. In the figure, the same reference numerals as those in FIG. 3 indicate the same or corresponding parts. Thus, by inserting the p-type buried layer 13 below the channel layer, it is possible to reduce the occurrence of parasitic capacitance.

Embodiment 4 FIG. Table 4 shows a crystal growth substrate used in the present embodiment.

[0036]

[Table 4]

In the crystal growth substrate for HBT according to the present embodiment, p
The mold buried layer 13 and the channel collector layer 14 are sequentially laminated. According to the study by the inventors, the p-type buried layer 13 and the channel collector layer 14 as shown in Table 4 were obtained.
It has been found that even when the HBT is provided, the characteristics of the HBT are not substantially affected. Conversely, the p-type buried layer 1
No. 3 is known to be able to maintain high-speed performance of the HBT by suppressing the acceleration of electrons to prevent scattering between valleys.

FIG. 5 is a cross-sectional view of an element in which an HBT and an FET are integratedly formed on the same substrate using a part of a crystal growth substrate for manufacturing an HBT. In the present embodiment, the crystal growth substrate in the FET formation portion is removed by etching until the channel collector layer 14 is exposed, an insulating region 24 is formed by ion implantation, and the HBT and the FET are electrically insulated.
Further, a recess having a predetermined depth is formed in the channel collector layer 14. In some cases, it is not necessary to form such a recess. Subsequently, a gate electrode 21, a source electrode 22, and a drain electrode 23 are formed, and an integrated bias circuit element is completed.

In the FET of FIG. 5, the lower portion of the channel collector layer 14 is the p-type buried layer 13, and the channel collector layer 14 can be used as a channel layer of the FET.

In particular, in the present embodiment, a GaAs layer having a relatively high electron transfer rate can be used for the channel layer, and the FET is formed near the surface.
The surface step due to the etching formation of T becomes small, and the manufacturing process such as mask alignment becomes easy.

As described above, in the first to fourth embodiments, the MES type field effect transistor (MES
FET) has been described as an example, but a junction field effect transistor (Junction FET) is also possible. For example, FIG. 6 shows a cross-sectional view of a FET in the case where the FET of the fourth embodiment is a junction field-effect transistor. In the drawing, the same reference numerals as those in FIG. 5 indicate the same or corresponding portions, and reference numeral 15 denotes a p-GaAs layer.

In the first to fourth embodiments, AlGaAs
Although the integrated bias circuit element of the s / GaAs HBT and the FET has been described, the InGaP / GaAs HB
Application to an integrated bias circuit element using T is also possible. In this case, for example, the AlGaAs emitter layer 7 is
n _0.48 GaP _0.52 layer (3 × 10 ¹⁷ / cm ³ , 1000
You can change it to Å).

Further, the present invention can be applied to an integrated bias circuit device using an InP-based HBT. In this case, AlGa
InP layer or InAlAs instead of As emitter layer 7
A layer is used, and an InGaAs layer or an InP layer is used instead of another GaAs layer.

In the first to fourth embodiments, the integrated bias circuit element for realizing the circuit configuration of FIG. 1 has been described. However, other circuit configurations including an HBT and an FET as shown in FIG. It is possible to apply. In the drawing, the same reference numerals as those in FIG. 1 indicate the same or corresponding parts, and reference numerals 21 and 22 denote H.
BT and 23 indicate resistance. In the circuit configuration of FIG.
Are FETs, and Tr2 and Tr3 are composed of HBTs. For example, resistors may be used instead of Tr2.

[0045]

As is clear from the above description, by using the integrated bias circuit element according to the present invention,
HBTs and FETs having different element structures can be integrated and formed on the same substrate, which makes it possible to reduce the size, weight, and reliability of the element.

In particular, by using the GaAs layer of the HBT as the channel layer of the FET, the FE having excellent high-speed performance can be obtained.
T can be formed.

By inserting a p-type buried layer below the channel layer, the performance of the FET can be improved without substantially changing the device performance of the HBT.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an integrated bias circuit device according to a first embodiment of the present invention.

FIG. 2 is a sectional view of the integrated bias circuit element according to the first embodiment of the present invention;

FIG. 3 is a sectional view of an integrated bias circuit element according to a second embodiment of the present invention;

FIG. 4 is a sectional view of an integrated bias circuit device according to a third embodiment of the present invention;

FIG. 5 is a sectional view of an integrated bias circuit element according to a fourth embodiment of the present invention.

FIG. 6 is a sectional view of an integrated bias circuit device according to a fourth embodiment of the present invention.

FIG. 7 is a circuit diagram of another bias circuit according to the present invention.

FIG. 8 is a circuit diagram of a conventional bias circuit.

[Explanation of symbols]

1 FET, 2 HBT, 3 Vcc, 4 Vpc, 5
Vout, 6 n-InGaAs emitter contact, 7 n-AlGaAs emitter, 8 p-GaAs
Base, 9 n-GaAs collector, 10 n-GaAs
s collector contact, 11 undoped GaAs buffer, 31 collector electrode, 32 base electrode, 33
Emitter electrode.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) H01L 27/095 H03F 3/50 F term (Reference) 5F003 BF06 BG06 BH07 BH12 BJ16 BM02 5F082 AA40 BA47 BA50 BC01 BC20 CA02 DA01 FA11 GA04 5F102 GA12 GB01 GD01 GJ04 GK05 GL05 GM05 GR04 GT01 GT05 5J091 AA01 AA58 CA65 CA92 FA16 FA20 GP02 HA06 HA09 HA18 HA24 HA25 MA21 QA02 SA13

Claims (7)

[Claims] 1. A bias circuit element in which a hetero bipolar transistor and a field effect transistor are integrated on a GaAs substrate, wherein the hetero bipolar transistor is formed on at least a GaAs buffer layer formed on the GaAs substrate. A GaAs collector contact layer formed on the GaAs buffer layer, a GaAs collector layer formed on the GaAs collector contact layer, a GaAs base layer formed on the GaAs collector layer, and a GaAs base layer. An AlGaAs emitter layer formed thereon;
a field-effect transistor is formed on a part of the crystal growth layer electrically insulated from the hetero-bipolar transistor. AlGaAs in the grown crystal growth layer
An emitter layer, the GaAs collector layer, or the GaAs
An integrated bias circuit element, wherein one of the s collector contact layers is formed as a channel layer. 2. The method according to claim 1, wherein said field-effect transistor comprises said Al.
The above InGaAs is formed so that the GaAs emitter layer is exposed.
The AlG in the recess provided in the emitter contact layer
a gate electrode formed on the surface of an aAs emitter layer, and a source electrode and a drain electrode formed on the InGaAs emitter contact layer on both sides of the gate electrode, wherein the AlGaAs emitter layer serves as a channel layer. 2. The integrated bias circuit element according to claim 1, wherein: 3. The GaAs collector contact layer,
GaAs for a channel having a lower carrier concentration than the GaAs collector contact layer between the GaAs buffer layer and the GaAs buffer layer.
a crystal growth layer including an s collector contact layer and being electrically insulated from the hetero bipolar transistor is removed so that the GaAs collector contact layer is exposed;
A gate electrode formed on the surface of the GaAs collector contact layer for the channel in a recess provided in the GaAs collector contact layer so that the collector contact layer is exposed; and the GaAs on both sides of the gate electrode with the gate electrode interposed therebetween.
2. The integrated bias circuit element according to claim 1, further comprising a source electrode and a drain electrode formed on the collector contact layer, wherein the channel GaAs collector contact layer is used as a channel layer. 4. The GaAs collector contact layer,
Further, between the GaAs collector contact layer for channel and the GaAs buffer layer, the GaAs for channel is provided.
4. The integrated bias circuit device according to claim 3, further comprising a GaAs buried layer having a conductivity type opposite to that of the s collector contact layer. 5. The method according to claim 1, wherein the GaAs collector layer is formed of the GaAs.
a GaAs buried layer having a conductivity type opposite to that of the GaAs collector layer and a channel GaAs collector layer having a higher carrier concentration than the GaAs collector layer, and are electrically insulated from the hetero bipolar transistor; The grown crystal growth layer is removed so that the GaAs collector layer for the channel is exposed.
A gate electrode formed on the collector layer; and a source electrode and a drain electrode formed on the GaAs collector layer for the channel on both sides of the gate electrode, and the GaAs collector layer for the channel is used as a channel layer. The integrated bias circuit device according to claim 1, wherein: 6. The integrated bias circuit element according to claim 1, wherein said field effect transistor is a MES type field effect transistor whose gate electrode is formed of a metal electrode. 7. The field-effect transistor, wherein the gate electrode is a junction field-effect transistor comprising a GaAs electrode layer of a conductivity type opposite to the channel layer and a metal electrode layer laminated thereon. The integrated bias circuit device according to claim 1, wherein: