JP2000058660A - Method and device for automatic wiring of semiconductor, and medium where semiconductor automatic wiring program is recorded - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor automatic wiring device which allows reduction in area of a back wiring layer and higher integration of a semiconductor integrated circuit. SOLUTION: A semiconductor automatic wiring device comprises a primitive cell generation part 21 for back wiring at a source region, back wiring at a disconnected drain region, and generating a primitive cell comprising a gate, and a primitive cell allocation part 22 for allocating the primitive cell, while corresponding to a logic circuit. Furthermore, a wiring part 23 for causing wiring for connecting a source region back wiring to a region between back wirings in the disconnected drain region when one of a power source region and a ground region cannot be directly connected to the back wiring of the source region at wiring of the primitive cell, is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to automatic wiring in the layout design of a semiconductor integrated circuit, and more particularly to a semiconductor automatic wiring apparatus, a semiconductor automatic wiring method, and a semiconductor automatic wiring program capable of efficiently supplying power or ground. Related to a medium on which is recorded.

[0002]

2. Description of the Related Art In recent years, the scale of a semiconductor integrated circuit has been increasing with the increase in density and the number of functions, and there has been a growing demand for an improvement in the efficiency of automatic wiring in the layout design of a semiconductor integrated circuit. I have. Generally, when a transistor is formed on a semiconductor substrate, a metal wiring is lined along the diffusion region. This backing wiring layer (Metal
The backing wiring formed in 1) is connected to a source region or a drain region in the transistor region via a contact hole.

A wiring layer (Metal2) for wiring between transistors is provided above the backing wiring layer (Metal1), and a wiring layer (Metal3) for supplying power (ground) is provided thereabove. Can be Backing wiring layer (Metal
Connection between backing wiring of 1) and wiring of wiring layer (Metal2), and wiring of wiring layer (Metal2) and wiring layer (Metal3)
Is connected by through holes.

A conventional semiconductor automatic wiring apparatus has realized automatic wiring by generating a primitive cell shown in FIG. 10 and arranging and wiring the primitive cell. Here, this primitive cell will be described.

As shown in FIG. 10, this primitive cell includes backing lines 101 and 102 in a source (power or ground) region and a backing line 10 in a drain region.
3 are alternately arranged, and between gates 104 and 1
05 is arranged. However, the gates 104 and 105 are connected to the backing wiring 1 in the source region as described later.
01 and 102 and the backing wiring 103 in the drain region are separated by an interlayer insulating film, and are not arranged on the same plane. Further, the backing wirings 101 and 102 in the source region and the backing wiring 10 in the drain region
3 is formed on the same backing wiring layer (Metal1). Note that a diffusion region 106 is disposed below the backing wires 101 to 102 in the source region, the backing wire 103 in the drain region, and the gates 104 to 105.

Further, the primitive cell shown in FIG.
Although the case where the transistors are arranged in one row is shown, when the required driving capability is large, primitive cells corresponding to two or more rows of transistors are generated. FIG. 11 is a diagram showing a primitive cell corresponding to the two rows of transistors. In this primitive cell, lining wires 111, 112 and 113 in the source region and lining wires 114 and 115 in the drain region are alternately arranged, and gates 116 to 119 are arranged therebetween. In addition,
Backing wirings 111 to 113 in the source region, backing wirings 114 to 115 in the drain region, and gates 116 to 11
Below 9, a diffusion region 120 is arranged.

When performing automatic wiring at the time of layout design, the semiconductor automatic wiring device generates and arranges the above-described primitive cells so as to correspond to a logic circuit.
Wiring between each primitive cell is performed. However, the backing wiring of the source region in the primitive cell is changed to the wiring layer (Meta
l3) When connecting to the power supply area or ground area, another wiring passes through the wiring layer (Metal2) between them, and the backing wiring of the source area and the power supply area or ground area of the wiring layer (Metal3) have through holes. May not be able to connect directly via In this case, it is necessary to route wiring for supplying power or ground in the backing wiring layer (Metal1).

FIG. 12 is a diagram showing an example of a wiring in a case where the backing wiring of the source region and the power supply region or the ground region of the wiring layer (Metal3) cannot be directly connected via a through hole. When the primitive cell shown in FIG. 11 is arranged and any of the backing wires 111 to 113 in the source region cannot directly supply power or ground from the wiring layer (Metal3), the gates 116 and 117 are connected as shown in FIG. Wiring to connect, and gates 118 and 119
A wiring 121 connecting the lining wirings 111 to 113 in the source region is generated so as to pass outside of the wiring connecting the wirings 121 and 113.

[0009]

However, as shown in FIG. 12, the wiring 121 connecting the backing wirings 111 to 113 in the source region is generated outside the primitive cell, so that the wiring 121 of the backing wiring layer (Metal1) is formed. The area will increase. Therefore, a semiconductor integrated circuit wired by a conventional semiconductor automatic wiring device has a problem that high integration is difficult.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and a first object of the present invention is to reduce the area of a backing wiring layer and to realize a semiconductor integrated circuit capable of high integration. It is to provide a wiring device.

A second object of the present invention is to provide a semiconductor automatic wiring method capable of reducing the area of a backing wiring layer and enabling high integration of a semiconductor integrated circuit.

A third object of the present invention is to provide a medium on which a semiconductor automatic wiring program is recorded in which the area of a backing wiring layer can be reduced and a semiconductor integrated circuit can be highly integrated.

[0013]

According to a first aspect of the present invention, there is provided a semiconductor automatic wiring apparatus, comprising: a generating means for generating a primitive cell including a backing wiring of a source region, a backing wiring of a divided drain region, and a gate; An arranging means for arranging the primitive cells in correspondence with the logic circuit; and a wiring area for the primitive cells, wherein if one of the power supply area and the ground area cannot be directly connected to the backing wiring of the source area, the divided drain area is provided. And a wiring means for generating a wiring connecting the backing wiring of the source region to a region between the backing wirings.

When one of the power supply region and the ground region cannot be directly connected to the backing wiring of the source region, the wiring means connects the wiring connecting the backing wiring of the source region to a region between the backing wirings of the divided drain region. Since it occurs, the area of the backing wiring layer can be reduced,
It is possible to increase the degree of integration of the semiconductor integrated circuit.

According to a second aspect of the present invention, there is provided a semiconductor automatic wiring device,
2. The semiconductor automatic wiring device according to claim 1, wherein the wiring means generates a wiring connecting the backing wiring of the source region between the backing wirings of the divided drain region, and then generates the wiring between the backing wirings of the separated drain region. The region where the wiring connecting the lining wiring of the source region did not pass through in the region of FIG.

The wiring means generates wiring for connecting the backing wiring of the source region to the region between the backing wirings of the separated drain region, and then backs up the source region in the region between the backing wirings of the separated drain region. Since the area where the wiring connecting the wiring does not pass is used as the backing wiring of the drain region, the backing wiring of the drain region can be enlarged, and the signal line can be stabilized.

According to a third aspect of the present invention, there is provided a semiconductor automatic wiring method comprising:
Generating a primitive cell including a source region lining wiring, a divided drain region lining wiring and a gate, arranging the primitive cells in correspondence with a logic circuit, and wiring the primitive cells. Generating a wiring for connecting the backing wiring of the source region to a region between the backing wirings of the divided drain region when one of the power supply region and the ground region cannot be directly connected to the backing wiring.

When one of the power supply region and the ground region cannot be directly connected to the backing wiring of the source region,
Since the wiring connecting the backing wiring of the source region is generated in the region between the backing wirings of the divided drain region, the area of the backing wiring layer can be reduced, and the integration degree of the semiconductor integrated circuit can be increased. Becomes

According to a fourth aspect of the present invention, there is provided a semiconductor automatic wiring program recorded on a medium, comprising: generating a primitive cell including a source line lining, a divided drain region lining and a gate; The step of arranging in correspondence with the circuit and, when wiring the primitive cells, if either the power supply region or the ground region cannot be directly connected to the backing wiring of the source region, the wiring is applied to the region between the backing wirings of the divided drain region. Generating a wiring connecting the backing wiring of the source region.

When one of the power supply region and the ground region cannot be directly connected to the backing wiring of the source region,
Since the wiring connecting the backing wiring of the source region is generated in the region between the backing wirings of the divided drain region, the area of the backing wiring layer can be reduced, and the integration degree of the semiconductor integrated circuit can be increased. Becomes

[0021]

FIG. 1 is a diagram showing an example of the appearance of a semiconductor automatic wiring device according to the present invention. Semiconductor automatic wiring equipment
Computer body 1, graphic display device 2, magnetic tape device 3 on which magnetic tape 4 is mounted, keyboard 5, mouse 6, CD-ROM (Compact Disc-Rea
d Only Memory) 8 CD-ROM device 7
And a communication modem 9. The semiconductor automatic wiring program is supplied by a storage medium such as the magnetic tape 4 or the CD-ROM 8. The semiconductor automatic wiring program is executed by the computer main body 1, and the operator operates the keyboard 5 or the mouse 6 while watching the graphic display device 2 to perform automatic semiconductor wiring.
Further, the semiconductor automatic wiring program may be supplied to the computer main body 1 from another computer via a communication line and a communication modem 9.

FIG. 2 is a block diagram showing a configuration example of a semiconductor automatic wiring apparatus according to the present invention. 1 includes a CPU (Central Processing Unit) 10;
ROM (Read Only Memory) 11, RAM (Random Acces
s Memory) 12 and a hard disk 13. CP
The U10 performs processing while inputting / outputting data to / from the graphic display device 2, magnetic tape device 3, keyboard 5, mouse 6, CD-ROM device 7, communication modem 9, ROM 11, RAM 12, or hard disk 13. The semiconductor automatic wiring program recorded on the magnetic tape 4 or the CD-ROM 8 is temporarily stored in the hard disk 13 by the CPU 10 via the magnetic tape device 3 or the CD-ROM device 7. The CPU 10 reads the semiconductor automatic wiring program from the hard disk 13
Then, the semiconductor device is automatically wired by loading it into the memory 12 and executing it.

FIG. 3 is a block diagram for explaining a schematic configuration of the semiconductor automatic wiring device according to the embodiment of the present invention. The semiconductor automatic wiring apparatus includes a primitive cell generator 21 for generating primitive cells, a primitive cell generator 22 for arranging primitive cells generated by the primitive cell generator 21 so as to correspond to a logic circuit, and a primitive cell generator. 22 includes a wiring section 23 for performing wiring between the primitive cells arranged by 22.

FIG. 4 is a flow chart for explaining a processing procedure of the semiconductor automatic wiring apparatus according to the present embodiment. First, the primitive cell generation unit 21 generates a primitive cell in which the backing wiring of the drain region is divided (S1). FIG. 5 shows an example of a primitive cell generated by the primitive cell generator 21. As shown in FIG. 5, lining wires 31 and 32 in a source (power or ground) region and lining wires 33 and 34 in a divided drain region are arranged.
Gates 35 and 36 are arranged between them.

The primitive cell shown in FIG. 5 shows a case where the transistors are arranged in one row. However, when the required driving capability is large, primitive cells corresponding to two or more rows of transistors are generated. FIG. 6 is a diagram showing a primitive cell corresponding to the two rows of transistors. In this primitive cell, lining wires 41, 42 and 43 in the source region and lining wires 44 to 47 in the divided drain region are arranged, and the gate 4
8 to 51 are arranged. The diffusion region 52 is arranged below the lining wires 41 to 43 in the source region, the lining wires 44 to 47 in the divided drain region, and the gates 48 to 51.

Next, the primitive cell arranging section 22 arranges the primitive cells so as to correspond to the logic circuit (S2). Then, the backing wiring layer (Metal
It is determined whether or not there is an area reduction priority designation in 1) (S3).

In the case where the user designates the priority of the area reduction of the backing wiring layer (Metal1) (S3, Yes), the wiring section 23 first connects the wiring in the wiring layer (Metal2) and the wiring layer (Metal2) among the wiring between the primitive cells. Connection in Metal 3) is performed (S4).

Next, the backing wiring in the backing wiring layer (Metal1) and the wiring in the wiring layer (Metal2) are connected. Another wiring of the wiring layer (Metal2) is placed on the backing wiring (power supply node) in the source region. It is determined whether or not there is
5). If another wiring of the wiring layer (Metal2) is present on the backing wiring (power supply node) of the source region (S5, Yes), the other wiring of the wiring layer (Metal2) covers the entire backing wiring (power supply node) of the source region. Then, it is determined whether or not power or ground cannot be directly supplied from the power supply region or ground region of the wiring layer (Metal3) to the backing wiring (power supply node) of the source region via a through hole (S6).

When power supply or ground cannot be directly supplied to the backing wiring (power supply node) in the source region (S
6, Yes), backing wiring (power supply node) of the source region that can be directly supplied with power or ground from the wiring layer (Metal3), and lining of the source region that cannot be directly supplied with power or ground from the wiring layer (Metal3) Wiring (power supply node) is connected through a region between the backing wirings of the divided drain region to supply power or ground (S7).

For example, in the example shown in FIG.
When the primitive cells shown in (1) are arranged and connected, the separate wiring 60 of the wiring layer (Metal2) covers directly above the backing wiring 32 in the source region, and power cannot be supplied directly from the wiring layer (Metal3). In this case, the backing wiring 32 of this source region and the source region 31 to which power can be supplied directly from the wiring layer (Metal3) are connected through a region between the backing wirings 33 and 34 of the divided drain region. By arranging and connecting the two primitive cells shown in FIG. 7A, an inverter is formed as shown in FIG. 7B.

In step S5, when there is no other wiring of the wiring layer (Metal2) on the backing wiring (power supply node) of the source region (S5, No), or in step S6, the power supply is directly applied to the backing wiring (power supply node) of the source region. If supply or ground supply is possible (S6, No), power supply or ground supply is performed to a place where power supply or ground supply is possible directly in the backing wiring of the source region (S8). That is, the wiring in the wiring layer (Metal2) is connected to the wiring of the wiring layer (Metal2) through the through hole at that location in the backing wiring of the source region, and the wiring of the wiring layer (Metal3) is further connected to the wiring of the wiring layer (Metal2) through the through hole. Connect to power or ground area.

Then, in the region of the gap between the divided backing wirings of the drain region, a region not used for the connection performed in step S7 is set as the backing wiring of the drain region (S9), and the process is terminated. For example, FIG.
When the primitive cells shown in FIG. 7 are arranged and connected, when the connection 61 connecting the backing wirings 31 and 32 of the source region passes through the region between the backing wirings 33 and 34 of the divided drain region, FIG. As shown in a), the backing wirings 33 and 34 in the divided drain region are expanded to such a degree that they do not contact the connection 61.

FIG. 8 is a diagram showing a cross section of a primitive cell automatically wired by the above processing. FIG. 8 (a)
Shows an AA ′ cross section of FIG. A source region and a drain region are formed in a diffusion region (Field) on the substrate, and gates 35 and 36 are formed above the source and drain regions to form a transistor. Also, the source region 7
1 and a backing wiring 32 in a source region formed on the backing wiring layer (Metal1) are connected via a contact hole 72. Further, the backing wiring 33 of the drain region formed on the wiring layer (Metal1) and the wiring layer (Metal2)
The wiring 73 formed above is connected by a through hole 74. Furthermore, a wiring 75 formed on the wiring layer (Metal2) and a power supply region 76 formed on the wiring layer (Metal3) are connected by a through hole 77.

FIG. 8B is a diagram showing the B-B of FIG. 7A.
The section B 'is shown. A source region and a drain region are formed in a diffusion region (Field) on the substrate, and gates 35 and 36 are formed above the source and drain regions to form a transistor. Further, the source region 71 and the backing wiring 31 of the source region formed on the backing wiring layer (Metal1)
And 32 are connected via a contact hole 81. Furthermore, the wiring layer (Meta
l2) The wiring 75 formed above and the power supply region 76 formed on the wiring layer (Metal3) are connected by through holes 82.

In step S3, if there is no user's designation to reduce the area of the backing wiring layer (Metal1) (S3, No), all the gaps between the separated backing wirings of the drain region are used as the backing wiring of the drain region. (S10), perform the conventional connection (S11),
The process ends. FIG. 9 shows an example of a case where the transistors are connected to two columns of primitive cells.

As described above, according to the semiconductor automatic wiring device of the present embodiment, the wiring portion 23 is divided when either the power supply region or the ground region cannot be directly connected to the backing wiring of the source region. Since a wiring for connecting the backing wiring of the source region is generated in a region between the backing wirings of the drain region, the area of the backing wiring layer can be reduced, and the integration degree of the semiconductor integrated circuit can be increased. .

[0037]

According to the semiconductor automatic wiring device of the first aspect, when the wiring means cannot directly connect one of the power supply region and the ground region to the backing wiring of the source region, the wiring means backs the divided drain region. Since the wiring for connecting the backing wiring of the source region is generated in the region between the wirings, the area of the backing wiring layer can be reduced, and the integration degree of the semiconductor integrated circuit can be increased.

According to the semiconductor automatic wiring apparatus of the second aspect, the wiring means generates a wiring for connecting the backing wiring of the source region to a region between the backing wirings of the separated drain region, and then the wiring is divided. The area between the backing wiring of the drain area and the area where the wiring connecting the backing wiring of the source area did not pass is used as the backing wiring of the drain area, so the backing wiring of the drain area can be enlarged and the signal line can be stabilized. I was able to plan.

According to the semiconductor automatic wiring method according to the third aspect, when one of the power supply region and the ground region cannot be directly connected to the backing wiring of the source region, the divided region between the backing wiring of the drain region is removed. Since the wiring for connecting the backing wiring in the source region is generated, the area of the backing wiring layer can be reduced, and the integration degree of the semiconductor integrated circuit can be increased.

According to the semiconductor automatic wiring program recorded on the medium according to the fourth aspect, when one of the power supply region and the ground region cannot be directly connected to the backing wiring of the source region, the backing of the divided drain region is performed. Since the wiring for connecting the backing wiring of the source region is generated in the region between the wirings, the area of the backing wiring layer can be reduced, and the integration degree of the semiconductor integrated circuit can be increased.

[Brief description of the drawings]

FIG. 1 is a view showing the appearance of a semiconductor automatic wiring device of the present invention.

FIG. 2 is a block diagram showing a configuration of a semiconductor automatic wiring device of the present invention.

FIG. 3 is a diagram illustrating a schematic configuration of a semiconductor automatic wiring device according to an embodiment of the present invention.

FIG. 4 is a flowchart for explaining a processing procedure of the semiconductor automatic wiring device according to the embodiment of the present invention.

FIG. 5 shows a primitive cell (transistor having one transistor) generated by the semiconductor automatic wiring device according to the embodiment of the present invention.
It is a figure which shows an example of the case of a column).

FIG. 6 shows a primitive cell (two transistors) generated by the semiconductor automatic wiring device according to the embodiment of the present invention.
It is a figure which shows an example of the case of a column).

FIG. 7A is a diagram showing an example of a primitive cell arranged and wired by the semiconductor automatic wiring device according to the embodiment of the present invention. (B) is a diagram showing a logic gate constituted by the primitive cells shown in (a).

FIG. 8A is a diagram showing a cross section AA ′ of the primitive cell shown in FIG. 7A. FIG.
It is a figure which shows the BB 'cross section of the primitive cell shown to (a).

9 is a diagram showing a case where a backing wiring of a source region of the primitive cell shown in FIG. 6 is connected.

FIG. 10 is a diagram showing an example of a primitive cell (in the case of one row of transistors) generated by a conventional semiconductor automatic wiring device.

FIG. 11 is a diagram showing an example of a primitive cell (in the case of two columns of transistors) generated by a conventional semiconductor automatic wiring device.

FIG. 12 is a diagram showing an example of a case where a conventional semiconductor automatic wiring device connects primitive cells (in a case where transistors are arranged in two columns).

[Explanation of symbols]

1 Computer main body, 2 Graphic display device, 3 Magnetic tape device, 4 Magnetic tape, 5 Keyboard, 6 Mouse, 7 CD-ROM device, 8 CD-
ROM, 9 communication modem, 10 CPU, 11 ROM,
12 RAM, 13 hard disk, 21 primitive cell generator, 22 primitive cell placement unit, 23
A wiring portion, 31, 32, 41 to 43, a backing wiring of a source region, 33, 34, 44 to 47 a backing wiring of a divided drain region, 35, 36, 48 to 51 gates,
61 connection, 71 source region, 72, 81 contact hole, 73, 75 wiring, 74, 77, 82 through hole.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B046 AA08 BA06 5F033 BA11 CA02 CA07 5F048 AC01 5F064 CC09 DD50 EE02 EE26 EE27 EE52 EE60 HH05

Claims (4)

[Claims] 1. A generating means for generating a primitive cell including a backing wiring of a source region, a backing wiring of a divided drain region, and a gate, and an arranging means for arranging the primitive cell corresponding to a logic circuit When wiring the primitive cells, if either the power supply region or the ground region cannot be directly connected to the backing wiring of the source region, the backing wiring of the source region is placed in the region between the separated backing wirings of the drain region. A wiring means for generating wiring to be connected. 2. The method according to claim 1, wherein the wiring unit generates a wiring connecting the backing wiring of the source region between the backing wirings of the divided drain region, and then generates the wiring in a region between the backing wirings of the divided drain region. 2. The semiconductor automatic wiring apparatus according to claim 1, wherein a backing wiring of the drain region is generated in a region where the wiring connecting the backing wiring of the source region does not pass. 3. A step of generating a primitive cell including a backing wiring of a source region, a backing wiring of a separated drain region, and a gate; arranging the primitive cell in correspondence with a logic circuit; In wiring, if one of the power supply region and the ground region cannot be directly connected to the backing wiring of the source region, a wiring for connecting the backing wiring of the source region to a region between the backing wirings of the divided drain region is generated. And a semiconductor automatic wiring method. 4. A step of generating a primitive cell including a backing wiring of a source region, a backing wiring of a separated drain region, and a gate; arranging the primitive cell in correspondence with a logic circuit; In wiring, if one of the power supply region and the ground region cannot be directly connected to the backing wiring of the source region, a wiring for connecting the backing wiring of the source region to a region between the backing wirings of the divided drain region is generated. Recording a semiconductor automatic wiring program including: