JP2000057197A - System for changing layout design of clock net - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a TAT(turn-around-time) at the time of changing design while satisfying a skew which is permitted in a clock tree even when an FF (a function cell including a flip-flop for inputting a clock signal) is added by the design change. SOLUTION: A design change mode clock tree generating means 10 adds a change to an existing clock tree when an additionally arranged FF exists while preserving an already generated clock tree, that is, a wiring for connecting a clock buffer and the clock buffer and the FF. More concretely, there are the following methods that (a): a clock wiring to the added FF is connected to the near part among the existing wirings of the clock net as much as possible and (b): the clock wiring to the added FF is connected to the near part of the output terminal of the already arranged clock buffer in the clock net and the buffer is inserted or a detour wiring is generated to adjust the delay at the time of necessity.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for changing the layout design of a clock net, and more particularly to a clock net for changing the layout design of a large-scale semiconductor integrated circuit (LSI) employing a clock tree structure for supplying a clock signal. The layout design change method.

[0002]

2. Description of the Related Art FIG. 5 is a diagram illustrating an example of a clock tree structure. As shown in FIG.
A clock signal is supplied from a clock signal input unit 52 to each of a plurality of flip-flops and the like (function cells for inputting a clock signal including a flip-flop; hereinafter, abbreviated as FF) 53 provided by a clock net. Will be described by way of an example of distributing. Note that, for convenience of illustration, all reference numerals are not given, but in FIG. 5 and FIGS. 2 to 4 described below, a rectangle indicates a functional cell (FF).
Also, although the clock signal is input from outside the chip,
If a PLL (Phase Locked Loop) circuit is used, the output terminal of the PLL circuit can be considered as a clock signal input unit.

In order to generate a clock tree for the LSI chip 51 shown in FIG. 1A, as shown in FIG.
The wiring path 54 up to this point has a tree structure via a buffer 55. At this time, by appropriately determining the arrangement position of the buffer 55 and the wiring path 54 at the same time in consideration of the signal propagation delay, the phase difference between the clock signals reaching each FF 53, that is, the clock skew can be reduced.

A method for automatically generating the clock tree structure has been conventionally known (Japanese Patent Laid-Open No. 5-54100). In today's high-speed layout design,
It is often used because skew reduction is important. The buffer 55 inserted to generate the clock tree is hereinafter referred to as a clock buffer. In the above publication, clock wiring is performed at the same time as arranging the clock buffer to perform more strict skew adjustment. However, a method that does not perform wiring processing is also in practical use.

In any case, the clock tree generation processing is performed after the functional cell arrangement processing is completed and before the wiring processing in the layout design. By this clock tree generation processing, the clock list in the net list is divided at the beginning from the single clock list by the clock buffer.

Next, a conventional design change method will be described. In the layout design, the netlist may be changed from the initial one by the circuit designer after the placement processing and the wiring processing are once completed. In such a case, it is possible to discard the already completed placement and routing results and start over with the layout design from the beginning, but if there are only a few changes, reuse the already completed placement and routing results as much as possible A method of performing only the position wiring for the existing portion has been generalized (for example, JP-A-4-247579 and JP-A-2-94543). In this method, TAT (Turn Aroun
d Time) is short.

FIG. 6 is a diagram in which the conventional system described in the above-mentioned Japanese Patent Application Laid-Open No. 4-247579 has been rewritten for easy comparison with the present invention. In the figure, the design information input means 60 in the design change device 57 inputs the existing netlist and layout information before the design change and the netlist after the design change, and the design information storage section 67 in the storage device 56. To memorize. The design change information extraction means 61 compares the netlists before and after the design change, and detects some changes such as addition or replacement of a functional cell and reconnection of nets,
The detection result is stored in the design change information storage unit 68 in the storage device 56.

The arrangement deleting means 62 and the wiring deleting means 63 in the design changing device 57 peel off the functional cells which cannot be used due to the design change and the wirings connected thereto. The design change mode arranging means 64 in the design change device 57 arranges functional cells that have not been arranged yet after the netlist change processing. The already arranged function cells are processed so as not to move as much as possible. This processing technique is disclosed in
A method of adding a cell to a position where an evaluation function determined by a connection relationship between the cell and an already-arranged cell is maximum or minimum or in the vicinity thereof as described in -94543. Can be applied.

The design change mode wiring means 65 in the design change device 57 connects a net whose connection has not yet been completed. Existing wiring results are reused as much as possible. This design change mode wiring means 65 is disclosed in
A wiring processing method as disclosed in Japanese Patent No. 10135 can be applied. When the processing necessary for the design change is completed, the layout result information is output by the design change result output unit 66. The storage device 58 can store data from the data input device 56 and can output the stored data to the data output device 59.

In this conventional clock net layout design change method, the netlist that has been placed and routed before the design change is after the clock tree is generated, and the netlist input after the design change is the one before the clock tree is generated. Therefore, if nothing is taken into consideration, the design change information extracting means 61 detects the change point, and the entire arrangement and wiring of the clock tree portion is torn off. However, in practice, if the clock net itself has not been changed in design, the previous tree structure should be reusable.
For this reason, the actual CAD tool has a mechanism that can save the generation result of the clock net, and can execute the design change without any trouble.

[0011]

However, the above-described conventional clock net layout design changing method has a problem when a design change occurs in the clock net. That is, in the field of LSI development, there is a case where a design change is made to add an FF to a circuit that does not satisfy the operation speed to satisfy the operation speed specification. In such a case, the following problem occurs.

The first problem is that, when a design change relating to a clock net occurs, a clock tree generation requiring a long processing time and redoing of a wiring process occur, and the design TAT increases. That is, in the conventional method shown in FIG.
A design change mode arranging means 64 for performing a design change for the first automatic wiring means and a design change mode wiring means 65 for the first automatic wiring means are provided. The first clock tree generator
It does not have the design change mode clock tree generation means.

That is, if a design change relating to the clock tree occurs due to an increase or decrease in the number of FFs, the generation of the clock tree must be restarted from the beginning. Clock tree generation must be performed before automatic routing,
Existing wiring results cannot be reused. Therefore, in the conventional method, when there is a design change in the clock net, it is necessary to restart the clock tree generation and the wiring process from the beginning. In addition, the conventional clock tree generation methods are also methods for generating a tree without a tree, and cannot reuse an existing tree.

A second problem of the conventional method is that if timing verification is performed after the placement and routing after the design change is completed, a new timing error occurs in a place irrelevant to the changed net, and this correction is made. This may cause an increase in the TAT. The reason is that since the existing wiring result cannot be used, the wiring route and the wiring length of any net may be changed.

The present invention has been made in view of the above points,
An object of the present invention is to provide a clock net layout design change method capable of shortening the TAT at the time of design change while satisfying the skew allowed for the clock tree even when an FF is added by a design change.

Another object of the present invention is to provide a clock capable of reducing the occurrence of a new timing error in a portion irrespective of a changed portion even when an FF is added by a design change. An object of the present invention is to provide a net layout design change method.

[0017]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention changes the layout design of a clock net for changing the layout design of a large-scale semiconductor integrated circuit employing a clock tree structure to supply a clock signal. In the method, design change information extraction means for comparing the netlist before the design change and after the design change, and detecting some changes such as addition or replacement of a functional cell, reconnection of nets,
Design change mode arranging means for arranging functional cells that have not yet been arranged after the netlist change processing, and clocks for the functional cells additionally arranged by the design change mode arranging means while preserving the already generated clock tree. A design change mode in which wiring is branched from the existing wiring of an existing clock tree and connected from a place as close as possible to the additionally arranged functional cell, and a clock tree generating means, and a design for wiring a net with incomplete connection And a change mode wiring means.

According to the present invention, the layout in which the clock wiring to the additionally arranged functional cell is connected in such a manner that the skew allowed for the clock tree is satisfied by making a slight change to the existing wiring of the existing clock tree. Can be completed.

Further, in the present invention, the design change mode clock tree generating means may be configured so that the density of the clock wiring, which is branched and connected from a place as close as possible to the additionally arranged functional cell, when the existing wiring is included, is set to the set value. If the clock wiring is higher than the existing wiring, the existing wiring is ignored and the clock wiring is wired, and the design change mode wiring means avoids the general signal wiring for the clock wiring after the clock wiring is completed by the design change mode clock tree generation means. It is characterized in that wiring is performed again.

According to the present invention, the clock wiring to the additionally arranged functional cell is given the highest priority, so that the wiring can be made as short as possible in consideration of an increase in delay and signal dullness.

According to another aspect of the present invention, there is provided a clock net layout design changing method for changing a layout design of a large-scale semiconductor integrated circuit employing a clock tree structure to supply a clock signal. Compare the netlist before and after the design change,
Design change information extraction means for detecting some changes such as addition or replacement of function cells, reconnection of nets, and design change mode arrangement means for arranging function cells that have not been arranged after the netlist change processing, A design change in which the clock wiring to the function cells additionally placed by the design change mode placement means is branched and connected near the output terminal of the clock buffer of the existing clock tree while preserving the already generated clock tree. The configuration has at least a mode clock tree generating means and a design change mode wiring means for wiring a net whose connection is not completed.

The present invention also provides a layout in which clock wiring to an additionally arranged functional cell is connected in a state where the skew allowed for the clock tree is satisfied by making a slight change to the existing wiring of the existing clock tree. Can be completed.

Further, according to the present invention, the design change mode clock tree generating means calculates a delay time to all the function cells belonging to the existing clock tree, and calculates a delay of an intermediate value between the calculated maximum and minimum delay times. The delay adjusting means having a time is provided in the middle of a clock wiring connected to a functional cell additionally provided by branching from near the output terminal of the clock buffer.

Here, it is desirable that the delay adjusting means in the above-mentioned invention has at least one delay buffer which is arranged immediately near the output terminal of the clock buffer. This is because a change in load before and after a design change of a net to be branched can be reduced, and a change in wiring delay of the net can be minimized.

According to the present invention, in order to achieve the above object, the design change mode clock tree generating means is provided with a function additionally provided by the design change mode arranging means while preserving the already generated clock tree. A first connection method of branching and connecting a clock wiring to a cell from an existing wiring of an existing clock tree as close as possible to an additionally arranged functional cell, and a method of connecting a clock wiring to an additionally arranged functional cell. The clock wiring is configured to be connected by selectively using the second connection method of branching and connecting near the output terminal of the clock buffer of the existing clock tree, and the skew of the entire clock tree when connected by the first connection method is reduced. The connection is performed by the second connection method only when a target skew value cannot be obtained.

According to the present invention, the first connection method which is advantageous in terms of wiring properties and power consumption can be prioritized. In the first connection method, when an increase in skew or delay becomes a problem, an increase in skew or delay may occur. Connection can be made with a small number of second connection methods, and an optimum layout design can be changed in accordance with the arrangement position of the additionally arranged function cell.

Further, the present invention provides a design change mode clock tree generating means that, when there are a plurality of additionally arranged function cells, two of the plurality of additionally arranged function cells which are arranged close to each other. The above function cells are grouped together, and a subtree is generated using a clock buffer and wiring so that skew is reduced.Then, the subtree is branched from near the output terminal of the clock buffer of the existing clock tree, and the wiring and delay buffer are added to the subtree. The remaining function cells of the plurality of function cells additionally connected and connected are independently connected to the existing clock wiring.

According to the present invention, by generating subtrees, even if the number of function cells to be added increases, congestion near the clock buffer can be avoided as much as possible, and increase in the load on the net can be suppressed as much as possible. The influence can be reduced.

[0029]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a clock net layout design change method according to the present invention. As shown in FIG. 1, this embodiment includes a data input device 1, a design change device 2, a storage device 3,
And a data output device 4. The design change device 2 includes a design information input unit 5, a design change information extraction unit 6, a placement deletion unit 7, a wiring deletion unit 8, a design change mode placement unit 9, and a design change mode clock tree generation unit 1.
0, design change mode wiring means 11, and design change result output means 12. The storage device 3 includes a design information storage unit 13 and a design change information storage unit 14.
This embodiment is characterized in that the design change mode clock tree generating means 10 is provided in the design change device 2 as compared with the conventional system of FIG.

Next, the operation of this embodiment will be described. The design information input means 5 inputs the existing netlist and layout information before the design change and the netlist after the design change, and stores them in the design information storage unit 13. The design change information extracting means 6 compares the netlists before and after the design change, and detects some changes such as addition or replacement of a functional cell and reconnection of nets. The result is
It is stored in the design change information storage unit 14. Layout deletion means 7
Then, the wiring deletion means 8 peels off the functional cell which cannot be used due to the design change or the wiring connected thereto. The design change mode arranging means 9 arranges functional cells that have not been arranged yet after the netlist change processing.

The design change mode clock tree generating means 10, which is a main part of this embodiment, additionally arranges the clock tree which has already been generated, that is, the clock buffer and the wiring connecting the clock buffer and the FF. If any FF is found, change the existing clock tree. More specifically, (a) the added FF
And (b) connecting the clock wiring to the added FF near the output terminal of the existing clock buffer of the same clock net. If necessary, there is a method of adjusting the delay by inserting a buffer or generating a bypass wiring. The design change mode wiring means 11 wires a net for which connection has not yet been completed. When the processing required for the design change is completed, the layout result information is output from the design change result output means 12.

In this embodiment, with the above configuration,
A layout that satisfies the skew allowed for the clock tree can be completed by making only a slight change to the already placed wiring. You only need to do the department. Further, since the existing wiring result is reused as much as possible, the wiring result after the design change can be prevented from largely changing.

The present embodiment does not aim to obtain a skew as close as possible to zero. This is for the following reason. First, even if a layout design having a skew very close to zero can be theoretically made, it is practically impossible to reduce the skew to zero because the characteristics vary from place to place on an actual silicon wafer. Because there is. Second, if the skew is too small, another problem such as power consumption due to the simultaneous operation of the circuits occurs. Therefore, in today's clock design, it is required to carry out layout design so as to fall within a practical skew within a certain allowable range, and the allowable range is also taken into consideration in each embodiment described below. .

[0034]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the design change mode clock tree generating means 10 of the main part of the present invention will be described below.

FIG. 2 is a layout diagram of a first embodiment of the present invention. In this embodiment, the clock wiring to the added FF is changed among the existing wirings of the clock net.
An example of branching and connecting from a place as close as possible to the added FF will be described. As shown in FIG. 5B, the wiring path 54 from the clock signal input unit 52 to each of the FFs 53 to be operated simultaneously is changed by a design change to the LSI chip 51 having a completed tree structure via the clock buffer 55. The number of FFs increases, and the design change mode arrangement means 9 of FIG.
Assume that the FF 15 is arranged at the position shown in FIG.

The design change mode clock tree generating means 10 shown in FIG. 1 searches for the clock net 16 closest to the FF 15 and connects them with the shortest possible wiring 17. It should be noted that the delay time of the clock signal for all the FFs that have been receiving the clock signal on the net 16 slightly increases due to the influence of the load of the added FF 15 and the wiring 17.

If the wiring density is low, the existing wiring may be avoided if the wiring density is low. However, if the wiring density is high, the existing wiring is ignored in principle. After the clock wiring is performed, the general signal wiring may be slightly avoided so that an error such as a short circuit generated later with the general signal wiring is eliminated.
This is because it is better to make the clock wiring shorter in consideration of an increase in delay, signal rounding, and the like. To avoid the general signal wiring, the design change mode wiring means 1
1 can be realized.

(Second Embodiment) FIG. 3 shows a layout diagram of a second embodiment of the present invention and a third embodiment described later. This second
In the embodiment, the clock wiring to the added FF is branched and connected near the output terminal of the already arranged clock buffer of the same clock net, and if necessary, the buffer is further used or the wiring is bypassed. This is an example of adjusting the delay with.

That is, as shown in FIG. 5B, the number of FFs increases due to the design change in the LSI chip 51 having the completed clock tree structure, and the design change mode arrangement means 9 shown in FIG. It is assumed that the FF 18 is arranged at the position. The design change mode clock tree generation means 10 of FIG. 1 first calculates the delay time to all the FFs belonging to the existing clock tree, and obtains the maximum and minimum values.
With this, it is possible to determine how long the delay time up to the added FF 18 does not deteriorate the skew of the entire tree. The delay buffer is inserted and the wiring path is adjusted based on this.

For example, an intermediate value between the maximum and the minimum of the delay time is targeted. In the example of FIG. 3, the wiring is branched from near the output terminal of the clock buffer 19 in the first stage. Then, by adjusting the types and positions of the delay buffers 20 and 21, the skew of the entire clock tree satisfies the specification. Instead of inserting a delay buffer, the wiring length may be adjusted by a bypass wiring.

The branching described above is preferably performed as close to the output terminal of the clock buffer as possible, and at least one delay buffer is preferably positioned immediately after branching.
By reducing the change in the load before and after the design change of the branching net, the change in the wiring delay of the net can be minimized, and the delay to be realized when generating the route to the FF to be added. Is easier and more accurate.

Therefore, in the example of FIG. 3, the wiring is branched from near the output terminal of the clock buffer 19, and the delay buffer 20 is placed immediately after the branch. Due to the effects of the delay buffer 20 and the slight wiring branched to input to the delay buffer 20, the delay time of the clock signal for all the FFs that have received the clock signal on the net 22 increases slightly. Note that The method of calculating the delay may be the same as that of the clock tree generating means. In general, a table look-up method is often used to calculate a delay generated in a functional cell, and an Elmore delay model is often used to calculate a wiring delay.

(Third Embodiment) In the third embodiment, if the wiring of this clock net does not exist near the FF to be added, the method of the first embodiment causes an increase in skew and delay. Although the method of the second embodiment is suitable, the use of the method of the second embodiment is disadvantageous in terms of wiring properties and power consumption.

In order to perform the above-mentioned use properly, a target skew value is given to the design change mode clock tree generating means 10, and if the method of the first embodiment is tried, if the target cannot be satisfied, the method of the second embodiment is used. Should be adopted. For example, with reference to FIG. 3, first, the FF 18 to be added is added.
Applying the method of the first embodiment to the
To the FF 18. A trial connection is made, or a wiring route is temporarily estimated, and the skew of the entire clock tree is calculated. In the example of FIG. 3, since the position of the net 23 and the FF 18 is far, the delay time to the FF 18 increases, and the target skew value cannot be satisfied. In that case, the method of the first embodiment is canceled and the adjustment is performed by the method of the second embodiment.

(Fourth Embodiment) FIG. 4 is a layout diagram of a fourth embodiment of the present invention. This embodiment is an example in which a plurality of FFs are added. When adding multiple FFs,
(A) A method of adding the added FFs one by one according to the method of the third embodiment. (B) First, a subtree is created by grouping adjacent ones of the added FFs, and then the second tree is added.
A method of connecting them in the manner of the embodiment, (c) a method of combining them, and the like are conceivable. FIG. 4 is an example of FIG.

That is, as shown in FIG. 5B, three FFs are increased by the design change in the LSI chip 51 having the completed clock tree structure, and the design change mode arrangement means 9 in FIG. FF24, 2
Assume that 5 and 26 are arranged. The design change mode clock tree generation means 10 of FIG. 1 first collects the additional FFs arranged nearby. Here, the added F
Since F25 and FF26 are arranged close to each other, they are put together and the clock buffer 28 and the wiring 27
Is used to generate a subtree such that the skew is reduced. For this method, a conventional clock tree generating means can be used.

Subsequently, the wiring is branched from near the output terminal of the clock buffer 31 and the skew of the whole new tree is adjusted using the delay buffer 29 and the wiring 30 so as to satisfy the specification. Another FF24 added
Are separated, so they are processed independently.

In this embodiment, since the subtree is generated, the following effects are obtained. If the FF 25 and the FF 26 are to be connected to the net 22 by the method of the second embodiment in the above example, two delay buffers are arranged near the clock buffer 31. When the number of FFs to be added increases, the vicinity of the clock buffer 31 becomes more crowded, and the load on the net 22 also increases. When a subtree is generated, the influence on the existing tree can be reduced when there are many FFs to be added.

The present invention is not limited to the above-described embodiments and examples. For example, even if there are not only one clock system as in the above-described embodiments and examples, but also a plurality of clock systems, The present invention can be applied by processing in order for each system. When a design change process is performed on existing data for which a clock tree has been generated but has not been wired, delay calculation is performed by estimating a wiring path, and actual wiring is performed by the design change mode wiring means 11. It is applicable by leaving it. However,
The actual wiring route may be different from the estimated wiring route.

[0050]

As described above, according to the present invention,
By making a slight change to the existing wiring of the existing clock tree, it is possible to complete the layout in which the clock wiring to the additionally placed functional cells is connected while satisfying the skew allowed for the clock tree. Therefore, even if a design change occurs, clock tree generation and wiring processing that require a long processing time can be performed in a short time, and the design change TAT can be shortened.

Further, according to the present invention, the existing wiring result is reused as much as possible so that the wiring result after the design change is not largely changed. New timing errors are less likely to occur.

Further, according to the present invention, when there are a plurality of functional cells to be additionally arranged in the clock tree, sub-trees are generated for two or more functional cells arranged in close proximity to each other, so that more functional cells are added. Even if
The congestion near the clock buffer can be avoided as much as possible, and the increase in the load on the net can be suppressed as much as possible, and the influence on the existing clock tree can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a layout diagram of the first embodiment of the present invention.

FIG. 3 is a layout diagram of a second embodiment and a third embodiment of the present invention.

FIG. 4 is a layout diagram of a fourth embodiment of the present invention.

FIG. 5 is a layout diagram of a clock tree generation example.

FIG. 6 is a block diagram illustrating a configuration of a conventional example.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 data input device 2 design change device 3 storage device 4 data output device 5 design information input means 6 design change information extraction means 7 placement deletion means 8 wiring deletion means 9 design change mode placement means 10 design change mode clock tree generation means 11 design Change mode storage unit 12 Design change result output unit 13 Design information storage unit 14 Design change information storage unit 15, 18, 24 to 26 Additional FF 16, 22, 23 Clock net 17, 27, 30 Wiring 19, 28, 31 Clock buffer 20, 21, 29 delay buffer

Claims (7)

[Claims] In a clock net layout design change method for changing a layout design of a large-scale semiconductor integrated circuit employing a clock tree structure to supply a clock signal, a net list before and after the design change is compared. Design change information extraction means for detecting some changes such as addition or replacement of function cells, reconnection of nets, and design change mode placement means for placing function cells that have not yet been placed after netlist change processing While preserving the already generated clock tree, the clock wiring to the functional cell additionally arranged by the design change mode arranging means is replaced by the existing wiring of the existing clock tree among the existing wirings. Design change mode clock tree generation means for branching and connecting as close as possible to the functional cell, and connection Layout design change scheme of the clock net and having at least a design change mode wiring means for wiring the completed non net. 2. The design change mode clock tree generating means according to claim 1, wherein a density of a clock wiring connected and branched from a place as close as possible to the additionally arranged function cell, including an existing wiring, is higher than a set value. When the clock wiring is high, the existing wiring is ignored and the wiring of the clock wiring is performed, and the design change mode wiring means, after the clock wiring by the design change mode clock tree generating means, ends the general signal wiring with respect to the clock wiring. 2. The method according to claim 1, wherein the wiring is re-wired to avoid the problem. 3. A clock net layout design changing method for changing a layout design of a large-scale semiconductor integrated circuit employing a clock tree structure for supplying a clock signal, wherein a net list before and after the design change is compared. Design change information extraction means for detecting some changes such as addition or replacement of function cells, reconnection of nets, and design change mode placement means for placing function cells that have not yet been placed after netlist change processing While preserving the already generated clock tree, branching the clock wiring to the function cell additionally arranged by the design change mode arrangement means from near the output terminal of the clock buffer of the existing clock tree. The design change mode clock tree generation means to be connected and the net with incomplete connection Layout design change scheme of the clock net and having at least a design change mode wiring means. 4. The design change mode clock tree generating means calculates a delay time up to all function cells belonging to the existing clock tree, and calculates a delay time having an intermediate value between the calculated maximum and minimum delay times. 4. The layout design change of the clock net according to claim 3, wherein the delay adjusting means is provided in the middle of the clock wiring connected to the additionally arranged function cell by branching from the output terminal of the clock buffer. method. 5. The layout of a clock net according to claim 4, wherein said delay adjusting means has at least one delay buffer branched immediately from an output terminal of said clock buffer and disposed immediately therefrom. Design change method. 6. A clock net layout design change method for changing a layout design of a large-scale semiconductor integrated circuit employing a clock tree structure for supplying a clock signal, wherein a net list before and after the design change is compared. Design change information extraction means for detecting some changes such as addition or replacement of function cells, reconnection of nets, and design change mode placement means for placing function cells that have not yet been placed after netlist change processing While preserving the already generated clock tree, the clock wiring to the functional cell additionally arranged by the design change mode arranging means is replaced by the existing wiring of the existing clock tree among the existing wirings. A first connection method for branching and connecting from a location as close as possible to the function cell, and Design change mode clock tree generating means for selectively connecting the clock wiring of the clock tree of the existing clock tree near the output terminal of the clock buffer by using a second connection method, and connecting the nets with uncompleted connections. At least a design change mode wiring means for wiring, wherein the design change mode clock tree generating means sets a skew of the entire clock tree when connected by the first connection method when a target skew value cannot be obtained. A clock net layout design change method, wherein only the second connection method is used for connection. 7. The design change mode clock tree generating means, when there are a plurality of additionally arranged function cells, two or more of the plurality of additionally arranged function cells arranged close to each other. The function cells of
In addition, a subtree is generated using a clock buffer and a wiring so as to reduce the skew, the branch is branched from near the output terminal of the clock buffer of the existing clock tree, and connected to the subtree using a wiring and a delay buffer. 7. The clock net layout design change method according to claim 1, wherein the remaining functional cells among the plurality of functional cells additionally arranged are independently connected to an existing clock wiring.