JP2000049225A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent leakage current between contact material which is connected to a wiring layer and a semiconductor substrate and form a low- resistance contact between the contact material and an impurity diffused layer, even if contact hole formed positions are misaligned from the impurity diffused layer. SOLUTION: In a p-type semiconductor substrate 2, an n+-diffused layer 6 of the conductive type which is reverse to that of this semiconductor substrate 2 is formed. An insulating film 8 is formed on the n+-diffused layer 6. Furthermore, a wiring layer 18 is formed on the insulating film 8. A hole is formed in the insulating film 8 to be filled with a contact material for allowing the n+-diffused layer 6 to contact the wiring layer 18. A titanium silicide film 12 is formed on the n+-diffused layer 6 in the hole. A polysilicon layer 14, in which the impurity of the same conductive type as that of the n+-diffused layer has been doped in advance is formed on the generally vertical sidewall of the hole. Then, tungsten 16 is embedded in the titanium silicide film 12 and the polysilicon film 14 in the hole.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a method of contacting an impurity region (diffusion layer) in a semiconductor substrate with a wiring layer provided thereon via an insulating film. And a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, when LOCOS has been used as an element isolation technique, a high-concentration impurity region (for example, a diffusion layer region serving as a source or a drain of a transistor) in an element region surrounded by a field oxide film and this In some cases, a contact plug is formed between the region and a wiring layer provided with an insulating film interposed therebetween.

FIG. 11 is a sectional view showing a structure of a conventional contact plug formed between an impurity region provided between field oxide films and a wiring layer. As shown in FIG. 11, a field oxide film 104 as an element isolation region is formed on a semiconductor substrate 102, and a diffusion layer 106 which is, for example, a drain of a MOS transistor is formed between the field oxide films 104. . Further, a silicon oxide film or BP is formed on the entire surface of the semiconductor substrate 102.
An insulating film made of SG or the like is formed, and a wiring layer 110 is formed on the insulating film. On the diffusion layer 106, a contact hole is formed by opening the insulating film 108.
Plug 11 for connecting wiring 06 and wiring layer 110
2 are formed.

In forming the contact plug 112,
A desired portion of the insulating film 108 is formed by R
The contact hole is formed by removal by IE or the like. At this time, due to misalignment at the time of resist patterning in the lithography method, the etching of the insulating film 108 for opening the contact hole also etches the field oxide film 104, and the contact hole becomes
In some cases, it can reach 4 below.

As a result, there is a problem that a conductor buried in the contact hole in a subsequent step comes into contact with a portion outside the high-concentration impurity region, and a leak current occurs between the wiring layer and the semiconductor substrate.

In order to solve this problem, conventionally, when a contact hole is opened, impurities are implanted again using the pattern after the opening of the contact hole as a mask, thereby forming a high concentration impurity region 112 on the surface of the semiconductor substrate 102 exposed by etching. To suppress the occurrence of leakage current (conventional example 1).

[0007]

However, in recent years, STI (Shallow Trench Isolation) has been used as an element isolation technique, and a box-shaped insulating film has been formed in an element isolation region.

FIG. 12 is a sectional view showing a structure of a conventional contact plug formed between an impurity region provided between STIs and a wiring layer. As shown in FIG. 12, the semiconductor substrate 122 has an STI as an element isolation region.
The diffusion layer 126 is formed between the STIs 124, for example, the drain of the MOS transistor. Further, an insulating film 128 made of a silicon oxide film, BPSG, or the like is formed on the entire surface of the semiconductor substrate 122, and a wiring layer 130 is formed on the insulating film 128. The insulating film 12 is formed on the diffusion layer 126.
8, a contact hole is formed, and a contact plug 132 for connecting the diffusion layer 126 and the wiring layer 130 is formed in the contact hole.

In this STI, when the misalignment as described above occurs, the STI is performed by RIE for opening a contact hole.
Semiconductor substrate 12 exposed by etching TI 124
The region surface 134 having a low impurity concentration of 2 is substantially perpendicular to the substrate surface. For this reason, even if impurities are implanted at an angle nearly perpendicular to the contact hole, sufficient impurities do not enter the low impurity concentration region surface 134, and a high concentration impurity region cannot be formed in this region surface 134.

Therefore, the contact plug 132 buried in the contact hole in a subsequent step comes into contact with a portion outside the high-concentration impurity region (diffusion layer 126), that is, a region surface 134 with a low impurity concentration, and the semiconductor substrate 122 and the There is a problem that a leak current occurs between the wiring layers 130.

On the other hand, there is a technique in which a leakage current is suppressed by burying polysilicon containing a high-concentration impurity region and an impurity of the same conductivity type in advance in the contact hole as a burying material (conventional example 2). However, in this case, there is a problem that the resistance of polysilicon itself is higher than that of metal, and the resistance of the contact surface between the diffusion layer and polysilicon is higher.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to form a contact hole by opening an insulating film formed on an impurity diffusion layer of a semiconductor substrate.
Even if the contact hole is displaced from the impurity diffusion layer, no leakage current occurs between the contact material connected to the wiring layer and the semiconductor substrate, and a low resistance between the contact material and the impurity diffusion layer. An object of the present invention is to provide a semiconductor device capable of forming a contact and a method for manufacturing the same.

[0013]

In order to achieve the above object, a semiconductor device according to the present invention comprises an impurity layer formed in a semiconductor substrate and having a conductivity type opposite to that of the semiconductor substrate, and an impurity layer formed on the impurity layer. An insulating film, a wiring layer formed on the insulating film, an opening formed in the insulating film for embedding a contact material for contacting the impurity layer and the wiring layer, A metal silicide film formed on the impurity layer in the portion, a silicon film containing an impurity of the same conductivity type as the impurity layer formed on the exposed surface of the semiconductor substrate in the opening, and the silicon film in the opening. A contact plug formed on the metal silicide film and the silicon film.

Further, according to the semiconductor device of the present invention, there is provided an element isolation region formed by embedding an insulating film in a groove provided in a semiconductor substrate, and the semiconductor device formed to be sandwiched between the element isolation regions. An impurity layer of the opposite conductivity type to the substrate;
An insulating film formed on the element isolation region and the impurity layer, and a wiring material for connecting the impurity layer sandwiching the element isolation region, are embedded in the insulating film both on the impurity layer and on the element isolation region. A metal silicide film formed on the impurity layer in the hole, and the impurity layer formed on the exposed surface of the semiconductor substrate under the impurity layer in the hole. And a silicon film containing an impurity of the same conductivity type as above, and a wiring formed on the metal silicide film and the silicon film in the opening.

Further, in the method of manufacturing a semiconductor device according to the present invention, a step of forming an impurity layer of a conductivity type opposite to that of the semiconductor substrate on a semiconductor substrate; a step of forming an insulating film on the impurity layer; Forming an opening in the insulating film to make contact with a layer; and forming a silicon film containing impurities on the impurity layer in the opening and on the semiconductor substrate surface exposed in the opening. Forming a metal film on the silicon film on the impurity layer in the opening, and reacting the silicon film and the metal film by performing a heat treatment to form a metal silicide film. And a step of embedding a metal in the opening.

Further, in the method of manufacturing a semiconductor device according to the present invention, a step of forming an element isolation region by burying an insulating film in a groove provided in the semiconductor substrate; Forming an impurity layer of the opposite conductivity type to the semiconductor substrate; forming an insulating film on the impurity layer; and forming an opening in the insulating film to make contact with the impurity layer. Forming a silicon film containing an impurity of the same conductivity type as that of the impurity layer on the impurity layer in the opening and on the groove side surface of the semiconductor substrate exposed in the opening; Forming a metal film on the silicon film on the impurity layer in the portion, forming a metal silicide film by reacting the silicon film and the metal film by performing a heat treatment, and forming a metal silicide film in the opening portion. Con Burying the transfected material, characterized by comprising the step of forming the contact material and the contact to a wiring layer on the insulating film.

Further, in the method of manufacturing a semiconductor device according to the present invention, there is provided a method of forming an element isolation region by burying an insulating film in a groove provided in a semiconductor substrate, and forming the semiconductor substrate so as to sandwich the element isolation region. Forming an impurity layer of the opposite conductivity type to the semiconductor substrate, forming an insulating film on the impurity layer, and forming a contact with the impurity layer sandwiching the element isolation region. Forming an opening over both the impurity layer and the element isolation region; and forming the opening on the impurity layer in the opening and the groove side surface of the semiconductor substrate exposed in the opening. Forming a silicon film containing an impurity of the same conductivity type as the impurity layer, forming a metal film on the silicon film on the impurity layer in the opening, and performing heat treatment. Characterized by comprising a step of forming a metal silicide film by reacting a con film and the metal film, and a step of embedding a wiring material in the opening.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. First, a semiconductor device according to a first embodiment of the present invention will be described. FIG. 1 is a sectional view showing the structure of the semiconductor device according to the first embodiment.

As shown in FIG. 1, a p-type semiconductor substrate 2
Is formed with an STI4 as an element isolation region, and an element such as an n-channel MOS transistor (not shown) is formed in an element region surrounded by the STI4. An n + diffusion layer 6 serving as a drain of the n-channel MOS transistor is formed between the STIs 4, and an insulating film 8 made of a silicon oxide film, BPSG, or the like is formed on the entire surface of the semiconductor substrate 2.

On the n + diffusion layer 6, a contact hole is formed by opening the insulating film 8. Here, in the formation of this contact hole, a positional shift may occur in the resist pattern due to misalignment of a photomask or the like during lithography. If the resist pattern is displaced, the etching at the time of opening the contact hole becomes n +
ST that is off the diffusion layer 6 and exists next to the n + diffusion layer 6
It reaches a part of I4. Thereby, originally, n +
The contact hole to be formed only on diffusion layer 6 is n
There is a possibility that the semiconductor layer 2 may fall off on the + diffusion layer 6 and reach the region 10 of the p-type semiconductor substrate 2 under the n + diffusion layer 6 where the impurity concentration is low. FIG. 1 shows a cross section of the semiconductor device in the case where a region surface 10 having a low impurity concentration is exposed below the n + diffusion layer 6 when a contact hole is formed.

A refractory metal silicide film, for example, titanium silicide (TiSi ₂ ) is formed on the n + diffusion layer 6 which is a horizontal portion in the contact hole, or on a part of the STI 4 which is also a horizontal portion in the contact hole. ) A film 12 is formed. In addition, a silicon film, for example, a polysilicon film 14 is formed on all side surfaces near the vertical including the region surface 10 having a low impurity concentration in the contact hole. This polysilicon film 14 is doped in advance with an impurity of the same conductivity type as n + diffusion layer 6, for example, phosphorus (P). Tungsten (W) 16 as a contact material is formed on the titanium silicide film and the polysilicon film in the contact hole.

Further, a wiring layer 18 made of an aluminum film or the like is formed on the insulating film 8. The wiring layer 18 is electrically connected to the n + diffusion layer 6 with low resistance via the tungsten 16 and the titanium silicide film 12.

In a semiconductor device having such a structure,
Since titanium silicide 12 is formed between n + diffusion layer 6 and tungsten 16 in the contact hole, low resistance is realized between n + diffusion layer 6 as the drain and tungsten 16 as the contact material. You. On the other hand, since polysilicon film 14 is formed on region surface 10 having a low impurity concentration below n + diffusion layer 6 which causes a leakage current, it is necessary to suppress a leakage current generated between region surface 10 and tungsten 16. Can be.

FIG. 1 shows a case where the position of the contact hole is shifted on the n + diffusion layer 6 and the contact material such as tungsten 16 reaches a part of the STI 4, but the position is shifted. Otherwise, titanium silicide 12 is formed only on n + diffusion layer 6.

As described above, according to the first embodiment, when forming the contact hole by opening the insulating film formed on the impurity diffusion layer of the semiconductor substrate, the contact hole is formed from above the impurity diffusion layer. Even if the formation position is shifted, no leak current occurs between the contact material connected to the wiring layer and the semiconductor substrate, and a low-resistance contact can be formed between the contact material and the impurity diffusion layer. It is.

Next, a method of manufacturing the semiconductor device according to the first embodiment will be described. 2 to 6 and FIG. 1 are cross-sectional views of respective manufacturing steps showing a method of manufacturing the semiconductor device according to the first embodiment.

As shown in FIG. 2, a desired resist pattern 20 is formed on the p-type semiconductor substrate 2 by photolithography.
Is formed, the semiconductor substrate 2 is etched by RIE to form a trench 22. After removing the resist pattern 20, a silicon oxide film is deposited on the entire surface of the semiconductor substrate 2 to fill the trench 22. Subsequently, as shown in FIG. 3, an extra silicon oxide film on the semiconductor substrate 2 is
Polishing and flattening by MP, S as an element isolation region
Form TI4.

Thereafter, an element such as an n-channel MOS transistor is formed on the element region surrounded by the STI 4. Here, as shown in FIG. 4, for example, phosphorus (P)
Are ion-implanted under predetermined conditions, and an n + diffusion layer 6 serving as a drain of the n-channel MOS transistor is formed between the STIs 4. Further, as shown in the figure, an insulating film 8 is deposited on the entire surface of the semiconductor substrate 2.

Next, as shown in FIG. 5, in order to make contact between the wiring layer formed on the insulating film 8 and the n + diffusion layer 6 on the semiconductor substrate 2, a resist is applied on the insulating film 8 and lithography is performed. After a desired resist pattern 24 is formed by the method, the insulating film 8 is opened by RIE to form a contact hole. The size of the contact hole is about 0.2 to 0.3 μm in length and width.

At this time, the resist pattern 24 may be misaligned due to misalignment of a photomask or the like during lithography. When the resist pattern 24 is displaced, the etching by RIE in the contact hole opening step is displaced on the n + diffusion layer 6, and n
+ It reaches a part of the STI 4 existing beside the diffusion layer 6. As a result, the contact hole which should be formed only on n + diffusion layer 6 is displaced on n + diffusion layer 6, and
There is a possibility that the surface of the p-type semiconductor substrate 2 under the n + diffusion layer 6 may reach the low impurity concentration region surface 10.

Therefore, following the above-described step shown in FIG. 5, after the resist pattern 24 is peeled off, as shown in FIG.
Polysilicon film 1 doped with phosphorus (P) in advance
4 is formed on the entire surface of the p-type semiconductor substrate 2 by LPCVD to a thickness of about 20 nm. In this film formation by the LPCVD method, n is a horizontal portion with respect to the substrate surface in the contact hole.
On the + diffusion layer 6, a film is deposited almost uniformly on the entire region including the region surface 10 which is a portion close to the vertical.

Further, a refractory metal such as titanium (T
i) A film 26 is deposited to a thickness of about 20 nm on the entire surface of the p-type semiconductor substrate 2 by a sputtering method. In the vapor deposition by the sputtering method, the titanium film 2 is formed on the n + diffusion layer 6 which is a horizontal portion.
6 is deposited to a thickness of about 20 nm, but is not so deposited on the area plane 10 which is a portion close to the vertical. The thickness of the titanium film 26 is not more than the thickness of the polysilicon film 14.

After the deposition of the titanium film 26, a temperature of 600.degree.
Heat treatment is performed at a temperature of about 00 ° C. By this heat treatment, the titanium film 26 and the polysilicon film 14 react to form titanium silicide (TiSi ₂ ) 12. At this time, the n + diffusion layer 6 which is a horizontal portion in the contact hole is formed.
In the above, since the thickness of the titanium film 26 and the thickness of the polysilicon film 14 are substantially the same, almost the entire film of the polysilicon film 14 becomes the titanium silicide 12 and the titanium silicide 1
Polysilicon film 14 hardly remains at the interface between 2 and n + diffusion layer 6. Therefore, low resistance is realized between n + diffusion layer 6 and the contact material embedded in the contact hole.

On the other hand, in the region 10 having a low impurity concentration below the n + diffusion layer 6 which causes a leakage current, the titanium film 26
Is deposited, the polysilicon film 14 is sufficiently left on the region surface 10 even when the titanium silicide 12 is formed, so that a leak current generated between the region surface 10 of the p-type semiconductor substrate 2 and the contact material is suppressed. be able to.

Next, a tungsten (W) film is formed by sputtering or CVD, and tungsten 16 serving as a contact material is buried in the contact hole. afterwards,
As shown in FIG. 1, a tungsten film on the insulating film 8,
The titanium silicide or titanium film 26 and the polysilicon film 14 are removed by dry etching or CMP. Then, an aluminum film is formed on the insulating film 8 and patterned by lithography to form the wiring layer 1.
8 is formed.

In the above-described process, the heat treatment was performed immediately after the titanium film 26 was formed. However, the present invention is not limited to this.
The heat treatment may be performed in any step after the formation of the titanium film 26. As described above, due to this heat treatment, the titanium film 26 and the polysilicon film 14 react to form titanium silicide (TiSi ₂ ) 12, and a low resistance is formed between the n + diffusion layer 6 and the tungsten 16 as a contact material. Is realized. On the other hand, in the region surface 10 under the n + diffusion layer 6 which causes a leakage current, the titanium film 26 is less deposited, so that even if the titanium silicide 12 is formed, the region surface 10
A sufficient polysilicon film 14 remains on the p-type semiconductor substrate 2
Leakage current between the region surface 10 and the contact material can be suppressed.

As described above, according to this method of manufacturing a semiconductor device, when an insulating film on an impurity diffusion layer such as a source or a drain is opened to form a contact hole, the impurity diffusion layer is misaligned in a lithography process. Even if the contact hole is displaced from above, no leak current occurs between the contact material embedded in the contact hole and the semiconductor substrate, and a low-resistance contact can be formed between the impurity diffusion layer and the contact material. .

Next, a semiconductor device according to a second embodiment of the present invention will be described. In the first embodiment, an example in which a contact hole is opened has been described. However, the present invention can be applied to an example in which a wiring connecting a diffusion layer sandwiching an STI is formed.

FIG. 7 is a sectional view showing a structure of a semiconductor device according to a second embodiment of the present invention. As shown in FIG. 7, an STI 34 is formed on the p-type semiconductor substrate 32,
An n + diffusion layer 36 is formed between the STIs 34 as a wiring layer. ST is provided between these n + diffusion layers 36.
I38 is formed. Further, an insulating film 40 made of a silicon oxide film, BPSG, or the like is formed on the entire surface of the semiconductor substrate 32.
Are formed.

The n + diffusion layer 36 and the STI 3
On 8, a wiring groove is formed by opening the insulating film 40. Here, in the formation of the wiring groove, if the etching of the insulating film 40 is excessively performed, the STI 38 is etched to reach a position deeper than the n + diffusion layer 36, and the p-type semiconductor substrate 32 below the n + diffusion layer 36 is etched. The wiring groove may be formed until the region surface 42 having a low impurity concentration is exposed. FIG. 7 shows a case where the region surface 42 having a low impurity concentration is exposed below the n + diffusion layer 36 when the wiring groove is formed.

Further, n +, which is a horizontal portion in the wiring groove,
A refractory metal silicide film, for example, a titanium silicide (TiSi ₂ ) film 44 is formed on the diffusion layer 36 or similarly on the STI 38 which is a horizontal portion in the wiring groove. In addition, a polysilicon film 46 is formed on all side surfaces near the vertical including the region surface 42 in the wiring groove. The polysilicon film 46 has an impurity of the same conductivity type as the n + diffusion layer 36,
For example, phosphorus (P) is doped in advance. Then, on the titanium silicide film 44 and the polysilicon film 46 in the wiring groove, tungsten (W) 48 as a wiring material is provided.
Are formed. This tungsten 48 is electrically connected to the n + diffusion layer 36 through the titanium silicide film 44 with low resistance.

In a semiconductor device having such a structure,
Since the titanium silicide film 44 is formed between the n + diffusion layer 36 and the tungsten 48 in the wiring groove, the n + diffusion layer 36 as the wiring layer and the tungsten 4 as the wiring material are formed.
8, the resistance can be reduced.

On the other hand, since the polysilicon film 46 is formed on the region surface 42 having a low impurity concentration below the n + diffusion layer 36 which causes the leakage current, the leakage current generated between the region surface 42 and the tungsten 48 is formed. Can be suppressed.

As described above, according to the second embodiment, when opening the insulating film on the impurity diffusion layer constituting the wiring layer and the like to form the wiring groove, excessive etching in the insulating film is required. Even when the wiring groove is formed deeper than the impurity diffusion layer due to the etching, no leakage current occurs between the wiring material embedded in the wiring groove and the semiconductor substrate, and a low current flows between the impurity diffusion layer and the wiring material. Resistive contacts can be formed.

Next, a semiconductor device according to a third embodiment of the present invention will be described. The third embodiment is an example in which the present invention is applied to a wiring in a memory cell array of a nonvolatile memory.

FIG. 8 is a plan view showing a configuration of a memory cell array according to the third embodiment, and shows a case where tungsten is used for a source wiring of a memory cell. As shown in FIG. 8, a word line 50 is wired in a row direction, and a wiring layer 52 made of aluminum (Al) or the like is wired in a column direction. A source wire 54 made of tungsten or the like is provided between the word lines 50, and a contact portion 56 for making a contact with a memory cell transistor is formed in the wiring layer 52.

FIG. 9 is a sectional view taken along line AA 'in FIG. 8, and FIG. 10 is a sectional view taken along line BB' in FIG. As shown in FIG. 9, a p-type semiconductor substrate 62 has a source n + diffusion layer 64 and a drain n + diffusion layer 64.
A diffusion layer 66 is formed. On a channel between the n + diffusion layer 64 and the n + diffusion layer 66, a floating gate 68 insulated from the channel is formed. On the floating gate 68, the word as a control gate insulated from the floating gate 68 is formed. Line 5
0 is formed.

An insulating film 70 is formed on the p-type semiconductor substrate 62 including the periphery of the floating gate 68 and the word line 50 as a control gate, and the opening of the insulating film 70 on the n + diffusion layer 66 is Tungsten 72 as a contact material in the contact portion 56 is formed. The wiring layer 52 is formed on the tungsten 72.
Is formed. The wiring layer 52 is electrically connected to the drain n + diffusion layer 66 via the tungsten 72 with low resistance. Further, on the n + diffusion layer 64, a source wiring 54 made of tungsten is formed.

In the structure as shown in FIG. 9, although not shown, similar to the first embodiment,
When an insulating film formed on the n + diffusion layer 66 in the semiconductor substrate 62 is opened to form a contact hole, the n + diffusion layer 6
6, even if the contact hole formation position is shifted from above,
No leakage current is caused by interposing a polysilicon film between tungsten 72 which is a contact material connected to 2 and the semiconductor substrate 62, and titanium silicide or the like is formed between tungsten 72 and n + diffusion layer 66. As a result, a low-resistance contact can be realized.

As shown in FIG. 10, an STI 74 is formed on the p-type semiconductor substrate 62, and the n + diffusion layer 64 is formed between the STIs 74. On the n + diffusion layer 64 and the STI 74, a wiring groove for etching the insulating film 70 to bury the source wiring 54 is formed. Here, in the formation of the wiring groove, if the insulating film 70 is etched deeply, the oxide film in the region of the STI 74 is excessively etched, and the upper surface of the STI 74 becomes deeper than the junction surface of the n + diffusion layer 64, and the n + diffusion Layer 64
Lower impurity concentration region surface 76 of p-type semiconductor substrate 62 below
There is a possibility that a wiring groove may be formed until the wiring is exposed.
FIG. 10 shows a case where the region surface 76 having a low impurity concentration is exposed below the n + diffusion layer 64 when the wiring groove of the source wiring 54 is formed.

In such a wiring groove, a refractory metal silicide film, for example, a titanium silicide film 78 is formed on the n + diffusion layer 64, which is a horizontal portion with respect to the substrate surface, or on the STI 74, which is also a horizontal portion. Is done. In addition, a polysilicon film 80 is formed on all side surfaces near the vertical including the region surface 76. This polysilicon film 80
Is doped in advance with an impurity of the same conductivity type as n + diffusion layer 64, for example, phosphorus (P).

The source wiring 54 made of tungsten is formed on the titanium silicide film 78 and the polysilicon film 80. This source wiring 54
Is electrically connected to the n + diffusion layer 64 through the titanium silicide film 78 with low resistance. Further, the source wiring 54
The wiring layer 52 made of aluminum or the like is formed thereon with the insulating film 70 interposed therebetween.

In the structure as shown in FIG.
As described in the second embodiment, the n + diffusion layer 64
Since the titanium silicide film 78 is formed between the n + diffusion layer 64 and the source wiring 54 made of a tungsten film, a reduction in resistance is realized.
On the other hand, since the polysilicon film 80 is formed on the region surface 76 having a low impurity concentration below the n + diffusion layer 64 that causes the leakage current, the leakage current generated between the region surface 76 and the source wiring 54 is suppressed. be able to.

As described above, according to the third embodiment of the present invention, when forming the contact hole by opening the insulating film formed on the impurity diffusion layer of the semiconductor substrate, the contact hole is formed from above the impurity diffusion layer. Even if the formation position of the contact hole is shifted, a leak current does not occur between the contact material connected to the wiring layer and the semiconductor substrate, and a low-resistance contact is formed between the contact material and the impurity diffusion layer. Is possible.

Further, when forming the wiring groove by opening the insulating film on the impurity diffusion layer constituting the source or the like, when the wiring groove is formed deeper than the impurity diffusion layer due to excessive etching in the etching step of the insulating film. Also in this case, no leak current occurs between the wiring material embedded in the wiring groove and the semiconductor substrate, and a low-resistance contact can be formed between the impurity diffusion layer and the wiring material.

In the above embodiment, the case where the element isolation region is formed by STI, in which the effect of the present invention is great, has been described. Similar effects can be obtained by using the present invention. For contact with the p + diffusion layer, polysilicon doped with an acceptor-type impurity such as boron (B) may be used. Furthermore, in the above embodiment, after forming a polysilicon film in the contact hole, a Ti film was formed on a part of the polysilicon film. However, cobalt (Co), nickel (Ni), antimony (Sb), etc. The same effect can be obtained when a metal that easily reacts with silicon (Si) is formed.

In the above embodiment, in particular, the STI
In the case where the element isolation region is formed by
The leakage current from the side surface of the TI can be suppressed, and the interface resistance is small, and the resistance of the contact material itself can be reduced.

[0058]

As described above, according to the present invention, when forming a contact hole or a wiring groove by opening an insulating film formed on an impurity diffusion layer of a semiconductor substrate, the contact connected to the wiring layer is formed. Device capable of forming a low-resistance contact between a contact material and a wiring material and an impurity diffusion layer without generating a leak current between the material or the wiring material and the semiconductor substrate, and a method of manufacturing the same. It is.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a cross-sectional view of each manufacturing step showing the method for manufacturing a semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a cross-sectional view of each manufacturing step showing the method for manufacturing a semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a cross-sectional view of each manufacturing step showing the method for manufacturing a semiconductor device according to the first embodiment of the present invention;

FIG. 5 is a cross-sectional view of each manufacturing step showing the method for manufacturing the semiconductor device of the first embodiment according to the present invention.

FIG. 6 is a cross-sectional view of each manufacturing step showing the method for manufacturing the semiconductor device of the first embodiment according to the present invention;

FIG. 7 is a cross-sectional view illustrating a structure of a semiconductor device according to a second embodiment of the present invention;

FIG. 8 is a plan view showing a configuration of a memory cell array in a nonvolatile memory according to a third embodiment of the present invention.

FIG. 9 is a sectional view taken along line AA 'in FIG.

FIG. 10 is a sectional view taken along line BB 'in FIG.

FIG. 11 is a cross-sectional view showing a structure of a conventional semiconductor device.

FIG. 12 is a sectional view showing the structure of another conventional semiconductor device.

[Explanation of symbols]

2 p-type semiconductor substrate 4 STI (element isolation region) 6 n + diffusion layer 8 insulating film 10 region region with low impurity concentration 12 titanium titanium silicide (TiSi ₂ ) film 14 polysilicon film 16 tungsten (W) 18) wiring layer 20 ... resist pattern 22 ... trench 24 ... resist pattern 26 ... titanium (Ti) film 32 ... p-type semiconductor substrate 34 ... STI 36 ... n + diffusion layer 38 ... STI 40 ... insulating film 42 ... low impurity concentration area surface 44 ... titanium silicide (TiSi ₂₎ film 46 ... polysilicon film 48 ... tungsten (W) 50 ... word lines 52 ... wiring layer 54 ... source wiring 56 ... contact portion 62 ... p-type semiconductor substrate 64 ... n + diffusion layer 66 ... n + diffusion layer 68 ... floating gate 70 ... insulating film 72 ... tungsten 74 ... STI 76 ... impurities Low degree area surface 78 ... titanium silicide film 80 ... polysilicon film

Claims (8)

[Claims] An impurity layer having a conductivity type opposite to that of the semiconductor substrate formed in the semiconductor substrate; an insulating film formed on the impurity layer; a wiring layer formed on the insulating film; An opening formed in the insulating film for embedding a contact material for contacting a layer and the wiring layer; a metal silicide film formed on the impurity layer in the opening; A silicon film containing an impurity of the same conductivity type as the impurity layer formed on the exposed surface of the semiconductor substrate; and a contact plug formed on the metal silicide film and the silicon film in the opening. A semiconductor device characterized by the above-mentioned. 2. An element isolation region formed by burying an insulating film in a groove provided in a semiconductor substrate, and an impurity layer of a conductivity type opposite to that of the semiconductor substrate formed to be sandwiched between the element isolation regions. An insulating film formed on the element isolation region and the impurity layer; and an insulating film formed on the impurity layer and the element isolation region in the insulating film so as to embed a wiring material connecting the impurity layers sandwiching the element isolation region. An opening formed over both of the above, a metal silicide film formed on the impurity layer in the opening, and a semiconductor substrate exposed surface below the impurity layer in the opening. A semiconductor comprising: a silicon film containing an impurity of the same conductivity type as an impurity layer; and a wiring formed on the metal silicide film and the silicon film in the opening. Location. A step of forming an impurity layer having a conductivity type opposite to that of the semiconductor substrate on the semiconductor substrate; a step of forming an insulating film on the impurity layer; and forming the insulating film to make contact with the impurity layer. Forming an opening in the opening; forming a silicon film containing impurities on the impurity layer in the opening and on the semiconductor substrate surface exposed in the opening; Forming a metal film on the silicon film on the impurity layer; reacting the silicon film with the metal film by performing a heat treatment to form a metal silicide film; and forming a metal in the opening. A method for manufacturing a semiconductor device, comprising: embedding. 4. A step of forming an element isolation region by burying an insulating film in a groove provided in the semiconductor substrate; and forming an impurity layer of a conductivity type opposite to that of the semiconductor substrate on the semiconductor substrate adjacent to the element isolation region. Forming, forming an insulating film on the impurity layer, forming an opening in the insulating film to make contact with the impurity layer, and forming an opening on the impurity layer in the opening. Forming a silicon film containing an impurity of the same conductivity type as that of the impurity layer on the groove side surface of the semiconductor substrate exposed in the opening; and forming a silicon film on the impurity layer in the opening in the opening. A step of forming a metal silicide film by reacting the silicon film and the metal film by performing a heat treatment, a step of embedding a contact material in the opening, and a step of forming a metal material on the insulating film. The method of manufacturing a semiconductor device characterized by comprising a step of forming the contact material and the contact to the wiring layer. 5. A step of forming an element isolation region by burying an insulating film in a groove provided in a semiconductor substrate; and forming an impurity layer of a conductivity type opposite to that of the semiconductor substrate on the semiconductor substrate so as to sandwich the element isolation region. Forming an insulating film on the impurity layer; and forming a contact with the impurity layer sandwiching the element isolation region on the impurity film on the impurity layer and the element isolation region. A step of forming an opening over both sides; and an impurity of the same conductivity type as the impurity layer is contained on the impurity layer in the opening and on the groove side surface of the semiconductor substrate exposed in the opening. A step of forming a silicon film, a step of forming a metal film on the silicon film on the impurity layer in the opening, and a step of reacting the silicon film with the metal film by performing a heat treatment. A method for manufacturing a semiconductor device, comprising: a step of forming a side film; and a step of embedding a wiring material in the opening. 6. The step of forming a silicon film, comprising:
6. The method for manufacturing a semiconductor device according to claim 3, wherein the method is a step of forming by a CVD method. 7. The method according to claim 3, wherein the step of forming the metal film on the silicon film is a step of forming by a sputtering method. 8. The semiconductor device according to claim 3, wherein the thickness of the metal film is set to be equal to or less than the thickness of the silicon film.
The method for manufacturing a semiconductor device according to any one of the above.