JP2000040752A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device which can be improved in disturbance characteristics without deteriorating it in write/erase characteristics. SOLUTION: A floating gate 4 of two-layered structure of a nonvolatile memory device is composed of a heavily doped upper film 4c and a lightly doped lower film 4a laminated through the intermediary of a diffusion preventive film 4b, where the lower film 4a is set lightly doped so as to be inverted in a disturbance state. Impurities contained in the upper film 4c are diffused into a polycrystalline silicon film 6a, and the lower film 4a is set lightly doped to be inverted in a disturbed state. With this setup, voltage drops that occurs each at erase (injection) and disturbance when a lower film is deleted and inverted can be set almost equal to each other, the nonvolatile memory device is improved in disturbance characteristics, less reduced in erase speed, and prevented from deteriorating in writing speed due to the depletion of an upper film at writing (discharge).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a nonvolatile memory element having a two-layer gate structure and a method of manufacturing the same, and more particularly to a technique which is effective when applied to improvement of the disturb characteristics of the nonvolatile memory element. is there.

[0002]

2. Description of the Related Art Some semiconductor memory devices have a two-layer gate structure including a control gate and a floating gate. In this memory device, charge is injected into or extracted from the floating gate, and the charge of the floating gate is reduced. Information is stored depending on the presence or absence. Since the floating gate is surrounded by the insulating film and is not connected to the external wiring, the injected charge remains even when power is not applied, and does not require a power supply to hold information. Can be used as

FIG. 1 shows an example of such a storage element.
A tunnel insulating film 3, a floating gate 4, an interlayer film 5, and a control gate 6 are sequentially formed on the main surface of the semiconductor substrate 1 between the source region and the drain region 2 formed on the main surface of the semiconductor substrate 1 using single crystal silicon or the like. It is laminated.

A semiconductor device is used as a storage circuit in which a plurality of such storage elements are formed in an array. The configuration of such a storage circuit depends on the connection form of the plurality of storage elements, such as an AND type, a NAND type, a NOR type, and a DINOR.
Various circuit configurations such as types are considered.

In this storage element, the control gate 6
By applying a high bias between the semiconductor substrate 1 and the semiconductor substrate 1, electrons are injected or released into the floating gate 4 through the tunnel insulating film 3 to change the threshold value of the memory cell transistor. It is used for storing information, and high voltage is required for injection or emission of such electrons.

For this reason, some semiconductor devices are provided with a booster circuit to obtain this high voltage. However, as the power supply voltage becomes lower due to a demand for a lower voltage of the device, the booster circuit copes with the problem. In the case where it cannot be separated, or in order to secure a margin of the booster circuit, a substrate bias for applying a reverse potential to the substrate to form a high potential is employed.

In the case of a substrate bias, a potential is also applied to non-selected cells, so that an injection phenomenon into non-selected cells (hereinafter referred to as disturb) occurs.

For example, in the AND type circuit shown in FIG.
Erase operation from semiconductor substrate to floating gate
The writing operation is performed by emitting electrons by the FN tunnel current from the floating gate to the drain by injecting electrons by N (Fowler-Nordheim) tunnel current. FIG. 3 is a table showing the respective applied biases in the respective operations of the selected memory cell (1, 1) and the unselected memory cell (2, 2) in the memory cell array.

When erasing the selected memory cell (1, 1),
A voltage of 1.5 V is applied between the control gate and the semiconductor substrate to the unselected memory cells (1, 2) (2, 2). As a result, a weak electric field is applied to the tunnel insulating film, and the electric field gradually decreases due to the electric field. Is injected into the floating gate, and the stored information may be destroyed over time.
This is called erasure disturbance.

At the time of writing, -10 V is applied between the control gate and the semiconductor substrate in the unselected memory cell (2, 1), electrons are gradually released to the semiconductor substrate, and stored information is destroyed with time. There is a risk. This is called write word disturbance. Further, in the non-selected memory cells (1, 2), there is a write drain disturbance in which -2 V is applied between the control gate and the drain, and electrons are gradually discharged to the drain.

Also, at the time of reading, there is a read disturb in which 2.0 V is applied between the control gate and the semiconductor substrate in the unselected memory cell (2, 1), and electrons are gradually injected into the floating gate.

The problem of the disturb becomes more apparent when the tunnel insulating film is deteriorated by repeating writing and erasing, and the fluctuation of the threshold voltage Vth of the memory becomes large during the disturb.

[0013]

To improve such disturb characteristics, two policies have been considered so far. One is to improve the quality of the tunnel insulating film, and the other is to reduce the electric field applied to the tunnel insulating film during disturb.

As a method of reducing the electric field, a method of reducing the activation concentration of impurities in the floating gate and causing a voltage drop due to depletion to reduce the electric field has been proposed. For example, as the floating gate, a semiconductor thin film of polycrystalline silicon or the like is used to introduce and activate an impurity. The floating gate has a two-layer structure, the lower film has a low impurity concentration, and the upper film has a high impurity concentration. In this case, the write / erase characteristics are made uniform and the punch-through breakdown voltage is improved. Such a two-layer floating gate and low impurity concentration are disclosed in Japanese Patent Application Laid-Open Nos. 2-175883 and 2-295.
No. 170 or JP-A-7-115144.

However, in such a method of reducing the activation concentration of the impurity in the floating gate to cause a voltage drop by depletion to reduce the electric field, the write / erase speed is reduced when the cell is operated as a selected cell. Problem.

[0016] Disturbances other than readout still have a problem.

An object of the present invention is to provide a technique for improving a disturb characteristic of a semiconductor memory element having a two-layer gate structure without deteriorating write / erase characteristics.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0019]

Means for Solving the Problems Among the inventions disclosed in the present application, the outline of typical inventions will be briefly described.
It is as follows.

A floating gate of a nonvolatile memory element having a two-layer gate structure is formed by laminating an upper film having a high impurity concentration and a lower film having a low impurity concentration via a diffusion preventing film,
The impurity concentration is such that the inversion occurs when the lower layer film is disturbed.

Further, the lower film is formed by diffusing impurities of the upper film into a polycrystalline silicon film serving as a lower film, and forming the lower film as an impurity concentration which causes inversion in a disturb state.

According to the above-described means, the activation concentration in the lower film is set to a low concentration by arranging the floating gate on the upper film and the lower film via the diffusion preventing film, thereby setting the activation concentration in the lower film. Is set to a high concentration. As a result, the voltage drop due to depletion and inversion in the lower layer during erasing (injection) and disturbing can be made substantially the same, thereby improving the disturbing characteristics, alleviating the reduction in erasing speed, and increasing the upper layer during writing (emission). It is possible to prevent a decrease in writing speed due to depletion in the inside.

Hereinafter, embodiments of the present invention will be described.

In all the drawings for describing the embodiments, those having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

[0025]

FIG. 4 is a longitudinal sectional view showing a storage element of a semiconductor device according to an embodiment of the present invention.

On the main surface of the semiconductor substrate 1 between the source region and the drain region 2 formed on the main surface of the semiconductor substrate 1 made of single crystal silicon or the like, a tunnel insulating film 3 made of silicon oxide is formed to a thickness of 8 nm, An interlayer film 5 composed of an ONON film in which a silicon oxide film and a silicon nitride film are laminated is formed to a thickness of 15 nm.
A control gate 6 is formed by laminating a tungsten silicide film 6b to a thickness of 150 nm on a polycrystalline silicon film 6a having a thickness of 100 nm.

The floating gate 4 is formed by forming a thin 1 nm thick anti-diffusion film 4 made of silicon oxide on a 40 nm thick polycrystalline silicon film into which an impurity serving as the lower film 4a is not introduced.
4.5 × 10 ²⁰ / cm ³ which becomes the upper layer film 4c through the layer b.
And a 100-nm-thick polycrystalline silicon film into which phosphorus of sufficiently high concentration has been introduced, and impurities are introduced from the upper polycrystalline silicon film to the lower polycrystalline silicon film by thermal diffusion treatment.

Therefore, the impurity activation concentration in the lower film 4a is lower than that of the upper film 4c. By reducing the activation concentration of the impurities in the lower film 4a, a depletion phenomenon occurs in the floating gate 4. Thus, the electric field applied to the tunnel insulating film 3 is effectively reduced, and the disturb characteristics can be improved.

With respect to such disturb characteristics, consider the case where an n-type impurity is introduced into the floating gate and a positive bias is applied to the control gate with respect to the substrate (a negative bias in the case of a p-type impurity).

Since the space charge is accumulated in the depletion layer, it is considered that the depletion layer has a function similar to the capacitance, and the state of the depletion layer can be known from the capacitance characteristics. Therefore, in order to observe the depletion phenomenon, FIG. 5 shows a change in capacitance characteristics due to a difference in impurity concentration of the floating gate 4 by a pseudo static (or low frequency) capacitance measurement method.

With respect to between the n-type floating gate and the p-type semiconductor substrate, the horizontal axis shows the bias voltage Vfg applied to the floating gate, and the vertical axis shows the capacitance C between the floating gate and the semiconductor substrate. Capacity C
In the storage region where the bias voltage Vfg is negative, the capacitance is considered to be the oxide film capacitance of the tunnel insulating film, and Vfg = −
The ratio based on the oxide film capacitance Cox per unit area at 4 V is shown.

On the inversion side where the bias voltage Vfg is positive, if the impurity concentration in the floating gate is sufficiently high, the depletion phenomenon does not occur and the value of C / Cox on the inversion side is:
It is almost 1. On the other hand, when the impurity concentration is low, even if the semiconductor substrate side is inverted, the inside of the floating gate is depleted, and the capacitance value C becomes the storage region (Vfg <0).
When the gate voltage is raised and the inside of the floating gate is also inverted, the value of C / Cox approaches one. From the inversion-side capacitance characteristic, the activation concentration of the impurity in the lower layer film can be estimated by solving the Poisson equation.

When phosphorus is introduced as an impurity by using polycrystalline silicon for the floating gate, the impurity concentration introduced into the upper layer film 4c, the upper layer film 4c and the diffusion prevention film 4b
FIG. 6 shows the relationship between the lower layer film 4a and the activated impurity concentration. It is understood that the activation impurity concentration in lower film 4a can be easily reduced according to the method of the present embodiment.

This is because, in addition to the fact that the insulating film suppresses the diffusion of impurities, the rate at which impurities mainly diffusing at the boundaries of crystal grains are taken into the crystal and activated is small.

The voltage drop due to depletion in the lower film 4a at the time of writing, erasing, and disturbing can be known from the activation concentration of the impurity. FIG. 7 shows the relationship between the impurity concentration introduced into the upper layer film 4c and the voltage drop value when the AND-type circuit configuration is operated by applying the bias shown in Table 1.

When the impurity concentration is sufficiently high, no voltage drop occurs. The impurity concentration is reduced to, for example, 5 × 1
At about 0 ²⁰ / cm ³ , the activation concentration in the lower film is 1 × 1
0 ¹⁹ / cm ³ approximately and makes a voltage drop of about 1V during erase in this state, erasing disturbance 0.1 V, when read disturb occurs a voltage drop of 0.2V, the delay of the erase speed than improving disturb characteristic Is more problematic.

Since the applied voltage at the time of writing / erasing is basically higher than the applied voltage at the time of disturbing, the voltage drop at the time of writing / erasing is equal to or larger than the voltage drop at the time of disturbing. Would. This relationship does not change even if the thickness of the lower layer film is reduced to suppress the extension of the depletion layer.

Therefore, setting the activation concentration value is important for improving the disturb characteristics by reducing the activation concentration of the lower layer film. In the case of the present embodiment, the activation concentration of the impurity in the lower layer film is, for example, from 1 × 10 ¹⁹ / cm ³ to 1 × 10 ¹⁸ / c.
If it is less than about m ³ , inversion occurs even during disturb, and 2Φ which is twice the Fermi potential, which is the inversion potential,
Since a voltage drop occurs by f (1 → 0.7 V), the disturb characteristics can be improved, and the deterioration of the erase speed can be reduced.

On the other hand, if the concentration of phosphorus introduced into the upper layer film is excessively reduced, the vicinity of the interface between the upper layer film and the interlayer film is depleted at the time of writing (emission), and a voltage drop occurs to lower the writing speed.

Therefore, when the activation concentration of the impurity in the floating gate is reduced to such an extent that the inside of the floating gate starts to be inverted at the time of disturb, the disturb characteristic is improved and the decrease in the erasing (electron injection) speed is reduced. can do. These impurity concentration setting values vary depending on the device structure of the storage element and the applied voltage conditions.

In the present embodiment, if the concentration of phosphorus introduced into the upper layer film is set to 2 × 10 ²⁰ / cm ³ or less, the lower layer film is inverted even at the time of read / erase disturb as well as at the time of erasure, and the disturb characteristic is reduced. It is expected to be greatly improved. The disturb life, which usually becomes a problem at a low electric field of 10 MV / cm or less, can be improved by one to two digits if the electric field is reduced by 1 MV / cm. That is, if a voltage drop of 0.7 V occurs in the floating gate during the disturb, when the thickness of the tunnel insulating film is 7 nm, the electric field is reduced by 1 MV / cm, and the disturb life is improved by one to two digits. It is expected to do.

If the concentration of phosphorus to be introduced into the upper layer film of the floating gate is set to 3 × 10 ¹⁹ / cm ³ or less, a problem arises in that the interlayer film side in the upper layer film is depleted at the time of writing and the writing speed is reduced. I do. Therefore, in the present embodiment, the concentration of phosphorus introduced into the upper layer film is 3 × 1
That is, it is desirable to set it to about 0 ¹⁹ / cm ^{3 to} 2 × 10 ²⁰ / cm ³ . At this time, the activated phosphorus concentration in the lower film becomes about 1 × 10 ¹⁶ / cm ^{3 to} 1 × 10 ¹⁸ / cm ³ . Even if the concentration of the lower layer film is reduced as described above, sufficient free electrons exist in the upper layer film, so that the write / erase characteristics are not affected.

It should be noted that the impurity concentration of the upper layer film or the lower layer film may vary depending on the circuit configuration because the characteristics vary depending on the circuit configuration. However, since the overall tendency is common, the same policy is adopted. , The impurity concentration can be optimized for each circuit configuration.

Further, when the activation concentration in the lower layer film is reduced, the flat band voltage approaches 0, so that there is an advantage that the writing (emission) speed is increased. In the experiment of the present inventors, the concentration of phosphorus introduced into the upper layer film was set to 7 × 10 ²⁰
/ Cm ³ to 3 × 10 ²⁰ / cm ³ to about 1.
5 times faster.

The above-mentioned disturb life is used as an evaluation standard for erasure disturbance and read disturb characteristics, and in the case of erasure disturbance, the life time is defined as follows.

(Lifetime) = (erasing time) × (guaranteed number of rewrites) × (number of non-selected sectors). In this embodiment, 10 ms × 1 × 10 ⁵ ×
63 = 17.5 hr. When all bits in the block are rewritten with the number of times of rewriting to be guaranteed and then written in a state where the threshold value Vth is low, the voltage at the time of disturb is applied and the life time is reduced. Memory is destroyed (Vth shifts from low to high)
The bit failure rate is defined by the ratio of the number of bits to the total number of bits.

Similarly, in the case of the read disturb, the lifetime is defined as, for example, 10 years, and when the voltage at the time of the read disturb is continuously applied for 10 years, the number of bits at which the memory is destroyed with respect to the total bit number The bit failure rate is defined by the ratio.

Normally, to derive the bit failure rate, a method of predicting from a shorter time data obtained by electric field acceleration or the like is used. From the viewpoint of product reliability, it is necessary to determine the chip failure rate, which can be easily calculated from the bit failure rate.

As for the erasing speed, the lowering of the activation concentration of the impurity in the floating gate lowers the erasing speed by about half an order of magnitude as compared with the case where the impurity concentration is sufficiently high. However, when used for image processing and other purposes, or when used for recording media such as replacement of a hard disk, erasure is not performed in sector units, and batch erasure methods such as block units are often used. In such a batch erasing method, the erasing speed is not so important, and the writing speed and the reading speed are regarded as important. Therefore, it is considered that the features of the present invention will be utilized.

As a method of solving the problem, a method of reducing the applied voltage at the time of erasing by increasing the concentration of the lower layer film can be considered. However, in this method, when the lower layer film is formed of a polycrystalline silicon film into which no impurity is introduced, and the impurity is introduced by thermal diffusion from the upper film, it is difficult to increase the concentration because the activation rate is low.

When a high concentration of impurities is introduced into the lower layer film, the impurities may segregate at the interface between the floating gate and the tunnel insulating film, thereby deteriorating the reliability of the tunnel insulating film. For example, when phosphorus is used as an impurity, an over-emission tunnel current may accidentally flow at the time of emission, and the threshold value may be extremely reduced to cause a defective bit.

As described above, the invention made by the present inventor
Although a specific description has been given based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the gist of the invention.

For example, the present invention can be implemented as a storage device using a two-layer gate FET, which is the nonvolatile storage element, or as an MPU device in which the FET is formed in a storage region.

[0054]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) According to the present invention, there is an effect that the disturb characteristic of the nonvolatile memory element can be improved.

(2) According to the present invention, there is an effect that a decrease in the erasing speed can be moderated, and a decrease in the writing speed due to depletion in the upper layer film at the time of writing (emission) can be prevented.

(3) According to the present invention, when the floating gate is an n-type, all the disturb characteristics in which a positive voltage is applied to the floating gate with respect to the substrate can be improved (not limited to read disturb). Erasure disturbance is also improved).

(4) According to the present invention, there is an effect that the life of an element which becomes defective over time is improved.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing a storage element which is a main part of a conventional semiconductor device.

FIG. 2 is a circuit diagram showing an AND-type circuit configuration;

FIG. 3 is a table showing operating conditions of the memory circuit shown in FIG. 2;

FIG. 4 is a longitudinal sectional view showing a storage element which is a main part of the semiconductor device according to one embodiment of the present invention;

FIG. 5 is a diagram showing capacitance characteristics between a floating gate and a semiconductor substrate of a storage element, which is a main part of a semiconductor device according to an embodiment of the present invention.

FIG. 6 is a diagram showing an activation impurity concentration of a floating gate upper layer film and a lower layer film of a storage element which is a main part of the semiconductor device according to one embodiment of the present invention;

FIG. 7 is a diagram showing a relationship between an impurity concentration of a floating gate of a storage element, which is a main part of a semiconductor device according to an embodiment of the present invention, and a voltage drop.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Source region, Drain region, 3 ...
Tunnel insulating film, 4 floating gate, 4a lower film, 4b diffusion prevention film, 4c upper film, 5 interlayer film,
6 control gate, 6a polycrystalline silicon film, 6
b: silicide film.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Kazuhiro Komori 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Inside Semiconductor Division, Hitachi, Ltd. (72) Inventor Hideyuki Yashima Gojosomi, Gomi-cho, Kodaira-shi, Tokyo No. 20-1, Hitachi Semiconductor Co., Ltd. Semiconductor Division (72) Inventor Kimio Hara 5--20-1, Kamimizu Honmachi, Kodaira City, Tokyo Co., Ltd.Hitachi Manufacturing Co., Ltd. Semiconductor Division (72) Inventor ▲ Takano Junichi F-term (reference) 5-20-1, Josuihonmachi, Kodaira-shi, Tokyo, Japan 5F001 AA01 AA04 AA30 AA43 AA63 AB02 AD12 AD53 AE02 AE08 5F083 EP04 EP06 EP08 EP55 EP79 ER21 ER22 ER30 GA11 GA25 JA04 ZA13

Claims (10)

[Claims] 1. A semiconductor device provided with a nonvolatile memory element having a two-layer gate structure provided with a floating gate, wherein the floating gate has a high impurity concentration upper layer film and a low impurity concentration lower layer via a diffusion prevention film. And a lower layer having an impurity concentration that causes inversion in a disturbed state. 2. The semiconductor device according to claim 1, wherein the upper film has an impurity concentration that does not cause depletion in an electron emission state. 3. The semiconductor device according to claim 1, wherein a plurality of the nonvolatile memory elements are provided in a matrix and have an AND circuit configuration. 4. The semiconductor device according to claim 3, wherein the impurity concentration of the floating gate lower layer film is 1 × 10 ¹⁶ / cm ^{3 to} 1 × 10 ¹⁸ / cm ³ . 5. The semiconductor device according to claim ³ , wherein an impurity concentration of the upper layer film of the floating gate is 3 × 10 ¹⁹ / cm ^{3 to} 2 × 10 ²⁰ / cm ³ . 6. A method of manufacturing a semiconductor device provided with a nonvolatile memory element having a two-layer gate structure provided with a floating gate, wherein the floating gate comprises an upper film having a high impurity concentration and a lower film having a low impurity concentration. Forming a polycrystalline silicon film serving as the lower film, a step of forming a diffusion prevention film on the conductor film, and an upper film having a high impurity concentration. And diffusing impurities of the upper layer film into a polycrystalline silicon film serving as the lower layer film, and forming the lower layer film as an impurity concentration that causes inversion in a disturbed state. A method for manufacturing a semiconductor device. 7. The method according to claim 6, wherein the upper film has an impurity concentration that does not cause depletion in an electron emission state. 8. The method of manufacturing a semiconductor device according to claim 6, wherein a plurality of said nonvolatile memory elements are provided in a matrix and have an AND-type circuit configuration. 9. The method according to claim 8, wherein an impurity concentration of the floating gate lower layer film is 1 × 10 ¹⁶ / cm ^{3 to} 1 × 10 ¹⁸ / cm ³ . 10. The semiconductor device according to claim 8, wherein an impurity concentration of the upper layer film of the floating gate is 3 × 10 ¹⁹ / cm ^{3 to} 2 × 10 ²⁰ / cm ^3. Method.