JP2000040053A - Input-output processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the loads of a central processing unit and an input-output processor and also to improve their performance by reducing the number of processor communication times of transfer start. SOLUTION: This input-output processor 20 contains a channel program managing means 21 connected to a communication stack 22 and a channel program processing means 24 which refers to a channel program address table 23 and sets to an address converting means 25. Table 23 copies a channel program address table 12 of a central processing unit 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output processing device, and more particularly to a device for controlling data transfer between a central processing unit (CPU) and a peripheral device (peripheral) of a computer system.

[0002]

2. Description of the Related Art In a computer, especially a system such as a supercomputer, a CPU is connected to many peripheral devices, and the CPU issues a plurality of input / output instructions to these peripheral devices at the same time. The input / output processing device controls the data transfer between the peripheral device and the main storage device according to the issued instructions. In such a system, the performance of the input / output processing device, that is, the processing speed or capability is improved by reducing the load on the CPU by improving the overall data transfer capability.

A conventional input / output processing device is disclosed in, for example,
No. 78067 discloses a peripheral device control method.
FIG. 8 shows a block diagram of such a conventional example, and FIG. 9 shows an operation flowchart thereof.

Next, the configuration and operation of a conventional input / output processing device will be briefly described with reference to FIGS. A peripheral device control device 200 is connected to the central processing unit 100 via a bus 300. The central processing unit 100 includes a channel program registration unit 110, a channel program update unit 120, a channel program use permission notifying unit 130, channel program registration tables 140 and 1.
It is configured by the above channel program 150. On the other hand, the peripheral device control device 200
10, a channel program management means 220, a channel program processing means 230, and a channel program management table 240.

When a peripheral device activation factor occurs, the channel program updating means 120 creates all the channel program registration tables 140. This is because the table address is transferred to the bus 3 by the channel program registration instruction.
00 to the peripheral device control device 200. Further, the channel program updating means 120 activates the channel program use permission notifying means 130 when there is no usable program 150 when updating the registration table. The next time it becomes available, it notifies the channel program management means 220 of this.

[0006]

The prior art described above with reference to FIGS. 8 and 9 has the following problems. First, since the table address is output to the peripheral device control device 200 according to the channel program registration instruction, the address is limited to the width of the bus 300. If the width exceeds the width of the bus 300, the channel program registration instruction must be output in a plurality of times.

When a plurality of channels and a plurality of peripheral devices are connected to the peripheral device control device, it is necessary to notify the peripheral device control device of information for the determination. This information is called a channel number and a device number. If the channel number and the device number are included in the channel program registration instruction, the width of the bus 300 is also limited in this case. Therefore, the channel program registration instruction must be output a plurality of times. Also, since a channel program registration table for different channel numbers and device numbers must be created separately, it is necessary to output a channel program registration command separately.

Further, when the channel number and the device number are included in the channel program, it is possible to notify the peripheral device control device 200 of the channel number and the device number. It becomes difficult. This is because the channel number and device number are unknown until the channel program processing means is started.

Another problem is that multiple channels and devices cannot be activated simultaneously. In the related art, the next processing cannot be performed until the channel program processing means is activated and the processing is completed, and an interrupt is generated in the channel program updating means 120 of the central processing unit 100. The reason is that it is impossible to determine which channel program is the end interrupt without observing the order of the end report interrupts. In general, during transfer of a channel with one device, transfer start with another device connected to the channel is not performed. Therefore, even if a channel program for another channel or device exists, it cannot be processed and is kept waiting, resulting in a decrease in performance.

[0010] Therefore, an object of the present invention is to reduce the number of P-communications for starting transfer, thereby reducing the load on the CPU and IOP to improve the performance, and when a plurality of devices are connected to a channel. Another object of the present invention is to provide an input / output processing device that enables simultaneous transfer activation to a plurality of devices and improves the overall transfer capability.

[0011]

In order to solve the above-mentioned problems, the input / output processing device according to the present invention employs the following characteristic configuration.

(1) An input / output processing device, which is arranged between a central processing unit and a plurality of peripheral devices and controls data transfer between the central processing unit and the peripheral devices, includes a channel for the central processing unit. The same channel program address table as the program address table is provided in the input / output processing device, and when the central processing unit activates the input / output processing device, the logical channel number, the physical channel number, and the device number are transferred by inter-processor communication. Output processing device.

(2) The input / output processing device according to the above (1), wherein the input / output processing device further comprises an address conversion means.

(3) The input / output processing device according to (1) or (2), wherein the input / output processing means further comprises a channel program processing means.

(4) An input / output processing device which is disposed between a central processing unit and a plurality of peripheral devices and has a channel program management means and a channel program processing means for controlling data transfer therebetween. The input / output processing device, wherein the program processing means has a channel program address table having the same contents as the channel program address table of the central processing unit.

(5) The input / output processing device according to (4), wherein the channel program processing means is provided with an address conversion means.

(6) The input / output processing device according to the above (4) or (5), wherein the input / output processing device further has a communication stack and stores a start instruction for a physical channel number and a device number currently being processed.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of an input / output processing device according to the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 shows an outline of a system configuration of a preferred embodiment of an input / output processing device of the present invention. The input / output processing device 20 includes a central processing unit (CP) including a main storage device 30.
U) 10 and an inter-processor communication (P communication) is issued, and the central processing unit 10 also issues a P communication to the input / output processing device 20. Also, the input / output processing device 20 is a central processing unit 1.
0 main storage device 30 can be accessed. The input / output processing device 20 is connected to the channel 40 of the physical channel number PC # 0 and the PC
# 1 channel 41 is provided. Peripheral device 51 of device number DV # 0 and peripheral device 52 of DV # 1 are connected to channel 40. In addition, DV #
2 peripheral devices 53 are connected.

FIG. 2 is an operation block diagram of the central processing unit 10 and the input / output processing unit 20 shown in FIG. FIG.
5 is a flowchart showing the transfer of signals between the central processing unit 10 and the input / output processing unit 20.

As shown in FIG. 2, the central processing unit 10 includes a channel program creating / managing unit 11, a channel program address table 12, and a channel program 13
Having. The input / output processing device 20 includes a channel program management unit 21, a communication stack 22, a channel program address table 23, a channel program processing unit 24, and an address conversion unit 25.

Here, the channel program address table 12 and the channel program address table 23
Are registered in advance. One example is shown in FIG.
Shown in Each word in the table represents an LC #. The first bit of the word indicates the presence / invalidity of the channel program. The start address of the channel program is stored in the address field. The channel program address tables 12 and 23 are set when the input / output processing device 20 is initialized.

When a transfer factor with the peripheral devices 51-53 shown in FIG. 1 occurs, the channel program creating / managing means 1
1 is a currently used LC # among valid LCs registered in the channel program address table 12.
And creates a channel program 13 at a corresponding address on the main storage device 30. I / O processor 20
Is started by issuing inter-processor communication (P communication) carrying LC #, PC #, and DV #.

The channels 40 and 41 transfer the determined address space of the main storage device 30 and the determined peripheral devices 51 to 53 in accordance with the combination of the address set in the address conversion means 25 and the PC # and DV #. Do.

The peripheral device 51 of the address conversion means 25
FIG. 7 shows an example of the case where the transfer from −53 to the main storage device 30 is performed. The data registers 81-84 have PC #,
Set DV #. In each word of the memory 89, PC #,
A transfer address corresponding to DV # is set. The PC # and DV # that have been transferred together with the transfer data from the channel are stored in the data register 80, and the output thereof is sent to the data comparator 85-8
8 is compared with the contents of data registers 81-84. If they match, the corresponding address is output from the memory 89 and becomes the address of the main storage device 30. Main storage device 3
0 to the peripheral devices 51-53 also in the case of PC #, D
This is the same except that the relationship between V # and the address is reversed.

When a new transfer factor occurs, P communication is issued from the central processing unit 10 to the input / output processing unit 20 using another LC # regardless of the transfer so far, and the channel is activated by the same operation. Can be hung. In this case, even if the channels are the same, the DV # may be different.

If the transfer with the peripheral device currently being transferred is interrupted due to, for example, the circumstances of the peripheral device, another DV
Transfer with the peripheral device # is started. When the transfer is completed, the channel program processing means 24 raises a termination interrupt to the channel program management means 21, and the channel program management means 21 reports the completion by placing the LC # on the P communication to the central processing unit 10. When receiving the P communication, the channel program creating / managing means 11 knows that the channel program of the corresponding LC # has been completed.

The preferred embodiment of the input / output processing device of the present invention has been described above in detail. However, the present invention should not be limited to such an embodiment, and various modifications can be made depending on the application.

[0029]

As will be understood from the above description, according to the input / output processing apparatus of the present invention, the activation of the channel causes the logical channel number, the physical channel number, and the device number to be in the P communication, so that the address is assigned. There is no need, and even if the address is large, one-time P communication is sufficient. Further, a plurality of transfer activations can be simultaneously performed on a plurality of devices under the same physical channel with respect to a plurality of devices.
Thus, the total transfer capability can be increased for efficient transfer.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating the relationship between an input / output processing device of the present invention and another device.

FIG. 2 is a block diagram for explaining the configuration of the input / output processing device of the present invention and the operation of the central processing unit.

FIG. 3 is a flowchart for explaining the operation of the apparatus of FIG. 2;

FIG. 4 is an example of a communication format of the input / output processing device of the present invention.

FIG. 5 is a communication format of a conventional device in comparison with the communication format of FIG. 4;

FIG. 6 is an example of a channel program address table of the input / output processing device of the present invention.

FIG. 7 is a block diagram of an example of an address conversion unit of the input / output processing device of the present invention.

FIG. 8 is a block diagram of a conventional example.

FIG. 9 is a flowchart of the conventional example of FIG.

[Explanation of symbols]

Reference Signs List 10 central processing unit (CPU) 20 input / output processing unit (IOP) 12, 23 channel program address table 21 channel program management unit 22 communication stack 24 channel program processing unit 25 address conversion unit 51, 52, 53 peripheral device

Claims (6)

[Claims] 1. An input / output processing device which is arranged between a central processing unit and a plurality of peripheral devices and controls data transfer between the central processing unit and the peripheral devices. The same channel program address table as the address table is provided in the input / output processing device, and when the central processing unit activates the input / output processing device, the logical channel number, the physical channel number, and the device number are passed by inter-processor communication. Characteristic input / output processing device. 2. The input / output processing device according to claim 1, wherein said input / output processing device further includes an address translation unit. 3. The input / output processing means further comprises a channel program processing means.
2. The input / output processing device according to claim 1. 4. An input / output processing device which is disposed between a central processing unit and a plurality of peripheral devices and has a channel program management means and a channel program processing means for controlling data transfer between the two. The input / output processing device, wherein the processing means has a channel program address table having the same contents as the channel program address table of the central processing unit. 5. An input / output processing apparatus according to claim 4, wherein said channel program processing means is provided with an address conversion means. 6. The input / output processing device further includes a communication stack, and stores a start instruction for a physical channel number and a device number currently being processed.
Or the input / output processing device according to 5.