JP2000037036A - Power-saving driving circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce wasteful power consumption generated in an intermittent drive by a stabilizing capacitor. SOLUTION: When a power stabilizing circuit REG1 conducting intermittent driving is turned off, electric charges accumulated in a power stabilizing capacitor C3 are cut off from the power stabilizing circuit REG1 and a ranging ICDMIC by a diode Di and a switching means SWT, therefore the wasteful discharging of the capacitor C3 can be reduced. It is thus possible to reduce the current and time required to charge the power stabilizing capacitor C3 when the power stabilizing circuit REG1 is turned on again.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power saving driving circuit used for a battery-operated small electronic device.

[0002]

2. Description of the Related Art For example, a light projection type in which pulsed light is projected on an object, and reflected light from the object is received by a light receiving section disposed at a predetermined base line distance from the light projecting section to perform distance measurement. In a distance measuring device (sensor), if the distance measuring operation is repeated continuously at a high speed in order to improve the distance measuring accuracy, a large amount of power is consumed.

As a method of reducing the power consumption of a system using such a sensor, a configuration in which a distance measurement operation is performed intermittently as shown in FIGS.

[0004] The details are as follows. Power supply voltage output circuit 101 composed of a constant voltage circuit, DC converter, etc.
A control signal P101 for making the control terminal (hereinafter, referred to as “CNT terminal”) an active state for a short time (for example, about 5 ms) is given at a relatively long time interval (for example, about 1 s) (see P101 in FIG. 6). Each control signal P
When the output voltage Vreg of the power supply voltage output circuit 101 is stabilized during the active period performed by the power supply 101, the distance measuring IC provided in the distance measuring module DMM
A signal P102 for performing a distance measuring operation is supplied to the MES terminal of the DMIC (hereinafter, referred to as "DMIC") to operate the DMIC (see Vreg and P102 in FIG. 6). When the distance measuring operation is completed, the output of the signal P102 is stopped. In FIG. 5, E is a power supply battery, CPU is a control circuit, X101 is a crystal oscillator, R101 and R102 are resistors, Tr101 is a transistor, IRED is a light emitting element, SPD is a light receiving element for distance measurement, and T is an object to be detected. It is.

[0005]

Normally, as shown in FIG. 5, a relatively large-capacity capacitor C103 is provided on the power supply line of the distance measuring module DMM in order to stabilize the power input to the DMIC. In the vicinity of. Also, a capacitor C102 for stabilizing the output is provided on the output side of the power supply voltage output circuit 101.

Therefore, when the power supply voltage output circuit 101 and the like are simply driven intermittently as described above, when the power supply voltage output circuit 101 is turned off, the capacitors C102, C1
The electric charge stored in the device 03 is discharged by the DMIC or other elements. Therefore, every time the power supply voltage output circuit 101 is operated, the capacitors C102 and C10
3 must be recharged. Therefore, each time the power supply voltage output circuit 101 operates, the capacitor C1
02, a large charging current flows for charging C103, and despite the intermittent driving, the overall average current consumption does not decrease so much, and there is a problem that high-speed driving cannot be performed (FIG. 6i). reference). That is, the charging current ic of the capacitors C102 and C103 is larger than the sum of the operating current io of the DMIC and the current ip of the IRED.

This problem is not limited to the above-described distance measuring system, but is a common problem in intermittent drive circuits including a load circuit having a power supply stabilizing capacitor and a power supply intermittently driven.

[0008]

SUMMARY OF THE INVENTION According to the present invention, there is provided a power supply apparatus comprising: a first power supply circuit for intermittently supplying a power supply voltage to a first load circuit via a first power supply line; The first prohibiting means prohibits the charge stored in the first capacitor provided between the first power supply line and the low potential side of the power supply from moving to the first load circuit, Prohibition means prohibits the charge stored in the first capacitor from moving to the first power supply circuit. Therefore, even when the first power supply circuit does not supply the power supply voltage, it is possible to reduce the discharge of the charge of the first capacitor, and the first power supply circuit supplies the first power supply voltage when the first power supply circuit supplies the power supply voltage. The current for recharging the capacitor can be reduced, and power can be saved. That is, the effect of power saving by intermittent driving increases.

The first inhibiting means is a first switching means, and the first load circuit, the first power supply circuit and the first
Further comprising a control circuit for controlling the operation of the switching means, the control circuit turning on the first switching means in response to the start of the operation of the first power supply circuit and supplying the power supply voltage to the first load circuit. And the first load circuit is driven after a desired time has elapsed since the first switching means was turned on. Therefore, after the power supply voltage is supplied and the first load circuit is stabilized, the first load circuit is driven. Therefore, in addition to the above effects, the stable operation of the first load circuit can be achieved.

[0010] A second load circuit intermittently supplies a power supply voltage via a second power supply line to a second load circuit that operates in accordance with the measurement result of the measurement means, using the first load circuit as a measuring means. When the power supply circuit does not supply the power supply voltage, the charge stored in the second capacitor provided between the second power supply line and the low potential side of the power supply moves to the second load circuit. The second switching means inhibits, the third inhibiting means inhibits the electric charge stored in the second capacitor from moving to the second power supply circuit, and the control circuit includes the second load circuit. , Further controlling the operations of the second power supply circuit and the second switching means, turning on the second switching means with the start of the operation of the second power supply circuit, and providing the second load circuit with Supply the power supply voltage and After the desired time the second switching means from the on-driving the second load circuit.
Therefore, in addition to the above effects, the second load circuit is intermittently driven only when necessary, so that power can be saved.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present application is a first power supply circuit for intermittently supplying a power supply voltage to a first load circuit via a first power supply line; 1 power supply line and a low potential side of the power supply.
And first prohibiting means for prohibiting the electric charge stored in the first capacitor from moving to the first load circuit when the first power supply circuit does not supply the power supply voltage. A second prohibition unit that prohibits the charge stored in the first capacitor from moving to the first power supply circuit when the first power supply circuit does not supply a power supply voltage. In.

According to a second aspect of the present invention, in the first aspect, the first inhibiting means is a first switching means, and the first load circuit, the first power supply circuit, and the first Further comprising a control circuit for controlling the operation of the switching means, wherein the control circuit turns on the first switching means at the start of the operation of the first power supply circuit and supplies the power to the first load circuit. A voltage is supplied and the first load circuit is driven after a desired time has elapsed since the first switching means is turned on.

The invention according to claim 3 of the present application is the invention according to claim 2, wherein the first load circuit is a measuring means, and the second load circuit is operated in accordance with a measurement result of the measuring means. A second power supply circuit for intermittently supplying the power supply voltage via the power supply line, a second capacitor provided between the second power supply line and a low potential side of the power supply, When the second power supply circuit does not supply the power supply voltage, the electric charge stored in the second capacitor is stored in the second power supply circuit.
A second switching means for prohibiting the transfer to the load circuit, and when the second power supply circuit does not supply a power supply voltage, the electric charge stored in the second capacitor is supplied to the second power supply circuit. A third prohibition unit for prohibiting movement to a circuit, wherein the control circuit further controls the operations of the second load circuit, the second power supply circuit, and the second switching unit, At the start of the operation of the second power supply circuit, the second switching means is turned on to supply the power supply voltage to the second load circuit, and a desired time after the second switching means is turned on. After the lapse of time, the second load circuit is driven.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following example, a first load circuit adopting a distance measuring IC (hereinafter referred to as "DMIC") constituting a measuring means is shown. The first load circuit (measuring means) is not limited to a distance measuring means such as a DMIC, but can be changed as appropriate.

In FIG. 1, a power supply E is a battery and supplies power to a power supply stabilizing circuit REG1, a control circuit CPU and the like which constitute a first power supply circuit. Power supply stabilization circuit REG1
Is a control terminal CNT (hereinafter referred to as “CNT”) for operation control.
Terminal ". ), And when "1" is input here, R
The voltage Vreg of the out terminal is set to a predetermined voltage v0, and when the voltage becomes “0”, the Rout terminal is cut off and a standby mode with low power consumption is set. The voltage Vreg generated at the Rout terminal is a voltage output via the diode Di constituting the second prohibiting means, and is output to the first power supply line L1. Note that a regulator, a DC / DC converter, a switching regulator, or the like is used as the power supply stabilizing circuit REG1. The capacitors C1 and C2 are for stabilizing the operation of the power supply stabilizing circuit REG1.

The first switching means SWT constitutes first inhibiting means, and includes resistors R3, R4, R5, P-channel M
It comprises an OS transistor Q1, an N-channel MOS transistor Q2 and the like.

The distance measuring module DMM includes a DMIC, a light emitting diode IRED, and a light receiving element P for receiving light reflected from an object T of light output from the light emitting diode IRED.
S, resistors R1, R2, transistor Tr1, and operation stabilizing capacitor C4.

When the MES terminal becomes "1", the DMIC causes the light emitting diode IRED to emit light and starts a distance measuring operation.
The ranging result is output from the DATA terminal, and when the MES terminal becomes "0", the standby state is established and the ranging operation is stopped. In the standby state, the light emitting diode I
Although the RED stops emitting light, it is assumed that a current of several mA continues to flow in this IC.

The switch SWR is a light emitting diode IRED.
When the switch is connected to the terminal a side, the current is supplied directly from the power source E. In this case, the light emitting diode IRE
The current flowing in D changes to affect the distance measurement accuracy,
Operation is possible even when the voltage of the power supply E decreases. Therefore,
When the power source is a battery as in this example, the battery life is extended. When the switch SWR is connected to the terminal b, the light emitting diode IRED is operated by the output of the power stabilizing circuit REG1. In this case, since the power supply voltage is stabilized, the power supply voltage is used, for example, when high ranging accuracy is required.

The capacitor C3 constitutes a first capacitor together with the capacitor C2 and stabilizes the operation of the DMIC similarly to the capacitor C4, and is provided between the power supply line L1 and the low potential side (ground side) of the power supply. It is.

The sum of the capacitance values of the capacitors C3 and C4 is set to be equal to or slightly larger than that of the capacitor C103 shown as the conventional example, and the capacitance of the capacitor C3 is so small as not to affect the operation performance of the DMIC. The capacitance >> the capacitance of C4. This ratio is usually C3:
C4 = 20: 1 is sufficient.

As described above, in this embodiment, the relatively large-capacity capacitor provided on the power supply input side of the conventional distance measuring module DMM is divided into two parts, and the DMI constituting the first load circuit is divided into two parts.
A capacitor having a small capacity is provided on the side close to C, and a capacitor having a large capacity is connected to the DM via the switching means SWT.
It is located far away from the IC.

X is a crystal oscillator, switches SW1 to SWn
Is a setting switch, and the control signal (P1, P2) output from the control circuit CPU, which will be described later,
2, P3, etc.).

In the above configuration, the capacitor C
3, C4 and the switching means SWT are provided to stably operate the DMIC.
It is desirable to arrange in the vicinity of C.

Next, the operation will be described with reference to FIG.

The control circuit CPU generates a pulse TP at a period of 0.5 seconds (t1) based on the output of the crystal oscillator X (see TP in FIG. 2). The period (t1) can be changed as appropriate, and is set as appropriate by a predetermined number of setting switches SW1 to SWn.

The control circuit CPU generates a pulse P1 having a pulse width t2 (from 500 microseconds to several milliseconds) from time (A) in synchronization with the rise of the pulse TP.
Output to EG1 (see P1 in FIG. 2).

The power supply stabilizing circuit REG1 starts operating in response to the input of the pulse P1, and starts operating to set the voltage Vreg at the terminal Rout to v0 (see Vreg in FIG. 2).

When the time (t3) from the start of the operation of the power supply stabilizing circuit REG1 to the time when the voltage Vreg at the terminal Rout becomes the predetermined voltage v0 and stabilizes, the control circuit C
The PU outputs a pulse P2 to the switching means SWT (see P2 in FIG. 2), turns on the transistors Q2 and Q1, and changes the output voltage Vreg of the power supply stabilizing circuit REG1 to DM.
Supply to IC.

Therefore, the voltage Vsw of the power supply terminal VinD of the DMIC becomes substantially Vreg (= v0) (FIG. 2 Vsw).
reference). Strictly speaking, the voltage slightly decreases due to the on-resistance of the P-channel MOS transistor Q1, but this problem can be solved by using the transistor Q1 with a small on-resistance.

When the voltage Vsw of the power supply terminal VinD of the DMIC is stabilized after the generation of the pulse P2 and the DMIC enters a steady state, that is, when the time (t4) elapses after the generation of the pulse P2, the control circuit CPU sets the DMIC. M
A pulse P3 is generated at the ES terminal (see P3 in FIG. 2).

The DMIC starts the distance measuring operation by the pulse P3, and the light emitting diode IR for a predetermined time and a predetermined number of times.
The ED is operated, the reflected light from the object T is received by the light receiving element PS, the distance is detected by calculation, and information on the distance value and the presence or absence of the object is output from the DATA terminal.
U changes this information into a predetermined output form and outputs it to output terminal O
1. Output from O2. In FIG. 2, the object T is detected at the timing (D) on the time axis, the presence / absence signal is output from the terminal O1, and the presence / absence signal is continuously output by the latch signal (PL) inside the control circuit CPU. A case is shown in which the output signal is output as a detection signal from a terminal O2 (see O1, PL, and O2 in FIG. 2).

The control circuit CPU terminates the output of the pulses P2 and P3 in synchronization with the termination of the output of the pulse P1, and
End the distance measurement cycle.

At this time, the transistors Q1, Q2, Tr
1 is turned off, and the power supply stabilizing circuit REG1 is also turned off. Therefore, the charge accumulated in the capacitors C2 and C3 is prohibited from flowing to the power stabilizing circuit REG1 by the diode Di, and is allowed to flow to the DMIC by the switching means SWT. It is forbidden. Therefore, the capacitors C2 and C3
Is discharged only by the leakage current of each element, and only slightly decreases by Δv from the time (B) of FIG. 2V to the time (C). However, although the charge of the capacitor C4 is discharged by the DMIC, the amount is small since the capacitance of the capacitor C4 is small as described above.

Thereafter, when the pulses P1 and P2 are generated again, only a small amount of electric charge is stored in the capacitors C2 and C3, so that only a small amount of current is required to charge them. Further, since the capacitance of the capacitor C4 is reduced, the charging current and the charging time can be reduced. This state is shown in FIG. 2i. That is, the operating current io of the DMIC and the current ip of the IRED are different from those of the conventional example.
The charging current ic of C2 and C3 is kept small with respect to the sum of the currents.

As described above, when the intermittently driven power supply is turned off, the electric charge accumulated in the power supply stabilizing capacitor is separated from the power supply and the load circuit. The current required to recharge the capacitor can be reduced. Therefore, power saving can be achieved.
That is, the effect of power saving by intermittent driving increases. Therefore, when a battery is used as a power source, the frequency of battery replacement is low, which is particularly effective.

Further, during the intermittent driving, the load circuit is driven after the power supply voltage is supplied and the load circuit is stabilized, so that the load circuit can operate stably.

Next, an application example of the above-described example is shown in FIG.
The difference from the previous example is that when a detection signal is generated from the terminal O2 of the control circuit CPU according to the distance measurement result of the DMIC constituting the measuring means, the signal is transmitted to the second load circuit (in this example,
A transmission circuit is used. ).

In the figure, a power supply stabilizing circuit REG2 constituting a second power supply means is provided with a power supply stabilizing circuit REG.
1 and operates using a battery E as a power supply.
The diode Di in the power supply stabilizing circuit REG2 forms a third prohibiting unit. Second switching means SWT2
Has the same configuration as the switching means SWT. The transmission circuit TRSM transmits a signal input from the control circuit CPU by radio waves. The transmission medium is not limited to radio waves,
Light, ultrasonic waves, and the like can be appropriately changed.

The capacitors C33 and C34 have the same functions as the capacitors C3 and C4, respectively. Of course, also in this case, the capacitance is set so that the capacitance of C33 >> the capacitance of C34. Note that the capacitor C33 forms a second capacitor.

Next, the operation will be described again with reference to FIG. Note that the operation up to the point where the object T is detected is the same as that in the above example, and the description of the operation is omitted.

When the detection signal is output from the terminal O2, the control circuit CPU outputs a pulse P4 to output the power stabilizing circuit R
EG2 is operated (see FIG. 2 Rout2). Note that a signal output from the terminal O2 may be used as the pulse P4.

When the power supply stabilizing circuit REG2 operates, the capacitor C33 is charged and the power supply stabilizing circuit R
After the output voltage Vreg2 of the EG2 is stabilized, that is, when the time (t5) from when the pulse P4 is output to when the output voltage Vreg2 is stabilized, the switching means SWT2 is turned on by a pulse P5 having a predetermined pulse width, The output voltage Vreg2 of the power supply stabilizing circuit REG2 is supplied to the transmitting circuit TRSM via the power supply line L2. Note that the pulse P5 is output at a predetermined cycle while the detection signal is being output from the terminal O2, and the output is stopped when the detection signal from the terminal O2 disappears. Similarly, the operation may be performed intermittently while the second load circuit operates, that is, during the time including P5.

After a lapse of time (t6) until the voltage of the terminal Vsw2 is stabilized, the control circuit CPU outputs a transmission signal to the transmission circuit TRSM, that is, a detection signal P6 according to the distance measurement result of the DMIC. Transmits the signal to a receiving means (not shown).

When the output of the pulse P5 ends, the switching means SWT2 is turned off, and the transmission circuit TRSM stops operating. At this time, since the capacitor C33 is separated from the transmission circuit TRSM, the charge accumulated in the capacitor C33 is not wastefully discharged by the transmission circuit TRSM. Therefore, useless current can be reduced and power can be saved.

As described above, since the second load circuit (in this example, the transmission circuit) is intermittently driven according to the result of the distance measurement by the DMIC, power saving can be achieved.

Also, after the distance measurement of the DMIC is completed, that is, only when necessary, the second load circuit (the transmission circuit in this example) is intermittently driven, so that power can be saved. Note that D
The second load circuit may be intermittently driven while the MIC is performing distance measurement.

It should be noted that the control circuit CPU operates as the transmitting circuit TRSM.
Are not limited to the above, and can be changed as appropriate. For example, if the output of the measuring means is single, the transmission is not performed, and the transmission is performed only when the same output occurs continuously for a predetermined number of times, or the output having a large number of outputs out of the predetermined number of measurements is transmitted. You may.

In the above description, the transmission circuit is used as the second load circuit. However, the present invention is not limited to this. For example, a data logger, a printer, a CCD camera, and a video recording device for recording a captured image on a video tape may be used. Good.

Further, the control circuit CPU has a built-in clock function for measuring the time using the output of the crystal oscillator X, and all functions except the clock function are stopped during a predetermined time period when it is not necessary to operate the load circuit. Then, the power consumption can be further reduced. For example, when the present invention is used in a system that only detects an intruder in a room at night or on a holiday, measurement is not required in other time zones, and in this time zone, all functions except the clock function are stopped. .

The power supply stabilizing circuit REG1 (REG
As shown in FIG. 4, when a regulator REG3 having no diode at the output terminal, that is, a regulator in which the voltage of C3 is discharged by REG3 even when the CNT terminal becomes “0” is used as shown in FIG. The same effect as described above can be obtained by providing a switching means SWT3 having the same configuration as that of the switching means SWT between the output terminal of the power supply stabilizing circuit REG1 and the capacitor and performing on / off operation by the pulse P1.

[0052]

According to the present invention, even when the first power supply circuit does not supply the power supply voltage, the charge discharge from the first capacitor can be reduced, and the first power supply circuit supplies the power supply voltage. In this case, the current for recharging the first capacitor can be reduced, and power saving can be achieved. That is, the effect of power saving by intermittent driving increases.

The first inhibiting means is first switching means, and the first load circuit, the first power supply circuit, and the first
Further comprising a control circuit for controlling the operation of the switching means, the control circuit turning on the first switching means in response to the start of the operation of the first power supply circuit and supplying the power supply voltage to the first load circuit. And the first load circuit is driven after a desired time has elapsed since the first switching means was turned on. Therefore, after the power supply voltage is supplied and the first load circuit is stabilized, the first load circuit is driven. Therefore, in addition to the above effects, the stable operation of the first load circuit can be achieved.

The first load circuit is used as a measuring means, and the second load circuit which operates according to the measurement result of the measuring means is supplied intermittently with a power supply voltage via a second power supply line. When the power supply circuit does not supply the power supply voltage, the charge stored in the second capacitor provided between the second power supply line and the low potential side of the power supply moves to the second load circuit. The second switching means inhibits, the third inhibiting means inhibits the electric charge stored in the second capacitor from moving to the second power supply circuit, and the control circuit includes the second load circuit. , Further controlling the operations of the second power supply circuit and the second switching means, turning on the second switching means with the start of the operation of the second power supply circuit, and providing the second load circuit with Supply the power supply voltage and After the desired time the second switching means from the on-driving the second load circuit.
Therefore, in addition to the above effects, the second load circuit is intermittently driven only when necessary, so that power can be further saved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of FIG. 1;

FIG. 3 is a circuit diagram showing another embodiment of the present invention.

FIG. 4 is a circuit diagram showing still another embodiment of the present invention.

FIG. 5 is a circuit diagram showing a conventional intermittent drive device.

FIG. 6 is a timing chart for explaining the operation of FIG. 5;

[Explanation of symbols]

DMIC First load circuit, measuring means L1 First power supply line REG1 First power supply circuit C3 First capacitor SWT First inhibiting means, first switching means Di Second inhibiting means CPU control circuit TRSM 2 load circuit REG2 2nd power supply circuit C33 2nd capacitor SWT2 3rd inhibition means L2 2nd power supply line

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2F065 DD01 FF12 GG07 JJ15 NN20 PP22 QQ47 2F112 AD01 BA04 CA20 5G065 AA01 DA04 DA07 EA02 FA01 FA05 GA03 GA06 HA16 JA07 KA02 KA05 LA07 MA07 MA10 NA01

Claims (3)

[Claims] A first power supply circuit for intermittently supplying a power supply voltage to a first load circuit via a first power supply line; a first power supply line and a low potential side of the power supply; And a first capacitor provided between the first power supply circuit and the first power supply circuit. When the first power supply circuit does not supply a power supply voltage, the charge stored in the first capacitor moves to the first load circuit. First prohibiting means for prohibiting, and when the first power supply circuit does not supply a power supply voltage, prohibiting the electric charge stored in the first capacitor from moving to the first power supply circuit. A power-saving drive circuit comprising: a second prohibition unit. 2. The device according to claim 1, wherein the first prohibiting means is a first switching means, and controls operations of the first load circuit, the first power supply circuit, and the first switching means. The control circuit further turns on the first switching means when the first power supply circuit starts operating.
A power supply driving circuit for supplying the power supply voltage to the load circuit and driving the first load circuit after a lapse of a desired time from turning on the first switching means. 3. The method according to claim 2, wherein the first load circuit is a measuring unit, and the second load circuit operates according to a measurement result of the measuring unit via a second power supply line. A second power supply circuit for intermittently supplying a power supply voltage, a second capacitor provided between the second power supply line and a low potential side of the power supply, and a second power supply circuit. When the power supply voltage is not supplied, second switching means for inhibiting the charge stored in the second capacitor from moving to the second load circuit, and the second power supply circuit reduces the power supply voltage. A third prohibiting unit for prohibiting the electric charge stored in the second capacitor from moving to the second power supply circuit when the power supply is not supplied; Circuit, the second power supply circuit and the upper Further controlling the operation of the second switching means, turning on the second switching means with the start of the operation of the second power supply circuit, and supplying the power supply voltage to the second load circuit, A power saving drive circuit for driving the second load circuit after a desired time has elapsed since the second switching means was turned on.