JP2000036569A - Structure of semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate contamination due to an outward diffusion of a ferroelectric by forming an amorphous semiconductor layer formed on a ferroelectric film of Ge, thereby simply finely micromachining a structure. SOLUTION: A conventional MOSFET is formed on a surface of a silicon substrate, W is used as a lower layer wiring, an interlayer insulating film is deposited, and then a laminated film of an amorphous Ge, a ferroelectric film, an IrO2 and W. To form the amorphous Ge of the fourth layer, it is preferable not to adopt a reduced atmosphere like a sputtering method or an electron beam vapor deposition so as not to deteriorate the characteristics by reducing an oxide ferroelectric. Then, an SiO2 mask is formed on the deposited film of the four layers, and a gate is patterned by dry etching. Thereafter, an n type impurity is implanted by an ion implanting method to form a source and a drain. Thus, a structure becomes simple, and easily finely micromachined. A stress by heat treating or polarized reversing characteristic according to outer diffusion of a constituting element is not degraded.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a structure of a semiconductor device,
In particular, it relates to the structure of a nonvolatile storage element.

[0002]

2. Description of the Related Art Reference: Non-Volatile FCG (Ferroelect
ric-Capacitor and Transistor-GateConnection) Memor
y Cell with Non-Destructive Read-Out Operation, Sy
mposium on VLSI Technology, 1996, pp. 56-57 Authors: T. Katoh, S. Fujieda, Y. Hayashi, and T. K
unio Non-volatile memory device using ferroelectrics has a metal / ferroelectric / semiconductor FET (Metal / Ferroelectric / Semic
Onductor-FETs (MFS-FETs) have a strong demand for realization because they have a simple structure, are easily miniaturized, and can read data at high speed and nondestructively. However, the formation of MFS-FET
It is difficult to control the ferroelectric / semiconductor structure interface. In view of this point, the above-mentioned literature considers ferroelectric capacitors and FE
T-gate connected structure (Ferroelectric-Capacitor an
d transistor-Gate connection (FCG) storage element. The advantage of FCG elements is that ferroelectric capacitors and F
Since the ET is formed separately, the characteristics of the ferroelectric and the FET are not degraded, and the ratio between the capacitance and the gate capacitance of the ferroelectric capacitor can be freely set by changing the respective areas. It is easy to apply a voltage necessary for reversing the polarization of the body to the ferroelectric capacitor.

[0003]

However, the FCG element disclosed in the above-mentioned document is a metal / ferroelectric / metal / insulating film / semiconductor FET (Metal / Ferroelectric / Metal / Insulator / Serial).
MFMIS-FET), the laminated structure is more complicated than MFS-FET, and when an FCG element is formed,
MFS- because ferroelectric capacitor and MOSFET are separated
There is a problem that the structure like the FET is not simple and it is difficult to miniaturize.

In addition, the heat treatment in the LSI process has a problem that the constituent elements of the ferroelectric are diffused outward and contaminate the Si substrate, thereby easily deteriorating the characteristics of the MOSFET.

[0005]

According to the present invention, there is provided a lower metal gate formed on a semiconductor substrate, a ferroelectric film formed on the lower metal gate, and a ferroelectric film formed on the ferroelectric film. An amorphous semiconductor layer, a channel portion formed in the semiconductor layer, a source / drain region formed apart from the channel portion, and an extraction electrode from the source / drain. In the ferroelectric thin film transistor, the ferroelectric thin film transistor is characterized in that the amorphous semiconductor layer is made of Ge, so that the ferroelectric capacitor portion and the MOSFET portion can be realized by one element, so that the structure is simplified and the fineness is reduced. Easy to convert.

Further, since there is no high-temperature heat treatment after the formation of the ferroelectric film, there is no deterioration in the characteristics of the MOSFET on the Si substrate due to outward diffusion of impurities from the ferroelectric film and its laminated structure.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Numerical conditions such as materials used, processing temperature, processing time, film thickness and the like mentioned in the following description are only preferred examples within the scope of the invention. Therefore, it is not limited only to these conditions.

[0008]

First Embodiment An example of the present invention will be described below with reference to FIG.
This will be described with reference to FIGS.

The description of the first embodiment is based on the description of a normal MOSFET.
Is formed on the surface of the silicon substrate, W (tungsten) is used as a lower layer wiring, and a step after depositing an interlayer insulating film is performed.

FIG. 1 shows an amorphous Ge / ferroelectric film / IrO ₂ /
FIG. 4 shows a cross-sectional view in which an SiO ₂ mask is formed on a W laminated film.

The first layer of W is formed by a sputtering method. In this embodiment, the film thickness is 0.1 μm. W acts to lower the gate resistance. The material is not limited to W, Ta, M
O, TiN, Nb, V, TaN, TaSiN, TiW, TiWN, TiAlN, etc. may be used as a single layer or a multilayer film by combining two or more kinds of materials.

The second layer of IrO ₂ is formed by sputtering. IrO ₂ is used as a base when forming a ferroelectric thin film. Therefore, the suitable material differs depending on the ferroelectric material and its film forming method. In addition to IrO ₂ , Ir, Ru, Pt, Ru
O ₂ , SrRuO ₃ , La _1-x Sr _x CoO ₃ , SrMoO ₃ etc. in a single layer or 2
In some cases, a combination of two or more materials is used as a multilayer film. In this embodiment, IrO ₂ is used in a thickness of 0.1 μm.

The third layer is a high dielectric film, for example, Pb
ZrTiO ₃ , SrBi ₂ Ta ₂ O ₉ , Ba _x Sr _1-x TiO ₃ , Pb ₅ Ge ₃ O ₁₁ , Bi ₄ Ti
₃ O ₁₂ , (Pb _, La) TiO ₃ and the like. In this embodiment, SrBi ₂ T
a ₂ O ₉ is used, and the film thickness is 0.4 μm. For example, a material that is spin-coated by a sol-gel method is heat-treated at 450 ° C. to remove organic components, and is then formed by performing main firing at 800 ° C.

The fourth layer is made of amorphous Ge. For the film formation, a method that does not use a reducing atmosphere, such as a sputtering method or electron beam evaporation, is preferable in order to reduce the oxide ferroelectric and not deteriorate the characteristics. In this embodiment, the film is formed by electron beam evaporation and has a thickness of 0.4 μm.

After depositing up to four layers, an SiO ₂ mask is formed to pattern the gate. SiO ₂ film is made of SiH
Substrate temperature 20 by plasma CVD using ₄ / N ₂ O as source gas
Deposit at 0 ° C. The film thickness of the SiO ₂ mask, the SiO ₂ mask is set so as to leave 100~200nm at the end patterning the gate. In this embodiment, the thickness of the SiO ₂ mask is 0.8 μm. An SiO ₂ mask is formed by a normal photolithography process and a dry etching process.

FIG. 2 is a cross-sectional view after the pattern of the SiO ₂ mask is transferred to the laminated film of amorphous Ge / ferroelectric film / IrO ₂ / W by dry etching. The dry etching is performed by introducing Cl ₂ / Ar gas and generating plasma by high frequency power of 13.56 MHz.

FIG. 3 shows that an n-type impurity is introduced into the source and drain electrode portions of the ferroelectric MOSFET by ion implantation. In the ion implantation, impurities are introduced into the Ge region through the remaining film at the time of gate processing of the SiO ₂ mask. There are P, As, and Sb as n-type impurities.
More than two kinds of impurities are introduced in combination. In this embodiment, description is made using P as an impurity. At this time, the channel region is covered with a resist formed by known photolithography to prevent implantation of P ions. After the ion implantation, the resist is removed, and a heat treatment is performed at 400 ° C. for 5 hours in an N ₂ atmosphere to crystallize amorphous Ge into polycrystalline Ge.
At the same time, P in the source and drain regions is activated to form an n ⁺ region.

FIG. 4 is a cross-sectional view after the formation of the interlayer insulating film. As the interlayer insulating film, SiO ₂ is formed on the entire surface of the wafer by plasma CVD. In plasma CVD, deposition is performed at a substrate temperature of 200 ° C. using SiH ₄ / N ₂ O as a source gas. In this embodiment, the film thickness of SiO ₂ is
0.4 μm.

The process after processing the source and drain electrodes of the ferroelectric MOSFET is the same as that of a known LSI. That is, a through hole is formed, wiring processing of an Al alloy or the like is performed, and finally, the wiring is covered with a protective film.

FIG. 5 is a sectional view of the device after the process is completed. In the element structure of this embodiment, the high-temperature process at 400 ° C. or higher is performed only when the ferroelectric film is formed, and can be manufactured by heat treatment at 400 ° C. or lower after the ferroelectric film is formed. By this low-temperature process, the heat history after the ferroelectric film formation can be reduced, so that the dielectric characteristics of the ferroelectric material are not easily deteriorated.

Further, when Si is used for the semiconductor layer, an oxide film (SiO ₂ ) having a low dielectric constant is formed at the Si / ferroelectric interface by the heat treatment required in the manufacturing process, and the Si / SiO ₂ / ferroelectric It becomes a structure. Since SiO ₂ is more stable than oxide ferroelectrics,
Is for reducing the ferroelectric material. In the present invention, since Ge is used for the semiconductor layer, an oxide film having a low dielectric constant cannot be formed at the Ge / ferroelectric interface, and an ideal Ge / ferroelectric structure can be obtained. This is because Ge does not reduce the ferroelectric material because the oxide of Ge is more unstable than the oxide ferroelectric.

In this embodiment, Ge is used for the semiconductor layer. However, it is sufficient that an oxide film having a low dielectric constant is not formed at the semiconductor / ferroelectric interface. For example, Si _x Ge _1-x is set in the range of x <0.5. May be used.

The device according to the present invention utilizes the spontaneous polarization of the ferroelectric in the gate portion to control the carrier concentration in the channel portion of the MOS structure to perform a memory operation. FIG. 6 shows the hysteresis characteristic of SrBi ₂ Ta ₂ O ₉ which is the ferroelectric of the present embodiment, to facilitate the description of the operation of the present invention. That is, coercive electric field = 40 kV / cm, remanent polarization = 12 μC / cm ² , and relative dielectric constant = 200. The film thickness of SrBi ₂ Ta ₂ O ₉ used in this example is 0.4 μm.

The write and erase operations will be described with reference to FIGS. Writing is performed by applying 0 V to the source electrode and applying a writing voltage of -5 V to the gate electrode and releasing the drain electrode. At this time, SrBi ₂ Ta ₂ O _{9 under} the source electrode
Since the electric field intensity generated at this time is -125 kV / cm, the spontaneous polarization of SrBi ₂ Ta ₂ O ₉ can be sufficiently inverted to the saturation region as can be seen from FIG.

Erasing is performed by applying 0 V to the source electrode and 5 V to the gate electrode and releasing the drain electrode. As described in the write operation, the SrBi ₂ Ta ₂
Since the electric field intensity generated in O ₉ is 125 kV / cm, the spontaneous polarization of SrBi ₂ Ta ₂ O ₉ can be sufficiently inverted to the saturation region as can be seen from FIG.

As shown in FIG. 9, the actual control of carriers in the channel portion of polycrystalline Ge in writing and erasing is
Since the ferroelectric substance under the channel is spontaneous polarization, in the structure of the present invention, the non-vertical component of the spontaneous polarization is used. When the device of the present invention is miniaturized and the channel length is shortened, the spontaneous polarization of the ferroelectric under the channel can be sufficiently controlled even by the control method of this embodiment.

At the time of writing and erasing, if the source electrode and the drain electrode are set to 0 V and the writing voltage and the erasing voltage are applied to the gate electrode, respectively, the potential of the channel portion becomes non-vertical from the source electrode and the drain electrode. Since control can be performed by combining direction component electric fields, stronger spontaneous polarization can be generated.

Reading is performed by applying 0 V to the gate and source electrodes and 1 V to the drain electrode as shown in FIG. After writing is completed, the threshold of the ferroelectric MOSFET (Vt)
Becomes lower and becomes normally on as shown in FIG. After erasing, Vt> 0 (V), so that the ferroelectric MOSFET does not turn on under the read condition. Binary data reading is performed using the change in the drain current.

[0029]

Second Embodiment A second embodiment of the present invention will be described below with reference to FIGS.

In the description of the embodiment, a normal MOSFET is formed on the surface of a silicon substrate, and W (tungsten) is used as a lower wiring.
Is performed after the step of depositing the interlayer insulating film.

FIG. 12 shows an amorphous Ge / ferroelectric film / Ir
FIG. 2 shows a cross-sectional view of forming a stacked film of O ₂ / W.

The first layer of W is formed by a sputtering method. W acts to lower the gate resistance. W for material
Not limited to, Ta, Mo, TiN, Nb, V, TaN, TaSiN, TiW, TiW
In some cases, N, TiAlN, or the like is used as a multilayer film in a single layer or a combination of two or more materials. In this embodiment,
The thickness is set to 0.1 μm.

The second layer of IrO ₂ is formed by a sputtering method. IrO ₂ is used as a base when forming a high dielectric thin film. Therefore, suitable materials differ depending on the high-dielectric material and the method of forming the film, and in addition to IrO ₂ , Ir, Ru, Pt, Ru
O ₂ , SrRuO ₃ , La _1-x Sr _x CoO ₃ , SrMoO ₃ etc. in a single layer or 2
In some cases, a combination of two or more materials is used as a multilayer film. In this embodiment, IrO ₂ is used in a thickness of 0.1 μm.

The third layer is a high dielectric film such as Pb
ZrTiO ₃ , SrBi ₂ Ta ₂ O ₉ , Ba _x Sr _1-x TiO ₃ , Pb ₅ Ge ₃ O ₁₁ , Bi ₄ Ti
₃ O ₁₂ , (Pb _, La) TiO ₃ and the like. In this embodiment, SrBi ₂ T
a ₂ O ₉ is used, and the film thickness is 0.4 μm. For example, a material that is spin-coated by a sol-gel method is heat-treated at 450 ° C. to remove organic components, and is then formed by performing main firing at 800 ° C.

The fourth layer is made of amorphous Ge. For the film formation, a method that does not use a reducing atmosphere, such as a sputtering method or electron beam evaporation, is preferable in order to reduce the oxide ferroelectric and not deteriorate the characteristics. In this embodiment, the film is formed by electron beam evaporation and has a thickness of 0.4 μm.

A p ⁺ region is formed on the surface of the amorphous Ge portion. As the p-type impurities, there are B, Al, Ga, In, and the like. Of these, one kind or two or more kinds of impurities are introduced in combination. In this embodiment, B is used as an impurity.
Use As the p ⁺ region contact resistance with the metal such as Al alloy becomes lower, B concentration is set to 10 ¹⁹ / cm ³ or more at the surface of the p ⁺ regions.

FIG. 13 shows that amorphous Ge / ferroelectric film / Ir
FIG. 4 shows a cross-sectional view in which an SiO ₂ mask is formed on an O ₂ / W laminated film. The SiO ₂ film is a plasma CV using SiH ₄ / N ₂ O as a source gas.
D is deposited at a substrate temperature of 200 ° C. The film thickness of the SiO ₂ mask, the SiO ₂ mask is set so as to leave 100~200nm at the end patterning the gate. In this embodiment, the thickness of the SiO ₂ mask is
0.8 μm. An SiO ₂ mask is formed by a normal photolithography process and a dry etching process.

FIG. 14 is a cross-sectional view after the pattern of the SiO ₂ mask is transferred to the laminated film of amorphous Ge / ferroelectric film / IrO ₂ / W by dry etching. The dry etching is performed by introducing Cl ₂ / Ar gas and generating plasma by high frequency power of 13.56 MHz.

FIG. 15 shows that an n-type impurity is introduced by ion implantation into the source and drain electrode portions of the ferroelectric MOSFET. The channel portion of the ferroelectric MOSFET covered with a residual film (100 to 200 nm) at the time of gate processing of the SiO ₂ mask is covered with a resist formed by known photolithography, and used as a mask for ion implantation. In the ion implantation, impurities are introduced into the Ge region through the remaining film at the time of gate processing of the SiO ₂ mask. There are P, As, and Sb as n-type impurities, and one or more of these impurities are introduced in combination. In this embodiment, description is made using P as an impurity. The dose is set so that (n-type impurity concentration)> (p-type impurity concentration) is maintained on the surface of the Ge layer so that the source and drain electrode portions have low contact resistance with a metal such as an Al alloy. . After ion implantation, the resist is removed and N ₂
Heat treatment at 400 ° C for 5 hours in an atmosphere
Is crystallized into polycrystalline Ge, and at the same time, impurities are activated to form p ⁺ regions and n ⁺ regions of source and drain regions.

FIG. 16 is a cross-sectional view after the formation of the interlayer insulating film. As the interlayer insulating film, SiO ₂ is formed on the entire surface of the wafer by plasma CVD. In plasma CVD, deposition is performed at a substrate temperature of 200 ° C. using SiH ₄ / N ₂ O as a source gas. In this embodiment, the film thickness of SiO ₂ is 0.4 μm.

FIG. 17 is a sectional view after the formation of the contact hole. The formation of the contact hole is performed by processing the SiO ₂ by a normal photolithography process and dry etching. The contact hole of the source electrode is p ⁺
It is formed at a position that straddles the region and the n ⁺ region.

The process after processing the source and drain electrodes of the ferroelectric MOSFET is the same as that of a known LSI. That is, an interlayer insulating film is formed, a through hole is formed, wiring processing of an Al alloy or the like is performed, and finally, the wiring is covered with a protective film.

FIG. 18 is a sectional view of the device after the process is completed.

In the device structure of this embodiment, the source electrode can directly control the potential of the channel portion, so that writing / erasing can be performed efficiently.

Further, in this embodiment, the high-temperature process at 400 ° C. or higher is performed only when the ferroelectric film is formed, and after the ferroelectric film is formed, it can be manufactured by heat treatment at 400 ° C. or lower. By this low-temperature process, the heat history after the ferroelectric film formation can be reduced, so that the dielectric characteristics of the ferroelectric material are not easily deteriorated.

When Si is used for the semiconductor layer, an oxide film (SiO ₂ ) having a low dielectric constant is formed at the Si / ferroelectric interface by heat treatment required in the manufacturing process, and the Si / SiO ₂ / ferroelectric It becomes a structure. Since SiO ₂ is more stable than oxide ferroelectrics,
This is because Si reduces the ferroelectric material. In the present invention,
Since Ge is used for the semiconductor layer, an oxide film having a low dielectric constant cannot be formed at the Ge / ferroelectric interface, and an ideal Ge / ferroelectric structure can be obtained. This is because Ge does not reduce the ferroelectric material because the oxide of Ge is more unstable than the oxide ferroelectric.

In this embodiment, Ge is used for the semiconductor layer, but it is sufficient that an oxide film having a low dielectric constant is not formed at the semiconductor / ferroelectric interface. For example, Si _x Ge _1-x is used in the range of x <0.5. You may.

The device according to the present invention utilizes the spontaneous polarization of the ferroelectric in the gate portion to control the carrier concentration in the channel portion of the MOS structure to perform a memory operation. FIG. 6 shows the hysteresis characteristic of SrBi ₂ Ta ₂ O ₉ which is the ferroelectric of the present embodiment, to facilitate the description of the operation of the present invention. That is, coercive electric field = 40 kV / cm, remanent polarization = 12 μC / cm ² , and relative dielectric constant = 200. The film thickness of SrBi ₂ Ta ₂ O ₉ used in this example is 0.4 μm.

The write and erase operations will be described with reference to FIGS.

Writing is performed by applying 0 V to the source electrode and applying a writing voltage of -5 V to the gate electrode and releasing the drain electrode. Since the electric field intensity generated in SrBi ₂ Ta ₂ O ₉ below the source electrode at this time is −125 kV / cm, the spontaneous polarization of SrBi ₂ Ta ₂ O ₉ is sufficiently inverted to the saturation region as can be seen from FIG. be able to.

The erasing is performed by applying 0 V to the source electrode and 5 V to the gate electrode and releasing the drain electrode. As described in the write operation, the SrBi ₂ Ta ₂
Since the electric field intensity generated at O ₉ is 125 kV / cm, the spontaneous polarization of SrBi ₂ Ta ₂ O ₉ can be sufficiently inverted to the saturation region as can be seen from FIG. In a first embodiment, a polycrystalline
The channel portion of Ge is controlled by the non-vertical component of spontaneous polarization. However, in the structure of this embodiment, as can be seen from FIG. 21, since the potential of the channel portion can be directly controlled by the source electrode, the lower portion of the channel can be controlled. This can be done with the vertical component of spontaneous polarization.

Reading is performed by applying 0 V to the gate and source electrodes and 1 V to the drain electrode as shown in FIG. After writing is completed, the threshold of the ferroelectric MOSFET (Vt)
Becomes lower and becomes normally on as shown in FIG.
After erasing, Vt> 0 (V), so that the ferroelectric MOSFET does not turn on under the read condition. Binary data reading is performed using the change in the drain current.

[0053]

As described above, according to the first embodiment of the present invention, the following effects can be obtained.

1. Since the polycrystalline Ge / ferroelectric interface is stable against heat treatment in the manufacturing process, an ideal semiconductor / ferroelectric interface can be obtained, so that the voltage applied to the ferroelectric can be increased, and The voltage between the gate and the source at the time of erasing can be reduced.

2. Ge has higher electron mobility and hole mobility than Si, and can increase on current.

3. Since the ferroelectric capacitor portion and the MOSFET portion can be realized by one element, the structure is simplified and the device is easily miniaturized.

4. Since there is no high-temperature heat treatment after the ferroelectric film is formed, the polarization reversal characteristics of the ferroelectric material are not deteriorated by the stress due to the heat treatment or the outward diffusion of the constituent elements.

5. Since there is no heat treatment at a high temperature after the ferroelectric film is formed, the heat treatment does not diffuse impurities from the ferroelectric and its laminated structure, thereby deteriorating the characteristics of the MOSFET on the Si wafer.

According to the second embodiment, the following effects can be further obtained.

6. Since the potential of the channel portion can be directly controlled by the source electrode, the potential can be controlled by the vertical component of the spontaneous polarization of the ferroelectric under the channel.

[0061]

DESCRIPTION OF THE PREFERRED EMBODIMENTS As described above in detail with reference to the embodiments, according to the present invention, a nonvolatile memory element which can be written / erased at a low voltage can be realized. JP 2-64
The present invention can also be applied to a cell in which a normal MOSFET such as that shown in 993 is connected to both ends. In addition, the nonvolatile memory element according to the present invention can be formed on an insulating film such as a liquid crystal panel in addition to application to an LSI as long as the ferroelectric material can be formed by a low-temperature process.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a stacked film deposition of a ferroelectric MOS transistor.

FIG. 2 is a sectional view showing the formation of a gate of a ferroelectric MOS transistor.

FIG. 3 is a cross-sectional view showing formation of a source / drain of a ferroelectric MOS transistor.

FIG. 4 is a cross-sectional view showing the formation of a correlated insulating film of a ferroelectric MOS transistor.

FIG. 5 is a sectional structural view of a ferroelectric MOS transistor.

FIG. 6 is a diagram showing a hysteresis loop of SrBi ₂ Ta ₂ O ₉

FIG. 7 is a sectional view showing data writing to a ferroelectric substance.

FIG. 8 is a sectional view showing data erasure from a ferroelectric substance.

FIG. 9 is a diagram showing polarization induced in a ferroelectric by writing / erasing;

FIG. 10 is a sectional view showing connection of a ferroelectric MOSFET at the time of reading;

FIG. 11 is a diagram showing characteristics of a ferroelectric MOSFET.

FIG. 12 is a cross-sectional view showing a stacked film deposition of a ferroelectric MOS transistor.

FIG. 13 is a sectional view showing the formation of a mask of SiO ₂ .

FIG. 14 is a cross-sectional view showing the gate formation of a ferroelectric MOS transistor.

FIG. 15 is a sectional view showing formation of a source / drain of a ferroelectric MOS transistor.

FIG. 16 is a sectional view showing formation of an interlayer insulating film of a ferroelectric MOS transistor;

FIG. 17 is a sectional view showing formation of a contact hole.

FIG. 18 is a sectional structural view of a ferroelectric MOS transistor.

FIG. 19 is a sectional view showing data writing to a ferroelectric substance.

FIG. 20 is a sectional view showing data erasure from a ferroelectric substance.

FIG. 21 is a diagram showing polarization induced in a ferroelectric by writing / erasing;

FIG. 22 is a sectional view showing the connection of the ferroelectric MOSFET at the time of reading.

Claims (7)

[Claims] A lower metal gate formed on a semiconductor substrate; a ferroelectric film formed on the lower metal gate; and an amorphous semiconductor layer formed on the ferroelectric film. A channel portion formed in the semiconductor layer;
In a ferroelectric thin film transistor including a source / drain region formed at a distance from the channel portion and an extraction electrode from the source / drain, the amorphous semiconductor layer is made of Ge. Ferroelectric thin film transistor. 2. An impurity having a conductivity type opposite to that of a source / drain region is doped above the channel portion.
The ferroelectric thin film transistor according to claim 1, wherein the extraction electrode on the source side is in contact with the source region and over the channel portion. 3. The method according to claim 1, wherein the amorphous semiconductor layer is formed of SixGe.
3. The ferroelectric thin film transistor according to claim 1, comprising a 1-x (x <0.5) compound. 4. The ferroelectric film is made of PbZrTiO3, SrBi2Ta2.
O9, BaxSr1-xTiO3, Pb5Ge3O11, Bi4Ti3O12 (Pb, La) Ti
3. The ferroelectric thin film transistor according to claim 1, comprising one kind of material selected from O3. 5. The ferroelectric thin film transistor according to claim 1, wherein the metal gate is a laminated film of two or more layers made of different materials. 6. The method according to claim 6, wherein the lower layer of the laminated film is made of W, Ta, Mo, TiN,
1 selected from Nb, V, TaN, TaSiN, TiW, TiWN, TiAlN
The ferroelectric thin film transistor according to claim 5, wherein the ferroelectric thin film transistor is a single-layer film made of different kinds of materials or a multi-layered film formed by combining two or more kinds of materials. 7. An upper layer of the laminated film is made of IrO2, Ir, Ru, P
_{t, RuO 2, SrRuO 3,} La1-xSrxCoO 3, claim 5, wherein the SrMoO a multilayer film of a combination of single-layer film or two or more materials made of one material selected from ₃ Ferroelectric thin film transistor.