JP2000035756A - Encryption apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the execution of a cipher algorithm to execute the processing of a 4 byte base for a 32-bit microcomputer by executing the processing including the operation regulated by a function by using key data by forming the set of the data. SOLUTION: The data obtd. by subjecting π3 (A, B) to a first dyadic operation of A and the key data K2 with the data A of the n-bit length is subjected to first substitution processing. The resulted data is subjected to a second dyadic operation with the key data K3 and the resulted data is subjected to second substitution processing. The set of the data of the n-bit length subjected to the additive operation of the resulted data and B is determined as the function to be outputted and the data M2, M3 are held by a first holding means. The key data K2, K3 are held by a second holding means. The set (M1, M2) of the data held by the first holding means is subjected to processing including the operation regulated by the function π3 using the key data K2, K3 held by the second holding means, by which the set (M1, C2) of the data is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an encryption device.

[0002]

2. Description of the Related Art Conventional typical encryption algorithms include DES (Data Encryption Standard) and FEAL.
(Fast Encryption Standard) is known and DES
For example, (1) Koyama et al., "Modern Cryptography",
IEICE, pp. 41-49, September 1986, and regarding FEAL, (2) Shimizu et al., "High-speed Data Encryption Algorithm FEAL", IEICE Transactions D, Vol. J70-D. 7, pp. 1413 ~
1423, July 1987, respectively.

First, a non-linear calculation part in the DES process, that is, a process called an S box will be described (see (1) p. 45, FIGS. 3-2 and p 46, FIG.
3). The 32-bit R is first replaced by the extended transposition table shown in Table 1, and some bits are duplicated and expanded to 48 bits.

[0004] The 48-bit R obtained in this way forms the following eight sets of 6-bit blocks, each of which is obtained by adding the subsequent 2 bits for every 4 bits from the beginning.

[0005] r31 r1 r2 r3 r4 r5, r4 r5 r6 r7 r8 r9, r8 r9 r10 r11 r12 r13, r12 r13 ......, r28 r29, r28 r29 r30 r31 r32 r31 r32 r31 Similarly, an exclusive OR operation with the 48-bit key K is performed, and the result is divided into eight sets of 6 bits each and input to eight S boxes from S1 to S8.
S1 to S8 are called selection functions. These S boxes are
Input 6 bits and output 4 bits.

As an example, Table 2 shows a substitution table for one S box S1.

[0007] One S box has four types (line numbers 0, 1, 2,
3) is prepared, and the substitution table is selected by using the first and last bits of the input 6 bits to determine which of the four types of substitution table is used. Then, the central 4 bits of the 6 bits input according to the selected substitution table are substituted. As a specific example, the binary input pattern is 01 for S1.
If it is 1011, 01 represented by the first 0 and the last 1, that is, row 1 (binary 01 is decimal 1
) Is selected. Next, a column 1 represented by a central 4-bit pattern 1101 (decimal 13)
3 is output, and as a result, the value 5 specified in the row 1 and the column 13, that is, 0101 is output to form a 4-bit substitution pattern. In the DES, a single-stage process is configured using such a process f (R, K), and this is repeated 16 stages.

As can be seen from the above processing example, DES is based on 1-bit unit processing.

Next, a non-linear calculation part in the FEAL processing, that is, a part including the function S will be described (see p. 1416 of the above (2), FIGS. 4 and 5).
The non-linear part of FEAL is easier to describe mathematically than the non-linear part of DES. The 32-bit data α is divided into 8-bit data α0, α1, α2, and α3, respectively, and exclusive-ORed with the key data in 8-bit units. After that, processing by a predetermined function S is performed.

Function S: S (x1 + x2 + δ) = Rot2 (w) where w = (x1 + x2 + δ) mod 256 δ = 0 or 1 (constant) Using this process f (α, β), a one-stage process is configured. Repeated eight steps. As seen in the above process,
FEAL is based on 8-bit processing.

[0011]

With the spread and widespread use of computer networks due to advances in information processing and communication technology, data and computers on transmission lines are required to secure information security against unauthorized use or capture of data. It is considered that encrypting the data stored in the server is an effective countermeasure.

DES, established in 1982 by the United States Department of Commerce as a standard for encryption algorithms, is one means of encrypting data.

[0013] However, since DES performs a great deal of processing in bit units, it takes a long time to implement it with microcomputer software based on byte processing, and a practical speed cannot be obtained. .

In order to solve this problem, the FEAL is based on processing in units of 1 byte (8 bits). Therefore, when the FEAL is realized by an 8-bit microcomputer, it is possible to achieve speedup several times or more as compared with DES. did it. It is considered that FEAL has made it possible to obtain a practical speed to some extent using software of an 8-bit microcomputer.

However, with recent advances in microelectronics technology, 16-bit microcomputers have been replaced by 8-bit microcomputers,
32-bit microcomputers have been used rather than bit microcomputers. It is anticipated that the use of 32-bit microcomputers will increase significantly in the near future. In the era of 32-bit microcomputers, higher-speed encryption processing is expected to be required. However, since a 32-bit microcomputer performs processing based on 4-byte data, an F designed for an 8-bit microcomputer based on 1-byte data is used.
Attempting to implement the EAL with a 32-bit microcomputer was inefficient.

Therefore, there has been a demand for an encryption algorithm for a 32-bit microcomputer that performs a 4-byte key processing.

An object of the present invention is to provide an encryption device for executing an encryption algorithm for performing a process based on 4 bytes for a 32-bit microcomputer.

[0018]

To solve the above problems, the following means are used.

That is, π3 (A, B) is subjected to a first binary operation of n-bit data A, A and key data K2, and the data obtained from the first binary operation is calculated. A first substitution process is performed, a second binary operation with key data K3 is performed on data obtained from the first substitution process, and a second binary operation is performed on data obtained from the second binary operation. 2 is a function that outputs a set of data obtained from the second substitution processing and n-bit data obtained by performing an addition operation on B,
1 and M2, a second holding means for holding the key data K2 and K3, and a data set (M1, M2) held by the first holding means. , The key data K held by the second holding means
Means for generating a data set (M1, C2) by executing a process including an operation defined by a function π3 using K3.

Further, the first and second binomial operations are each an additive operation.

In addition, there is provided a computing unit capable of executing each of the first and second binary operations by one instruction, and capable of executing each of the first and second substitution processing by one instruction. The means for generating the data set (M1, C2) comprises:
And the second and second binomial operations and the first and second substitution processing are executed using the arithmetic unit.

Further, the data set (M1, C2)
Means for generating a function π3 with respect to the data set (M1, M2) held by the first holding means using the key data K2, K3 held by the second holding means.
After executing the operation defined by the equation (3), data obtained from the execution result of the operation defined by the function π3 and the key data K1
A data set (M1, C2) is generated by executing a process including an AND operation with the obtained data.

As a result, since the 32-bit data is replaced or transposed by one basic instruction using the 32-bit microcomputer, the cryptographic conversion can be performed at high speed.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (1) First Embodiment FIG. 1 shows an embodiment of the present invention.

In FIG. 1, a 64-bit plaintext 101 and a 64-bit × 4 = 256-bit key data 100 are 32 bits.
Input to the 32-bit microcomputer 102, and thereafter, are cryptographically converted by the 32-bit microcomputer 102 in the order of the instructions in the program 103.
The 4-bit ciphertext 104 is output.

FIG. 2 shows a flow of a cryptographic conversion process executed by the 32-bit microcomputer 102 and the program 103 of FIG.

201: The input data M is divided into upper 32 bits M1 and lower 32 bits M2.

202: An exclusive OR operation corresponding to the bits of M1 and M2 is performed.

WORK2 ← M1 (+) M2 Hereinafter, (+) indicates the same processing. In the figure, the exclusive OR is indicated by a symbol obtained by superimposing ○ and +.

203: Modulo addition of WORK2 and key data K1 is performed.

X ← WORK2 + K1 Here, x + K1 indicates a modulo addition modulo 232, that is, a remainder obtained by dividing the sum of x and K1 by 232.

Hereinafter, + indicates the same processing.

204: After x is cyclically shifted to the left by 2 bits, modulo addition of the data and x and 1 is performed.

X ← Rot2 (x) + x + 1 Hereinafter, Rot2 indicates the same processing.

105: After x is cyclically shifted to the left by 4 bits, the exclusive OR of the data and x is calculated.

X ← Rot4 (x) (+) x Hereinafter, Rot4 indicates the same processing.

206: WORK1 ← x (+) M1 207: x ← x + K2 208: x ← Rot2 (x) + x + 1 y ← x 209: x ← Rot3 (x) (+) x Here, Rot3 (x) is x Is cyclically shifted left by 8 bits.

210: x ← x + K3 211: x ← Rot2 (x) + x + 1 212: x ← Rot16 (x) + (x∧y) Here, Rot16 (x) cyclically shifts x to the left by 16 bits. Show. In addition, x∧y indicates that a logical AND of x and y corresponding to bits is taken.

213: WORK2 ← x (+) WORK2 214: x ← WORK2 + K4 215: x ← Rot2 (x) + x 216: WORK1 ← WORK1 (+) x 217: WORK2 ← WORK2 (+) WORK1 218: Output data of WORK1 Upper 32 bits of W
ORK2 is output as the lower 32 bits of the output data.

As described above, when the functions π1 to π4 are defined as shown in FIG. 2, this embodiment can be represented by a composite function as follows: C = π1, π4, π3, π2, π1 (M).

All functions πi · πi (i = 1 to 4) have the property of repeating the same function transformation twice and returning as πi · πi (x) = x.

Therefore, if M = π1, π2, π3, π4, π1 (C) is used as the decryption function, the ciphertext C can be returned to the original plaintext M.

(2) Modification Example 1 of Embodiment The process in which the process corresponding to the conversion functions π1 to π4 in the above embodiment is repeated twice may be used as the cryptographic conversion.・ Π3 ・ π2 ・ π1 ・ π4 ・ π3 ・ π2
・ It may be π1 (M).

At this time, the equation of the decoding conversion is M = π1, π2, π3, π4, π1, π2, π3, π4.
Π1 (C)

Similarly, in general, what is obtained by repeating this embodiment n times may be used as encryption conversion.

(3) Second Modified Example of Embodiment FIG. 4 shows another embodiment of the present invention.

401: Input data M is divided into upper 16 bits M1 and lower 16 bits M2.

402: The exclusive OR of the bits of M1 and M2 is calculated.

WORK2 ← M1 + M2 Hereinafter, + indicates the same processing.

403: Modulo subtraction of x and key data K1 is performed.

X ← x−K1 Here, x−K1 indicates a modulo subtraction modulo 216, that is, the remainder obtained by dividing the difference between x and K1 by 216.

Hereinafter, "-" indicates the same processing.

404: After x is cyclically shifted left by 2 bits, modulo subtraction of the data and 1 is performed.

X ← Rot (x) −x−1 Hereinafter, Rot2 indicates the same processing.

405: After x is cyclically shifted left by 4 bits, the exclusive OR of the data and x is calculated.

X ← Rot4 (x) (+) x Hereinafter, Rot4 indicates the same processing.

406: WORK1 ← x (+) M1 407: x ← x−K2 y ← x 408: x ← Rot2 (x) −x−1 409: Rot8 (x) − (x∧y) Here, Rot8 (X) indicates that x is cyclically shifted left by 8 bits. In addition, x∧y indicates that a logical AND of x and y corresponding to bits is taken.

410: WORK2 ← x (+) WORK2 411: x ← WORK2-K3 412: x ← Rot2 (x) −x−1 413: WORK1 ← WORK1 (+) x 414: WORK2 ← WORK2 (+) WORK1 415 : WORK1 as upper 16 bits of output data, W
ORK2 is output as the lower 16 bits of the output data.

(4) Third Modification of Embodiment FIG. 5 shows another embodiment of the present invention.

501: Input data M is divided into upper 8 bits M1 and lower 8 bits M2.

502: An exclusive OR operation corresponding to the bits of M1 and M2 is performed.

WORK2 ← M1 (+) M2 Hereinafter, + indicates the same processing.

503: Modulo addition of x and key data K1 is performed.

X ← WORK2 + K1 y ← x Here, x + K1 indicates a modulo addition modulo 28, that is, a remainder obtained by dividing a difference between x and K1 by 28.

Hereinafter, + indicates the same processing.

504: After x is cyclically shifted left by 2 bits, modulo addition of the data and x and 1 is performed.

X ← Rot2 (x) + x + 1 Hereinafter, Rot2 indicates the same processing.

505: x ← Rot4 (x) + (x∧y) Here, Rot4 (x) indicates that x is cyclically shifted to the left by 4 bits. In addition, x∧y indicates that a logical AND of x and y corresponding to bits is taken.

506: WORK1 ← WORK1 (+) x 507: x ← WORK1 + K2 508: x ← Rot4 (x) + x + 1 509: WORK2 ← WORK2 (+) x 510: WORK1 ← WORK1 (+) WORK2 511: Output WORK1 Upper 8 bits of WO
RK2 is output as the lower 8 bits of the output data.

(5) Fourth Modification of Embodiment FIG. 6 shows another embodiment of the present invention.

(1) Using a message 62 for performing authentication as key data, an arbitrary initial value 61 is encrypted using an algorithm 63 according to the present invention.

(2) The encryption result 64 is encrypted again with the subsequent data of the message used in (1), and this operation is repeated until the end of the message.

(3) The final encryption result is output as the message authentication code 65.

(6) Fifth Modification of Embodiment FIG. 7 shows another embodiment of the present invention. This IC card generates an authentication code of the message.

(1) An initial value 76 required for message authentication is transmitted to the microcomputer 72 in the IC card 71 through the I / O 74.

(2) A message 77 for performing authentication is sent to (1)
The microcomputer 72 generates the authentication code 78 using the encryption software 75 stored in the memory 73 in the same manner as described above.

[0077]

In the present embodiment, substitution and transposition as shown in FIG. 3 are repeated.

That is, in the embodiment shown in FIG.
04), (207, 208), (210, 211),
The processing of (214, 215) has the form of x ← x + Kix ← Rot2 (x) + (x) +1, which is obtained by dividing 32-bit data into blocks each having 4 bits. Substitution processing for each block is performed by the above two data conversions.
It can be seen that they are going all at once for the block.

Here, 4-bit block data A = (a1, a2, a3, a4), where ai = 1 or 0 (i = 1 to 4), B = (b1, b2, b3, b4) However, the fact that the conversion is made to bi = 1 or 0 (i = 1 to 4) means that the Boolean algebra operation f
1, f2, f3, and f4 exist; b1 = f1 (a1, a2, a3, a4) b2 = f2 (a1, a2, a3, a4) b3 = f3 (a1, a2, a3, a4) b4 = f4 (a1, a2, a3, a4).

Further, 205, 209, and 212 in FIG. 2 are (1) x ← Rot4 (x) (+) x (2) x ← Rot8 (x) (+) x (3) x ← Rot16 (x ) + (X∧y), which are (1) transposed to perform a 4-bit left circular shift and then further substituted, (2) 8-bit left circular The figure shows a process of performing a transposition after performing a transposition of performing a shift, and a process of performing (3) a 16-bit left circular shift.

As is apparent from FIG. 3, any bit change in the first 32 bits of data is the last 32 bits.
It can be seen that all bits of data are affected.

Thus, it is understood that the present embodiment has an effect of efficiently performing encryption conversion having a high degree of randomness.

[Brief description of the drawings]

FIG. 1 shows an embodiment of a cryptographic conversion device for implementing the present invention.

FIG. 2 is a flowchart showing details of encryption conversion in FIG. 1;

FIG. 3 is an explanatory diagram showing that the embodiment of the present invention efficiently repeats substitution conversion and transposition conversion.

FIG. 4 is a flowchart showing details of cryptographic conversion when a 16-bit microcomputer is used.

FIG. 5 is a flowchart showing details of encryption conversion when an 8-bit microcomputer is used.

FIG. 6 is a flowchart illustrating a method for generating a message authentication code using a cryptographic algorithm according to the present invention.

FIG. 7 is a configuration diagram of an IC card that generates a message authentication code using an encryption algorithm according to the present invention.

[Explanation of symbols]

100: key data, 101: plaintext, 102: 32-bit microcomputer, 103: program, 104:
Cryptogram.

Claims (4)

[Claims] An encryption apparatus for encrypting n-bit data M1 and M2 into n-bit data C2 using key data K2 and K3, wherein π3 (A, B) is converted to n-bit data. A first binary operation is performed on the long data A, A and the key data K2, a first substitution process is performed on data obtained from the first binary operation, and the first substitution process is performed. Performs a second binary operation on the key data K3 for the data obtained from
A function for performing a second substitution process on data obtained from the term operation, and further outputting a set of data obtained from the second substitution process and n-bit data obtained by performing an addition operation on B A first holding unit that holds the data M1 and M2; a second holding unit that holds the key data K2 and K3; and a data set (M1, M1) held by the first holding unit.
M2) is subjected to a process including an operation defined by a function π3 using the key data K2 and K3 held by the second holding means, thereby forming a data set (M1, C
Means for generating 2). 2. The encryption apparatus according to claim 1, wherein said first and second binary operations are each an addition operation. 3. An arithmetic unit capable of executing each of the first and second binomial operations with one instruction, and executing each of the first and second substitution processing with one instruction. The means for generating a data set (M1, C2) executes the first and second binomial operations and the first and second substitution processing using the arithmetic unit. Item 3. The encryption device according to Item 2. 4. The means for generating the data set (M1, C2) is provided by the second holding means for holding the data set (M1, M2) held by the first holding means. After performing the operation defined by the function π3 using the key data K2 and K3, the AND operation of the data obtained from the execution result of the operation specified by the function π3 and the data obtained from the key data K1 is performed. 4. The encryption device according to claim 3, wherein a data set (M1, C2) is generated by executing a process including the data set.