JP2000031493A - Thin-film transistor and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin-film transistor having a good drain current-gate voltage characteristic and a manufacturing method thereof. SOLUTION: A channel layer 14 formed on a base substrate 10, where the taper angle of the section of the end part is 10-45 deg., a gate electrode 18 which is formed on the base substrate 10 and channel layer 14 and intersects the channel layer 14, and source/drain regions 22 formed on the channel layer 14 at both sides of the gate electrode 18 are constituted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film transistor and a method for manufacturing the same, and more particularly, to a thin film transistor having good drain current-gate voltage characteristics and a method for manufacturing the same.

[0002]

2. Description of the Related Art Thin film transistors (TFT, Thin Film)
Transistor) is widely used as a switching element for pixels of an active matrix type liquid crystal display panel for reasons such as power saving, space saving, quick response speed, and beautiful display. A conventional thin film transistor will be described with reference to FIG. FIG. 7 is a sectional view showing a conventional thin film transistor. FIG. 7A is a cross-sectional view along the direction in which the channel layer of the conventional thin film transistor extends, and FIG. 7B is a cross-sectional view along the direction in which the gate electrode of the conventional thin film transistor extends.

[0003] As shown in FIG.
On silicon oxide film 112, a channel layer 114 is formed. A gate insulating film 116 is formed on the channel layer 114, and the gate electrode 1 is formed on the gate insulating film 116.
18 are formed. A low-concentration region 122a is formed in the channel layer 114 by self-alignment with the gate electrode 118.
2b are formed, and the low-concentration region 122a and the high-concentration region 122b form a source / drain region 122.

[0006] An interlayer insulating film 124 is formed on the entire surface. The contact hole 1 reaching the high concentration region 122b from the surface of the interlayer insulating film 124 is formed in the interlayer insulating film 124.
The source / drain electrode 128 is connected to the high-concentration region 122b via the contact hole 126.

[0005]

[SUMMARY OF THE INVENTION However, in the conventional thin film transistor as described above, good drain current I _D in the off region - the gate voltage V _G characteristics were not obtained. That is, as shown in FIG. 8, the drain current I _D of the off region is unstable, the drain current I _D has fallen to increase with gate voltage V _G is decreased.

It is an object of the present invention to provide a thin film transistor having good drain current-gate voltage characteristics and a method for manufacturing the same.

[0007]

The object of the present invention is to provide a channel layer formed on a base substrate and having a taper angle of 10 ° to 45 ° in cross section at an end portion, and a channel layer formed on the base substrate and the channel layer. The thin film transistor has a gate electrode crossing the channel layer and source / drain regions formed in the channel layer on both sides of the gate electrode. Accordingly, since the cross section of the end of the channel layer is formed in a tapered shape, the step coverage of the gate insulating film can be improved, and the channel layer is etched so as to suppress damage to the end. Therefore, it is possible to prevent a large amount of leak current from flowing in the region near the end of the channel layer. It is possible to suppress the leakage current occurs near the edge region of the channel layer, good drain current I _D - can be obtained gate voltage V _G characteristics.

The above object is also achieved by a semiconductor layer forming step of forming a semiconductor layer on a base substrate, and etching the semiconductor layer to form a channel layer comprising the semiconductor layer and having a tapered end section. And a gate electrode forming step of forming a gate electrode crossing the channel layer on the base substrate and the channel layer. Thus, since the cross section of the end of the channel layer is formed in a tapered shape, the step coverage of the gate insulating film can be improved, and the channel layer is etched so as to suppress damage to the end. Can be. Therefore, it is possible to prevent the leakage current will flow more near the edge region of the channel layer, good drain current I _D - can be prepared a thin film transistor having a gate voltage V _G characteristics.

In the above-described method of manufacturing a thin film transistor, it is preferable that in the etching step, the semiconductor layer is etched such that a taper angle of a cross section of an end of the channel layer is 10 ° to 45 °. In the above-described method for manufacturing a thin film transistor, it is preferable that in the etching step, the semiconductor layer is etched using a CF ₄ gas and an O ₂ gas, or a Cl ₂ gas and an O ₂ gas as an etching gas.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION The present inventors have proposed a thin film transistor.
Drain current I in the off region of the _D-Gate
Voltage V_GIn order to analyze the cause of the lack of characteristics,
Film transistor OBIC (Optical Beam Induced Curve)
rent spectroscopy) The current distribution was measured.

The OBIC current distribution is a current distribution obtained by irradiating a laser beam to a specimen to excite carriers flowing in the specimen, ie, electrons and holes, and detecting the excited carriers. is there. If a threshold value to be detected is set in advance, the distribution of a region where a current equal to or higher than the threshold value flows can be observed. Therefore, OB
From the IC current distribution, a region where a large amount of current flows in the test piece, that is, a region where a strong electric field is applied can be observed.

FIG. 9 shows a conventional thin film transistor OBI.
FIG. 4 is a conceptual diagram showing a C current distribution, in which a potential V _S of a source electrode 128 on the upper side of the drawing is set to 0 V, and a drain electrode
28 of the potential V _D and + 5V, in which the electric potential V _G of the gate electrode 118 showing the OBIC current distribution when a -5V. FIG. 9 shows an n-channel type thin film transistor as an example, in which a region where an OBIC current is observed, that is, a region where a current equal to or higher than a threshold value is flowing is blacked out.

As shown in FIG. 9, in the conventional thin film transistor, the OB
IC current was observed. That is, a large amount of leak current flows in the region near the end of the channel layer 114. As shown in FIG. 7B, the reason why a large amount of leakage current flows in the region near the end of the channel layer 114 is that the channel layer 1
Since the coverage of the gate insulating film 116 formed on the insulating layer 14 is not good, the channel layer 11 is formed by highly anisotropic etching used when forming the channel layer 114.
It is considered that the region near the end of No. 4 is damaged. In the region near the end of the damaged channel layer 114, a defect is generated, so that the donor is hardly activated.
Therefore, a stronger electric field is applied to the region near the end of the damaged channel layer 114 than to the non-damaged region.

The present invention has been made in view of the above study, and has been made to improve the step coverage of a gate insulating film, and to prevent damage to a region near the end of the channel layer when forming the channel layer. The main feature is to suppress the addition. A thin film transistor and a method of manufacturing the same according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a sectional view showing the thin film transistor according to the present embodiment. FIG. 1A is a sectional view taken along the direction in which the channel layer of the thin film transistor extends.
(B) is a cross-sectional view along the direction in which the gate electrode of the thin film transistor extends. FIG. 2 is a conceptual diagram showing the OBIC current distribution of the thin film transistor according to the present embodiment. FIG.
, The drain current I _D of the thin film transistor according to the present embodiment - is a graph showing the gate voltage V _G characteristics. 4 to 6 are process sectional views illustrating the method for manufacturing the thin film transistor according to the present embodiment.

(Thin Film Transistor) As shown in FIG.
On the glass substrate 10, a silicon oxide film 12 having a thickness of 200 nm is formed.
A channel layer 14 made of a polycrystalline silicon film having a thickness of 50 nm and having a tapered end section is formed. On the channel layer 14, a gate insulating film 16 made of a silicon oxide film having a thickness of 120 nm is formed.

The thin film transistor according to the present embodiment is characterized mainly in that the cross section of the end of the channel layer 14 is formed in a tapered shape, and the cross section of the end of the channel layer 14 is formed in a tapered shape. Because it is formed,
As shown in (b), the gate insulating film 16 is formed with good step coverage. The taper angle of the cross section at the end of the channel layer 14 is set to, for example, 10 so that the step coverage of the gate insulating film 16 can be improved.
° to 45 °, and more preferably 15 °
° to 30 °.

Since the gate insulating film 16 is formed with good step coverage, it is possible to suppress the flow of a large amount of leak current in the region near the end of the channel layer 14, thereby improving the drain current I. _D - gate voltage V _G characteristics can be obtained. Gate insulating film 1
A gate electrode 18 is formed on 6, and an anodic oxide film 20 is formed on the surface of the gate electrode 18.

The channel layer 14 is self-aligned with the low concentration region 22a on the gate electrode 18 on which the anodic oxide film 20 is formed.
Are formed, and a high-concentration region 22b is formed in the gate insulating film 16 by self-alignment, and the low-concentration region 22a and the high-concentration region 22b constitute a source / drain region 22. Further, an interlayer insulating film 24 is formed on the entire surface. In the interlayer insulating film 24, a contact hole 26 reaching the high-concentration region 22b from the surface of the interlayer insulating film 24 is formed, and a source / drain electrode 28 is connected to the high-concentration region 26b via the contact hole 26.

(Electrical Characteristics) The electrical characteristics of the above-described thin film transistor will be described with reference to FIGS. FIG. 2 shows the OB of the thin film transistor according to the present embodiment.
It is a conceptual diagram which shows IC current distribution. 3, the drain current I _D of the thin film transistor according to the present embodiment - is a graph showing the gate voltage V _G characteristics.

The OB of the thin film transistor according to the present embodiment
When the IC current distribution was measured, a measurement result as shown in FIG. 2 was obtained. FIG. 2 shows that the potential V _S of the source electrode 28 on the upper side of the drawing is 0 V, and the potential V _D of the drain electrode 28 on the lower side of the drawing is +.
And 5V, in which the electric potential V _G of the gate electrode 18 showed OBIC current distribution when a -5V. FIG.
This is a channel type thin film transistor as an example, and the region where the OBIC current is observed, that is, the region where a current equal to or higher than the threshold value is flowing is indicated by black.

As shown in FIG. 2, no OBIC current was observed in the thin film transistor according to the present embodiment.
In a conventional thin film transistor, an OBI as shown in FIG.
C current distribution was observed, and the leakage current was
However, in the thin film transistor according to the present embodiment, a leak current higher than a preset threshold did not flow, and no OBIC current was observed. That is, in the thin film transistor of the present embodiment,
The flow of a large amount of leak current in the region near the end of the channel layer 14 is suppressed.

The thin film transistor according to the present embodiment as described above
Drain current I_D-Gate voltage V_GMeasured properties
However, as shown in FIG._D-Gate power
Pressure V _GCharacteristics were obtained. That is, the thin film transistor according to the present embodiment
In the transistor, as shown in FIG._GBut
The drain current I_DCan increase
And the drain current I_DIs stable to almost a constant value.
In a conventional thin film transistor, as shown in FIG.
Voltage V_GThe drain current I_DIncreases
However, in the thin film transistor according to the present embodiment,
Gate voltage V_GThe drain current I_DIncreases
Absent. The drain voltage of the thin film transistor according to the present embodiment is
Style I_DIs stable near the end of the channel layer 14.
Suppresses the flow of a large amount of leak current in the region
It is thought to be done.

As described above, according to the present embodiment, since the cross section of the end portion of the channel layer is formed in a tapered shape, the step coverage of the gate insulating film can be improved, whereby the channel layer can be improved. Can be prevented from flowing in the vicinity of the end portion. It is possible to suppress the leakage current occurs near the edge region of the channel layer, according to this embodiment, good drain current I _D - can be obtained gate voltage V _G characteristics.

(The Method for Fabricating the Thin Film Transistor) Next, the method for fabricating the thin film transistor according to the present embodiment will be explained with reference to FIGS. 4 to 6, the left side is a cross-sectional view along the direction in which the channel layer of the thin film transistor extends, and the right side is a cross-sectional view along the direction in which the gate electrode of the thin film transistor extends.

First, a plasma CV is placed on a glass substrate 10.
A 200-nm-thick silicon oxide film 12 is formed by a D (Plasma enhanced Chemical Vapor Deposition) method. Next, a channel layer 14 of a 50 nm-thick polycrystalline silicon film is formed on the silicon oxide film 12 by a plasma CVD method.
(See (a)).

Next, a photoresist mask 30 for patterning the channel layer 14 is formed by photolithography (see FIG. 4B). Next, the channel layer 14 is etched by dry etching using the photoresist mask 30 as a mask (FIG. 4C).
reference). At this time, etching is performed under the condition of low anisotropy. By performing etching under conditions of low anisotropy,
The channel layer 14 is etched while also etching the photoresist mask 30 and the silicon oxide film 12, so that the cross section of the end of the channel layer 14 is formed into a rather gentle taper.

As an etching gas, CF_FourGas and O_Two
Gas can be used. Etching conditions, for example
If CF_FourGas flow rate 50 sccm, O_TwoGas flow
33 sccm, the pressure in the etching chamber was 4 Pa,
The power may be 1 kW. O _TwoIncrease the gas flow rate.
The photoresist mask 30 is easily etched.
So, O_TwoChannel by adjusting gas flow
The taper angle of the cross section at the end of the layer 14 can be appropriately set.
Wear.

The etching gas is CF ₄ gas and O ₂
The gas is not limited to the gas, and for example, a Cl ₂ gas or the like may be used instead of the CF ₄ gas. When Cl ₂ gas and O ₂ gas are used as the etching gas, for example, the flow rate of Cl ₂ gas may be 180 sccm, and the flow rate of O ₂ gas may be 20 sccm. In addition, the etching conditions for etching the channel layer 14 are not limited to the above, and the cross section of the end of the channel layer 14 can be tapered, and damage to a region near the end of the channel layer 14 can be made. If the pressure in the etching chamber can be set appropriately, for example,
-13 Pa and the power may be set in the range of 800 W-1 kW.

The taper angle of the cross section at the end of the channel layer 14 may be appropriately set so as to improve the step coverage of the gate insulating film 16 formed on the channel layer 14 in a later step. , For example, 10 ° to 45 °
Can be set to However, it is difficult in device design to set the taper angle of the cross section at the end of the channel layer 14 to be extremely small, and the step coverage of the gate insulating film 16 becomes worse as the taper angle increases.
It is desirable to set the angle to about 15 ° to 30 °.

Since the channel layer 14 is etched under the above-mentioned condition, that is, under the condition of low anisotropy, damage to the region near the end of the channel layer 14 can be suppressed. Next, on the entire surface by the plasma CVD method,
A gate insulating film 16 made of a silicon oxide film having a thickness of 120 nm is formed. Since the cross section at the end of the channel layer 14 is formed in a tapered shape, the step coverage of the gate insulating film 16 can be improved (see FIG. 4D).

Next, a film thickness of 30 is formed on the entire surface by sputtering.
An aluminum film of 0 nm is formed. Next, the gate electrode 18 is formed by patterning the aluminum film by photolithography. Gate electrode 1
The width of 8 can be, for example, 4 μm.

Next, the gate electrode 18 is formed by anodic oxidation.
An anodic oxide film 20 having a thickness of 120 nm is formed on the surface of the substrate.
The anodic oxide film 20 is for preventing hillocks or the like from being generated on the surface of the gate electrode 18 due to heat treatment or the like in a later step (see FIG. 5A). Next, the gate insulating film 16 is patterned by photolithography. Dry etching can be used for patterning. The width of the gate insulating film 16 is, for example, 6 μm,
That is, in the drawing on the left side of the drawing of FIG. For example, CHF ₃ can be used as an etching gas. The etching conditions include, for example, a gas flow rate of 200 sccm and a pressure in the etching chamber of 3 sccm.
Pa and power may be set to 1.4 kW (see FIG. 5B).

Next, the anodic oxide film 2 is formed by ion implantation.
0 is formed in a self-aligned manner on the gate electrode 18 on which the impurity ions are formed.
And then heat-treated to reduce the low concentration area.
An area 22a is formed. The acceleration voltage is, for example, 70 keV,
Dose amount is, for example, 1.0 × 10 ¹⁴ion / cm^Twogiven that
Good. As the impurity, for example, P can be used.
You.

Next, high-concentration impurity ions are introduced into the gate insulating film 16 in a self-aligned manner by an ion implantation method, and thereafter heat treatment is performed to form a high-concentration region 22b. The acceleration voltage may be, for example, 10 keV, and the dose may be, for example, 1.5 × 10 ¹⁵ ions / cm ² . As the impurity, for example, P can be used. Thus, the source / drain region 22 is constituted by the low-concentration region 22a and the high-concentration region 22b (see FIG. 5C).

Next, the entire surface is formed by a plasma CVD method.
A silicon oxide film having a thickness of 40 nm and a silicon nitride film having a thickness of 370 nm are sequentially formed, and an interlayer insulating film 24 composed of a silicon oxide film and a silicon nitride film is formed (see FIG. 5D). Next, the interlayer insulating film 24 is etched by a photolithography technique, whereby the contact holes 26 reaching the high concentration regions 22b of the source / drain regions 22 are formed.
And an opening (not shown) reaching the anodic oxide film 20 on the surface of the gate electrode 18. When etching the silicon nitride film of the interlayer insulating film 24, dry etching using CF ₄ gas and O ₂ gas as an etching gas is performed.
F ₄ gas flow rate is 50 sccm, O ₂ gas flow rate is 33 s
ccm, the pressure in the etching chamber is 4 Pa, and the power is 1 kW. Further, when etching the silicon oxide film of the interlayer insulating film 24, wet etching can be used. As an etching solution, a buffered hydrofluoric acid solution containing acetic acid or a buffered hydrofluoric acid solution is used. Seconds may be used.

Next, the anodic oxide film 20 on the surface of the gate electrode 18 exposed in the opening (not shown) is etched by wet etching. As the etching solution, for example, a phosphoric acid solution containing chromium can be used, and the temperature of the etching solution may be, for example, 65 ° C., and the etching time may be, for example, 4 minutes. Thus, a contact hole (not shown) reaching the gate electrode 18 is formed in the interlayer insulating film 24.

Next, a film thickness of 1 was formed on the entire surface by sputtering.
By sequentially forming a 00-nm-thick titanium film, a 200-nm-thick aluminum film, and a 100-nm-thick titanium film, a stacked film composed of these films is formed. next,
The stacked film is patterned by the photolithography technique, and the source / drain wiring 28 connected to the source / drain region 22b through the contact hole 26 and the gate electrode 18 through the contact hole (not shown).
To form a gate wiring (not shown) to be connected to. BCl ₃ gas and Cl ₂ gas can be used as an etching gas. The etching conditions include, for example, BC
The flow rate of l ₃ gas is 90 sccm and the flow rate of Cl ₂ gas is 60 sccm.
sccm, the pressure in the etching chamber can be 10 Pa, and the power can be 1 kW (see FIG. 6).

As described above, the thin film transistor according to the present embodiment can be manufactured. As described above, according to the present embodiment, since the channel layer is etched under the condition of low anisotropy, the cross section of the end portion of the channel layer can be formed in a tapered shape, whereby the step coverage of the gate insulating film can be improved. Can be improved. In addition, since the channel layer is etched under the condition of low anisotropy, damage to the region near the end of the channel layer due to the etching can be reduced. Since step coverage of the gate insulating film can be improved and damage to the region near the end of the channel layer can be reduced, a large amount of leak current flows in the region near the end of the channel layer. it can be prevented, thereby better drain current I _D - can be prepared a thin film transistor having a gate voltage V _G characteristics.

[Modified Embodiment] The present invention is not limited to the above-described embodiment, and various modifications are possible. For example, in the above embodiment, a thin film transistor having an LDD structure has been described as an example. However, the present invention is not limited to a thin film transistor having an LDD structure, and can be applied to a thin film transistor having no LDD structure.

In the above embodiment, a thin film transistor has been described as an example. However, the present invention can be applied not only to a thin film transistor but also to any semiconductor device.

[0041]

As described above, according to the present invention, since the cross section of the end portion of the channel layer is formed in a tapered shape, the step coverage of the gate insulating film can be improved. Further, since the channel layer is formed by etching the semiconductor layer under the condition of low anisotropy, damage to the region near the end of the channel layer due to the etching can be reduced. Since step coverage of the gate insulating film can be improved and damage to the region near the end of the channel layer can be reduced, a large amount of leak current flows in the region near the end of the channel layer. Can be prevented, which results in a good drain current I _D
- it is possible to provide a thin film transistor having a gate voltage V _G characteristics.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a thin film transistor according to an embodiment of the present invention.

FIG. 2 is a conceptual diagram illustrating an OBIC current distribution of a thin film transistor according to an embodiment of the present invention.

Is a graph showing the gate voltage V _G characteristics - [3] the drain current I _D of the thin film transistor according to an exemplary embodiment of the present invention.

FIG. 4 is a process sectional view (part 1) illustrating the method for manufacturing the thin film transistor according to the embodiment of the present invention.

FIG. 5 is a process sectional view (part 2) illustrating the method for manufacturing the thin film transistor according to the embodiment of the present invention.

FIG. 6 is a process sectional view (part 3) illustrating the method for manufacturing the thin film transistor according to one embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a conventional thin film transistor.

FIG. 8 shows a drain current _ID- of a conventional thin film transistor.
It is a graph showing the gate voltage V _G characteristics.

FIG. 9 is a conceptual diagram showing an OBIC current distribution of a conventional thin film transistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Glass substrate 12 ... Silicon oxide film 14 ... Channel layer 16 ... Gate insulating film 18 ... Gate electrode 20 ... Anodic oxide film 22 ... Source / drain region 22a ... Low concentration region 22b ... High concentration region 24 ... Interlayer insulation film 26 ... Contact hole 28 source / drain electrode 30 photoresist mask 110 glass substrate 112 silicon oxide film 114 channel layer 116 gate insulating film 118 gate electrode 122 source / drain region 122a low concentration region 122b high concentration Region 124 ... Interlayer insulating film 126 ... Contact hole 128 ... Source / drain electrode

Claims (4)

[Claims] 1. A channel layer formed on a base substrate and having a taper angle of 10 ° to 45 ° in a cross section of an end portion, formed on the base substrate and the channel layer, intersecting the channel layer. A thin film transistor comprising: a gate electrode; and source / drain regions formed in the channel layer on both sides of the gate electrode. 2. A semiconductor layer forming step of forming a semiconductor layer on a base substrate; and etching the semiconductor layer, comprising the semiconductor layer;
An etching step of forming a channel layer having a tapered end section; and a gate electrode forming step of forming a gate electrode crossing the channel layer on the base substrate and the channel layer. Manufacturing method of a thin film transistor. 3. The method for manufacturing a thin film transistor according to claim 2, wherein in the etching step, the semiconductor layer is etched such that a taper angle of a cross section of an end of the channel layer is 10 ° to 45 °. A method for manufacturing a thin film transistor. 4. The method for manufacturing a thin film transistor according to claim 2, wherein in the etching step, the semiconductor layer is etched using CF ₄ gas and O ₂ gas or Cl ₂ gas and O ₂ gas as an etching gas. A method for manufacturing a thin film transistor, comprising: