JP2000031438A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate erroneous writing or reading in or from a non-selected memory cell transistor by applying specified bias to the source and the drain of the non-selected memory cell transistor connected before and after a selected memory cell transistor. SOLUTION: If a gate electrode 122 is applied with high voltage, hot electrons are generated from the tip of a channel 126 formed on the surface of a substrate 111 below a side wall 115 and part of them are trapped inside a nitride film 120. In a memory cell transistor M2 adjacent on the drain electrode 117 side to a selected memory cell transistor M3, a source region 112-4 and a drain region 113-4 are biased at the same writing potential as that at the drain electrode 117 of the selected memory cell transistor M3. Therefore, current caused to flow from the selected memory cell transistor M3 toward the non-selected memory cell transistors M2... is suppressed to the minimum and thereby erroneous wiring is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device using a nonvolatile memory cell of a type known as a MONOS element for storing storage charges in a nitride film.

[0002]

2. Description of the Related Art A MONOS element has a nitride film sandwiched between an insulating film such as a nitrogen oxide film between a channel portion and a gate of a cell transistor, and can store electrons as storage charges in the nitride film. Having a structure.

When electrons are stored in this nitride film,
The electric field applied from the gate when a voltage is applied to the gate is offset according to the amount of electrons stored in the nitride film,
The threshold voltage of the cell transistor can be made different between a cell with electrons and a cell without electrons. Data is recorded by utilizing the characteristics of the cell transistor that can vary the threshold voltage.

[0004]

However, the conventional M
In a semiconductor memory device using ONOS element cells, for example, at the time of writing, the drain side of the selected memory cell transistor is biased to the writing potential and the source side is biased to the Vss potential. The sources and drains of the memory cell transistors other than the selected memory cell transistor all have a floating potential. Therefore, when the source potential of the unselected memory cell transistor adjacent to the selected memory cell transistor is lower than the drain potential of the memory cell transistor, a current flows from this drain to the source of the unselected memory cell transistor,
As a result, erroneous writing is performed on this unselected memory cell transistor.

[0005] Such a phenomenon similarly occurs when data is read.

Accordingly, the present invention provides a method for writing data,
It is an object of the present invention to provide a semiconductor memory device configured so that writing or reading is not performed erroneously on a non-selected memory cell transistor adjacent to a memory cell transistor selected at the time of reading.

[0007]

A semiconductor memory device according to the present invention comprises a memory cell array comprising a plurality of memory cell transistors arranged in a matrix in a row direction and a column direction, and a plurality of memory cell transistors arranged in a row direction. A plurality of word lines to which the gates of the memory cell transistors are connected in common, a plurality of bit lines to which the sources and drains of the plurality of memory cell transistors arranged in the column direction are connected in common, First and second switching elements connected in parallel, a first voltage source connected to the first switching element, a second voltage source connected to the second switching element, and the memory cell When writing or reading data to or from a transistor, all non-selected cells arranged on the drain side of the memory cell transistor connected to the selected bit line The first switching element connected to the bit line is made conductive, and the second switching element connected to all the non-selected bit lines arranged on the source side of the memory cell transistor connected to the selected bit line. And control means for conducting the switching element.

According to the above configuration, a predetermined bias potential is applied to the source and the drain of all the non-selected memory cell transistors other than the memory cell transistor selected at the time of writing and reading, that is, the source and the drain of the non-selected memory cell transistor are set to the predetermined bias potential. It is possible to provide a semiconductor memory device which can apply a potential which can prevent erroneous writing and erroneous reading.

[0009]

An embodiment of the present invention will be described below with reference to the drawings.

First, a configuration of a bias circuit connected to a bit line of a cell array configured using the MONOS element cells according to the present embodiment will be described with reference to FIG.
In the figure, bias control circuits A1, A2, A3, and A4 are connected to bit lines BL1, BL2, BL3, and BL4 of all of the cell arrays Ce (only four are shown here).

A first switch transistor 1 having one end connected to the bit line BL1 and the other end connected to the low voltage source Vss is connected to the bit line BL1 of the bias control circuit A1.
a and a second switch transistor 1b having one end connected to the bit line BL1 and the other end connected to the high voltage source Vpp.
And a bit line selection circuit consisting of a parallel circuit consisting of

Further, the bit line BL1 and the sense circuit terminal S
The third switch transistor Tr is connected to the AIN.

The gates of the transistors 1a, 1b and Tr are supplied with output signals of a decoding circuit De and an address addition / subtraction circuit AS, respectively.

All remaining bias control circuits A2, A
3 and A4 are similarly configured.

FIG. 2 is a sectional view showing the structure of a plurality of memory cell transistor arrays in a row direction connected to a word line WL among a plurality of word lines intersecting bit lines B1 to B4 in the cell array Ce of FIG. is there.

In FIG. 2, a plurality of n + -type first buried regions 1 are formed in a cell formation region of a p-type semiconductor substrate 111.
12-3, 112-4, and 112-5, and a plurality of n + -type second embedded regions 113-2, 113-3, and 113-
4 are alternately formed. First embedded region 112-3
Are used as source regions in the respective memory cell transistors, and the first buried regions 112-3.
Formed at a predetermined distance from each other are used as drain regions of the same memory cell transistor.

For example, an insulating film 114 is formed on the source region 112-3. The insulating film 114 is formed at least on the source region 1 on the side facing the drain region 113-3.
It is formed to have an edge corresponding to the edge of 12-3. In this embodiment, the source region 112-3 is formed on the source region 112-3 with the same dimensions so that the front and rear edges coincide with each other.

The drain region 11 of the insulating film 114
A first sidewall 115 made of an insulator is provided on the side surface facing 3-3 so that the bottom surface covers the surface of the semiconductor substrate 111.

The drain region 113-3 has an edge corresponding to the edge of the drain region 113-3 on the side facing the source region 112-3, and the bottom surface of the drain region 113-3 is formed on the semiconductor substrate 111. The second formed to cover the surface
Are provided. The second side wall 116 is also formed of an insulating material.
An insulating film 117 is formed on the source region 113-3 behind it.
Is formed. In this embodiment, the side wall 118 is also formed on the side surface behind the insulating film 117.

Further, the first and second sidewalls 1
A first silicon oxide film 119, which is an insulating film, is formed on the surface of the semiconductor substrate 111 sandwiched between 15 and 116, and a nitride film 120 is formed on the first silicon oxide film 119. . A second silicon oxide film 121 is further formed on the nitride film 120, and finally the sidewalls 115 and 116, insulating films 114 and 117,
A gate electrode 122 made of polysilicon is formed in common on second oxide film 121. This gate electrode 1
Reference numeral 22 is used as a word line WL. Thus, a memory cell having the MONOS structure is formed.

The memory cell transistor M formed between the source region 112-3 and the drain region 113-3
3, the memory cell transistor M is also provided between the source region 112 and the drain region 113 formed before and after that.
1, M2 and M4 are formed.

Now, it is assumed that, for example, the memory cell transistor M3 is selected when writing or reading data. For example, in the case of writing, FIG. 1 connected to the bit line BL1 of the selected memory cell transistor M3.
Of the first switch transistor 1b is a decode circuit De.
And the potential Vpp is supplied to the bit line BL1.

On the other hand, unselected bit lines BL2, BL3,
The selected memory cell transistor M3 of BL4
In the bias circuits A2 and A3 connected to the bit lines BL2 and BL3 arranged adjacent to the source region 112-3, the first switch transistors 1a respectively receive signals from the decode circuit De or the addition / subtraction circuit AS. Are conducted, and the low voltage source Vs is applied to the bit lines BL2 and BL3, respectively.
A low potential Vss is supplied from s.

In the bias circuit A0 connected to the bit line BL0 of the memory cell transistor M2 arranged adjacent to the drain region 113-3 of the selected memory cell transistor M3, the decoding circuit De or the addition / subtraction circuit The second switch transistor 1b is turned on by the signal from the AS, and the high potential Vpp is supplied to the bit line BL0 from the high voltage source Vpp.

Further, referring to FIGS. 2 and 3, for example, semiconductor substrate 11 in a memory cell transistor selected at the time of writing and an unselected adjacent memory cell transistor.
An operation state including a state of a depletion layer inside 1 will be described.

For example, an operation state when the memory cell transistor M3 is selected in FIG. 2 will be described with reference to FIG. In the cell M3 having the MONOS structure, the state where electrons (hot electrons) are injected into the nitride film 120 is referred to as a write state.
A state where electrons are stored in 0 is defined as “0”, and a state where electrons are not injected is defined as “1”.

At the time of writing, the potential of the substrate 111 and the potential of the source electrode 114 are fixed to “0” volts, respectively, and a voltage for writing “0”, for example, 5 volts, is applied to the drain electrode 117. In this state, the gate electrode (word line WL) 1
22 is applied with a predetermined high voltage for writing, for example, 7 volts.

Then, since the positive voltage is higher below the drain region 113-3 than the source region 112-3, the depletion layer 125 in the substrate 111 extends deeper, as shown in FIG.

In this state, if the voltage applied to the gate electrode 122 is high, the substrate 11 below the sidewall 115
A wedge-shaped channel 126 is formed in one surface region.
The tip of the channel 126 further extends from below the sidewall 115 to reach the lower portion of the insulating film 119.

In this state, hot electrons are generated from the tip of the channel 126. Most of the generated hot electrons e1 are in the drain region 113-3.
Is moved along the surface region of the substrate 111 in the direction of, but a portion e2 passes through the insulating film 119 due to the electric field effect of the gate electrode 122 and is trapped and stored in the nitride film 120.

At this time, in the memory cell transistor M2 adjacent to the drain electrode 117 of the selected memory cell transistor M3, the source region 112-4 and the drain region 113-4 of the selected memory cell transistor M3 are connected to the selected drain electrode 117.
As shown in FIG. 2, the depletion layer 125 is biased to Vpp which is the same write potential as
Only slightly extends along 113-4, the current flowing from the selected memory cell transistor M3 to the adjacent unselected memory cell transistor M2 is minimized, and erroneous writing is prevented.

On the other hand, in the circuit of FIG. 1, when an address of a write cell is input, the input address is subtracted by -1 or +1 by an addition / subtraction circuit AS.
The bit line of the added or subtracted address and the bit line of the lower address are biased to a lower potential Vss by the decoding circuit De.

Hereinafter, an example of the configuration of a circuit for applying a predetermined bias to the source and drain of the memory cell transistor before and after the selected memory cell transistor and the operation thereof will be described in more detail with reference to FIGS. I do.

In FIG. 4, the memory cell arrays Ce are arranged in an 8 × 8 matrix for convenience of explanation. The memory cells in the same row correspond to the corresponding word lines WLI to WLI.
The drains of the memory cells connected to L8 in the same column are connected to the same bit line, and the sources are connected to the same bit line. For example, the memory cell 1 in the rightmost column
The drains of the memory cells 11 to 18 are connected to the bit line BL1, and the sources of the memory cells 11 to 18 are connected to the bit line BL2. The bit line BL2 is also connected to the drains of the memory cells 21 to 28 in the adjacent column.
Word lines WLI to WL8 are connected to row decog 101. The bit lines BL1 to BL9 are connected to the column decoder 102.
Bit line selection circuit 103 controlled by the output signal of
Is connected to the program circuit 104 via the.

The bit line selection circuit 103 is composed of a plurality of N-channel transistors. As described with reference to FIG. 1, the drains of the transistors 1a and 1b are connected to the bit line BL1, and the transistors 2a and 2b are connected to the bit line BL2.
The drains of 2b and 1c are connected. Similarly, transistors 3a-8 are connected to bit lines BL3-BL8, respectively.
a, 3b to 8b, and the drains of 2c to 7c are connected, and the bit line BL9 is connected to the drains of the transistors 9b and 8c.

Control signals CUI-C output from column decoder 102 are connected to the gates of transistors 1a-8a.
U8 is supplied, control signals CB1 to CB9 output from the column decoder 102 are input to the transistors 1b to 9b, and control signals CLI to CL8 output from the column decoder 102 are input to the transistors 1c to 9c. The program circuit 104 includes a data write circuit 105, a sense up circuit 106, a bias circuit 107, and a ground circuit 108.
It is composed of The data write circuit 105 is connected via an N-channel transistor T2 whose ON / OFF is controlled by an external signal W, and the sense amplifier 106 is connected via an N-channel transistor Tl which is turned on / off by an external signal R to select a bit line. Commonly connected to transistors 1 a to 8 a of circuit 103.

The bias circuit 107 is a bit line selection circuit 1
03 are commonly connected to the transistors 1b to 9b. The ground potential 108 is commonly connected to the transistors 1c to 8c of the bit line selection circuit 103.

At the time of writing data to a memory cell,
A high voltage is supplied to the bit line to which the drain of the selected memory cell is connected, and a reference potential (for example, ground potential) is supplied to the source. Then, when charges are injected into the nitride film of the memory cell, a high voltage is supplied to the gate of the selected memory cell, that is, to the word line to which the selected memory cell is connected. As a result, current flows through the channel of the memory cell, and charges in the channel region are injected into the nitride film. When no charge is injected into the nitride film of the selected memory cell, that is, when the erased state is maintained, a reference potential (for example, ground potential) is supplied to the selected word line.

Before data programming (data writing) to the memory cells, the data in the memory cells is erased. That is, the memory cell initializes the data before programming the data, sets all of the data to a state of storing one of the binary data, and then selectively writes the other data of the binary data. I do.
Before erasing data, charges are injected into the nitride films of all memory cells from which data is to be erased. That is,
By keeping the initial state of the memory cell to be erased and then erasing, the distribution of the threshold voltage of the memory cell after erasure is made nearly uniform. The charge is injected into the memory cell before erasing by, for example, supplying a high voltage to the bit line BL1, setting the bit line BL2 to the reference potential, and sequentially setting the word lines WLI to WL8 to a high voltage.
Charges are sequentially injected into 1 to 18. After that, the bit line BL
2, a high voltage is supplied, the bit line BL3 is set to a reference potential, and the word lines WLI to WL8 are sequentially set to a high voltage to sequentially inject charges into the memory cells 21 to 28. This is repeated from the bit lines BL3 to BL9, and charges are injected into the nitride films of all the memory cells. Alternatively, if all the bit lines are set to the reference potential and all the word lines are set to the high potential, charges are injected into the nitride film from the channel region by the hot electron effect. When the charge injection is completed as described above, all the word lines are set to the reference potential, and a high voltage is supplied to the bit lines. For this reason, the charge of the nitride film is pulled by the high voltage of the bit line and is released by the tunnel effect. After this release, a verify read is performed to check whether the release amount is sufficient.If the release amount is not enough, further release is performed, and charge release and verify read are performed until the memory cell reaches an optimal threshold voltage. Repeated. The verify read for confirming the erased state may be performed by setting the voltage supplied to the word line, that is, the gate of the memory cell to a lower value than in the normal read. Then, it is checked whether the memory cell is turned on at this low voltage. When the memory cell is turned on, the threshold voltage of the memory cell is lower than the voltage supplied to the word line. Therefore, the threshold voltage of the memory cell to be set when erasing is completed is determined based on the voltage of the word line. I can do it. The bias circuit 107 outputs a high voltage at which data can be erased when data is erased, and outputs a predetermined voltage when data is read.
The bit lines BL1 to BL8 each have a gate connected to the signal CU.
The transistors 1a to 8a controlled by the I to CU8 are connected to one ends of the transistors 1a to 8a. The other ends of the transistors 1a to 8a are connected in common and are connected to the sense amplifier 106 via a transistor Tl which is turned on when reading data. At the same time, it is connected to the data write circuit 105 via the transistor T2 which is turned on at the time of data programming, that is, at the time of data writing. Bit line BL2
BL9 to BL9 are respectively connected to one end of transistors 1c to 8c whose gates are controlled by signals CLI to CL8, and the other ends of these transistors 1c to 8c are commonly connected to a ground potential 107. Signals CUI to CU8, signal CL
The logic levels of I to CL8 and signals CB1 to CB9 are determined by an address input (not shown). Signal CUI
10 to CU8, signals CLI to CL8, signals CB1 to CB
One example of 9 logic levels is shown in FIG.

In the example shown in FIG. 5, when the signal W and the signal R are both data of logic "0", the signals CUI to CU are erased.
8, all the signals CLI to CL8 become logic "0", and the transistors 1a to 8a and 1c to which these signals are supplied.
8c is turned off, and signals CB1 to CB8 are all logical "1".
And transistors 1b to 1b to which these signals are supplied.
9b are all turned on, and the bit lines BL1 to BL9 are connected to the bias circuit 107 and supplied with a high voltage for erasing. At the time of this erasure, the word lines WLI to WL8 are all set to logic "0" (for example, ground potential). At the time of verify read for checking the erase state, the power supply voltage V1 supplied to the row decoder 101 is set to a predetermined voltage. In the example of FIG. 5, once the transistors 1a to 9a are turned on once, the on state is continued as it is,
c to 9c are all on in the initial state, and are sequentially turned off one by one while maintaining that state.

Next, a data program will be described with reference to FIG. When programming data, signal W is set to logic "1" and signal R is set to logic "0". In this embodiment, programming is sequentially performed from the memory cell connected to the bit line BL1 to the bit line BL8.
The address of the memory cell is designated by inputting an address, and the bit line BL is sequentially designated according to the contents of the address.
1 and BL2 are programmed, then the memory cells between bit lines BL2 and BL3 are programmed, and then the column of memory cells to be programmed moves sequentially with an increase in address signal, and finally, Bit line B
The memory cells between L8 and BL9 are programmed.

At the time of the first address input, the signal CUI = ""
1 ", CU2-CU8 =" 0 ", signals CL1-CL8 =
Set to “1”. Therefore, the bit lines BL2 to BL9
Are connected to a ground circuit 108 via transistors 1c to 8c whose gates are supplied with signals CLI to CL8 of "1", and are supplied with a ground potential. The bit line BL1 is a transistor 1a having a gate supplied with a signal CUI of "1".
And the transistor T2 connected to this transistor and supplied with the signal W to the gate, and connected to the data write circuit 105 as shown in FIG. Accordingly, a high voltage is supplied from the data writing circuit 105 to the bit line BL1. If the selected word line is set to a high voltage, a current flows from the bit line BL1 to BL2 through the memory cell connected to this word line, charges are injected into the nitride film of the memory cell, and data is written.

If the selected word line remains at the same reference potential as the non-selected word line, no current flows through the selected memory cell, so that the erased state is maintained and no data is written. . When the programming of the data in the memory cell between the bit lines BLI and BL2 is completed,
The address changes and the memory cell between bit lines BL2 and BL3 is programmed. As shown in FIG.
I = CU2 = "1", CU3 to CU8 = "0", and the signals CLI = "0" and CL2 to CL8 = "1"
Is set to Therefore, a high voltage is supplied to the bit lines BL1 and BL2, and the bit lines BL3 to BL9 are set to the ground potential. If the selected word line is set to a high voltage, a current flows through the memory in which the high voltage is supplied to the gate between the bit lines BL2 and BL3, and charges are injected into the nitride film of this memory cell. Also, the bit line BLI
Even if a high voltage is supplied to the gates of the memory cells between the bit lines BL1 and BL2, the bit lines BL1 and BL2 are both set to a high voltage, so that a current flows through the memory cells between these bit lines. And the threshold state does not change.

Next, reading of data from the memory cell programmed in the above procedure will be described. When reading data, the signal W is set to logic "0" and the signal R is set to logic "1". At the time of the first address input,
Memory cells 11 to 11 between bit lines BL1 and BL2
18 is selected. At this time, as shown in FIG. 5, since the signal CUI and the signal CLI are set to logic "1", the transistors 1a and 1c to which the signal CUI and the signal CLI are supplied turn on, and the bit line BL1
Is connected to the sense amplifier 106 via the transistor 1a supplied with the signal CLI to the gate and the transistor T2 supplied with the signal R of logic "1" and turned on. The bit line BL2 is connected to the ground circuit 108 via the transistor 1c whose gate is supplied with the signal CLI, and is supplied with a ground potential. For example, when the word line WLI is selected and set to logic "1", the memory cell 11 is selected. On the other hand, the signals CB1 and CB2 become logic "0",
The signals CB3 to CB9 are set to logic "1", and the unselected bit lines BL3 to BL9 are connected to the bias circuit 107 via the transistors 3b to 9b to which the signals CB3 to CB9 are supplied to the gates, and a predetermined voltage is applied. Supplied.

The case where the memory cell 11 is selected will be described in more detail. As described above, the ground potential is supplied to the bit line BL2. That is, one end of the memory cell 11 connected to the bit line BL2 is connected to the ground potential. The other end of the memory cell 11 is connected to the sense amplifier 106. In the memory cell, logic “0” and logic “1” are stored depending on the magnitude of the threshold voltage. That is, at the time of data programming, the nitride film 12
A memory cell into which charges have been injected to 0 has a high threshold voltage, and a memory cell in an erased state in which no charges have been injected at the time of data programming has a low threshold voltage. When the threshold voltage is high, the word line becomes logic "1", and the selected memory cell does not turn on even when a memory cell is selected, and turns on when the threshold voltage is low.

Now, of the memory cells between the bit lines BL1 and BL2, the word line WL2 to the word line WL8 are logic "0" and are in the non-selected state, so the memories connected to the word lines WL2 to WL8. The cell is off, and when the memory cell 11 has a high threshold voltage, the word line WLI
Is a logic "1", the memory cell 11 is turned off. Therefore, the bit line BL1 is charged by the load transistor of the sense amplifier, and this charged state is detected by the sense amplifier. Is determined to be logic "1". When the threshold voltage of the memory cell 11 is low, the memory cell 11 is turned on, so that the bit line BL1 is discharged toward the ground potential through the memory cell 11 and the bit line BL2, and this discharge state is detected by the sense amplifier 106. For example, it is determined that the storage data of the memory cell 11 is logic “0”.

When memory cell 21 is selected, bit line BL2 is connected to sense amplifier 106 and bit line B
L3 is connected to the ground potential. Therefore, the bit line BL2
When the threshold voltage of the memory cell 21 is high, the bit line BL2 is electrically isolated from the bit line BL3. Therefore, the bit line BL2 is charged by the load transistor of the sense amplifier. Is detected. On the other hand, when the threshold voltage of the memory cell 21 is low, the bit line BL2 is discharged toward the ground potential 108 through the memory cell 21 and the bit line BL3, and this discharge state is detected by the sense amplifier 106.

By the way, in the nonvolatile semiconductor memory device configured as described above, a memory cell whose word line is logic "1" and data should not be read is turned on when the threshold voltage is low. For example, when the memory cell 41 is selected and the threshold voltage of the memory cell 41 is high, the memory cell 41 is turned off. However, when the threshold voltage of the memory cell 31 adjacent to the memory cell 41 is low, the memory cell 31 is turned on. For example, when the threshold voltages of the memory cells 31 and all the memory cells 21 and 11 arranged on the right side of the memory cell 31 and connected to the word line WLI in FIG. 4 are low, the bit lines BL4 and BL4 are passed through these memory cells. Are connected through the memory cells.

Assuming that these bit lines are at the ground potential, the load transistor of the sense amplifier 106 causes BL4 to pass through the memory cell when bit line BL4 is charged.
, All the bit lines on the right side are also charged, and the data in the memory cell 41 cannot be read until the charging is completed, and the data reading speed is reduced. To prevent this, as described above, unselected bit lines
It is charged to a predetermined potential by the bias circuit 107.

[0050]

As described in detail above, according to the present invention,
Since a predetermined bias is applied without setting the source and the drain of the connected unselected memory cell transistor before and after the selected memory cell transistor to a floating state, the memory cell selected at the time of writing and reading operation It is possible to provide a semiconductor memory device capable of effectively avoiding erroneous writing and erroneous reading to a memory cell transistor other than a transistor.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a substrate configuration of the memory cell row in FIG. 1;

FIG. 3 is a cross-sectional view illustrating the configuration of the memory cell transistor illustrated in FIG. 2 in detail;

FIG. 4 is a detailed diagram of a bias control circuit according to the embodiment of FIG.

FIG. 5 is a logical value table for explaining the operation of the circuit of FIG. 4;

[Explanation of symbols]

 A1 to A4 bias control circuit 1a to 9b switch transistor Ce memory cell array 101 row decoder 102 column decoder 103 bit line control circuit 104 program circuit 105 data write circuit 106 sense amplifier 107 bias circuit 108 Ground circuit

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[Procedure amendment]

[Submission date] July 15, 1999 (1999.7.1)
5)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claim 3

[Correction method] Change

[Correction contents]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0021

[Correction method] Change

[Correction contents]

The memory cell transistor M formed between the source region 112-3 and the drain region 113-3
5, the source regions 112-3, 112
-4, 112-5 and drain regions 113-2, 113-
3 and 113-4, respectively.
1, M2, M3, M4, and M6 are formed. In this embodiment, the source regions 112-3, 112-4, 1
12-5 and drain regions 113-2, 113-3, 11
As will be described later, each of the bit lines BLn-
1,... BLn + 4.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0023

[Correction method] Change

[Correction contents]

On the other hand, unselected bit lines BL0, BL3,
The selected memory cell transistor M3 of BL4
In the bias circuits A3 and A4 connected to the bit lines BL3 and BL4 arranged adjacent to the source region 112-4, the respective first switch transistors 1a receive signals from the decode circuit De or the addition / subtraction circuit AS. Is conducted, and the low voltage source Vs is applied to the bit lines BL3 and BL4, respectively.
A low potential Vss is supplied from s.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0024

[Correction method] Change

[Correction contents]

In the bias circuit A0 connected to the bit line BL0 of the memory cell transistor M2 arranged adjacent to the drain region 113-4 of the selected memory cell transistor M3, the decoding circuit De or the addition / subtraction circuit The second switch transistor 1b is turned on by the signal from the AS, and the high potential Vpp is supplied to the bit line BL0 from the high voltage source Vpp.

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0027

[Correction method] Change

[Correction contents]

At the time of writing, the potential of the substrate 111 and the potential of the source region 112-4 are fixed at "0" volts, respectively, and a voltage for "0" writing, for example, 5 volts, is applied to the drain region 113-4. In this state, a predetermined high voltage for writing, for example, 7 volts is applied to the gate electrode (word line WL) 122.

[Procedure amendment 6]

[Document name to be amended] Statement

[Correction target item name] 0028

[Correction method] Change

[Correction contents]

Then, since the plus voltage is higher below the drain region 113-4 than the source region 112-4, the depletion layer 125 in the substrate 111 extends deeper, as shown in FIG.

[Procedure amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0030

[Correction method] Change

[Correction contents]

In this state, hot electrons are generated from the tip of the channel 126. Most of the generated hot electrons e1 are in the drain region 113-4.
Is moved along the surface region of the substrate 111 in the direction of, but a portion e2 passes through the insulating film 119 due to the electric field effect of the gate electrode 122 and is trapped and stored in the nitride film 120.

[Procedure amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0031

[Correction method] Change

[Correction contents]

At this time, in the memory cell transistor M2 adjacent to the selected memory cell transistor M3 on the drain region 113-4 side, the source region 112-5 and the drain region (not shown) of the selected memory cell transistor M3 are connected to the selected drain region 113. Since the bias is biased to Vpp which is the same writing potential as −4, the depletion layer 125 is in the region 11 as shown in FIG.
Only slightly extend along 2-5,..., The current flowing from the selected memory cell transistor M3 to the adjacent unselected memory cell transistors M2 is minimized, and erroneous writing is prevented. .

[Procedure amendment 9]

[Document name to be amended] Statement

[Correction target item name] 0036

[Correction method] Change

[Correction contents]

Control signals CUI-C output from column decoder 102 are connected to the gates of transistors 1a-8a.
U8 is supplied, control signals CB1 to CB9 output from the column decoder 102 are input to the transistors 1b to 9b, and control signals CLI to CL8 output from the column decoder 102 are input to the transistors 1c to 9c. The program circuit 104 includes a data write circuit 105, a sense amplifier 106, a bias circuit 107, and a ground circuit 108.
It is composed of The data write circuit 105 is connected via an N-channel transistor T2 whose ON / OFF is controlled by an external signal W, and the sense amplifier 106 is connected via an N-channel transistor Tl which is turned on / off by an external signal R to select a bit line. Commonly connected to transistors 1 a to 8 a of circuit 103.

[Procedure amendment 10]

[Document name to be amended] Drawing

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 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Yuichi Tatsumi 25-1, Ekimae Honcho, Kawasaki-ku, Kawasaki City, Kanagawa Prefecture Inside Toshiba Microelectronics Corporation (72) Inventor Hitoshi Ota 25-1, Ekimae Honcho, Kawasaki-ku, Kawasaki City, Kanagawa Prefecture Toshiba Within Microelectronics Co., Ltd. (72) Noriaki Suzuki, Inventor 25-1, Ekimae Honmachi, Kawasaki-ku, Kawasaki, Kanagawa Prefecture Within Toshiba Microelectronics Co., Ltd. (72) Inventor Hidenobu Minagawa 25-1, Ekimae Honcho, Kawasaki-ku, Kawasaki, Kanagawa Toshiba Microelectronics F term (reference) 5B025 AA04 AB02 AC01 AE08 5F001 AA11 AA14 AD12 AE02 AE03 5F083 EP17 EP18 GA15 KA01 KA05 LA03 LA12 LA16

Claims (4)

[Claims] 1. A memory cell array comprising a plurality of memory cell transistors arranged in a matrix in a row direction and a column direction, and a plurality of memory cell transistors in which gates of a plurality of memory cell transistors arranged in a row direction are commonly connected. A plurality of memory cell transistors arranged in the column direction, a plurality of bit lines having sources and drains connected in common, and a first and a second switching connected in parallel to each of the bit lines. An element, a first voltage source connected to the first switching element, a second voltage source connected to the second switching element, and a selected voltage at the time of writing and reading data to and from the memory cell transistor. The first switch connected to all unselected bit lines arranged on the drain side of the memory cell transistor connected to the connected bit line Control means for conducting the switching element and conducting the second switching elements connected to all the non-selected bit lines arranged on the source side of the memory cell transistor connected to the selected bit line. A semiconductor memory device comprising: 2. The semiconductor memory device according to claim 1, wherein said control means includes a column decoder for selecting a bit line by an address signal at the time of writing and reading. 3. The memory cell array includes a semiconductor substrate of a first conductivity type, a source region of a second conductivity type formed in the semiconductor substrate, and a second region formed at a predetermined distance from the source region. A drain region of a conductivity type, a source electrode connected to the source region, and an offset having a constant width between the source region and the drain region and a bottom surface formed to cover the surface of the semiconductor substrate. A non-offset sidewall having an edge coincident with an edge of the drain region facing the source region, the bottom surface of which is formed so as to cover the surface of the drain region; and A source electrode connected to the region, a first oxide film formed on the surface of the semiconductor substrate sandwiched between the offset and non-offset sidewalls, A nitride film formed on the oxide film;
A plurality of non-volatile memory cell transistors each having a second oxide film formed on the nitride film and a gate electrode commonly formed above the source region, the drain region, and the second oxide film Writing means for accumulating an amount of charge in the nitride film according to a gate voltage value applied to the gate electrode at the time of data writing; 2. The semiconductor memory device according to claim 1, further comprising: reading means for reading out, as data, an output corresponding to the amount of charge accumulated in the nitride film. 4. A plurality of source regions having offset sidewalls and drain regions having non-offset sidewalls are alternately arranged in the row direction, and the non-volatile region is provided between the source electrode and the drain electrode. 4. The semiconductor memory device according to claim 3, wherein each of the memory cell transistors is formed.