JP2000031202A - Packaging body and method of semiconductor device - Google Patents

Packaging body and method of semiconductor device

Info

Publication number
JP2000031202A
JP2000031202A JP15195296A JP15195296A JP2000031202A JP 2000031202 A JP2000031202 A JP 2000031202A JP 15195296 A JP15195296 A JP 15195296A JP 15195296 A JP15195296 A JP 15195296A JP 2000031202 A JP2000031202 A JP 2000031202A
Authority
JP
Japan
Prior art keywords
semiconductor device
contact
main body
body substrate
electronic device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15195296A
Other languages
Japanese (ja)
Other versions
JP3657696B2 (en
Inventor
Yuko Shibusawa
祐子 渋沢
Takeshi Sasaki
剛 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Development and Engineering Corp
Original Assignee
Toshiba Corp
Toshiba Electronic Engineering Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Electronic Engineering Co Ltd filed Critical Toshiba Corp
Priority to JP15195296A priority Critical patent/JP3657696B2/en
Publication of JP2000031202A publication Critical patent/JP2000031202A/en
Application granted granted Critical
Publication of JP3657696B2 publication Critical patent/JP3657696B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75Apparatus for connecting with bump connectors or layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Liquid Crystal (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To improve the connecting precision as well as the yield by discriminating the acceptability of bump abutting status on wiring terminals in the packaging time of a semiconductor device following the chip on glass mode. SOLUTION: The dummy bumps 16 abutting on a main body substrate 10 are formed in the case of abutting the bumps 13 on the wiring terminals made of the same material as that of the bumps 13 against a liquid crystal driver chip 12 and then the abutting status of the bumps 13 is detected from the backside of the main body substrate so as to discriminate the acceptability of the abutting status of the bumps 13. Finally, corresponding to the discrimination results, the connection requirements of COG(chip on glass) bonder is adjusted to improve the connecting precision of the abutting status of the bumps 13 on the wiring terminals.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体装置の実装
に関し、特に半導体装置のベアチップを基板に直接フェ
ースダウンにて実装する半導体装置の実装体及び半導体
装置の実装方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device mounting method and a semiconductor device mounting method in which a bare chip of the semiconductor device is directly mounted face down on a substrate.

【0002】[0002]

【従来の技術】近年、アクティブマトリクス型の液晶表
示装置の様な電子装置において、ガラス等からなる本体
基板上に配列される薄膜トランジスタ(以下TFTと略
称する。)等の電子回路を駆動あるいは制御する半導体
装置を、直接本体基板上に搭載するチップオングラス
(以下COGと略称する。)と呼ばれる実装方式が開発
されている。このCOGによる実装方式の内、特に狭い
ピッチでの実装が可能であり、大型の液晶表示装置への
適用が可能とされているフェースダウン方式にあって
は、半導体装置のバンプを、異方性導電膜を介して基板
上の電子装置の配線端子に接続したり、光硬化性等の接
着樹脂にて配線端子に接続するが、この接続時、バンプ
と配線端子との導通状態を検知しあるいはバンプと配線
端子とのずれや、半導体装置の基板に対する傾き等を検
知する手段を有していなかった。
2. Description of the Related Art In recent years, in an electronic device such as an active matrix type liquid crystal display device, an electronic circuit such as a thin film transistor (hereinafter abbreviated as TFT) arranged on a main substrate made of glass or the like is driven or controlled. A mounting method called a chip-on-glass (hereinafter abbreviated as COG) for mounting a semiconductor device directly on a main body substrate has been developed. Among the COG mounting methods, the face-down method, in which mounting at a particularly narrow pitch is possible and which can be applied to a large-sized liquid crystal display device, uses anisotropic bumps in a semiconductor device. It is connected to the wiring terminal of the electronic device on the substrate via the conductive film, or is connected to the wiring terminal with an adhesive resin such as photo-curing. At this connection, the conduction state between the bump and the wiring terminal is detected or There is no means for detecting the displacement between the bump and the wiring terminal, the inclination of the semiconductor device with respect to the substrate, and the like.

【0003】但し従来、Tape Carrier P
ackage(以下TCPと略称する。)とガラス基板
上の端子とを異方性導電膜にて接続する際の接続性を検
知するものとして、特開平4−287023号公報に
は、ガラス基板側に透明導電膜からなるダミー端子を設
け、ダミー端子位置における異方性導電膜中の導電粒子
のつぶれ具合を観察する事により接続状態を検知する旨
が開示されている。
However, conventionally, Tape Carrier P
Japanese Patent Application Laid-Open No. 4-287,023 discloses a technique for detecting the connectivity when an package (hereinafter abbreviated as TCP) and a terminal on a glass substrate are connected by an anisotropic conductive film. It is disclosed that a dummy terminal made of a transparent conductive film is provided, and the connection state is detected by observing the degree of collapse of the conductive particles in the anisotropic conductive film at the position of the dummy terminal.

【0004】[0004]

【発明が解決しようとする課題】しかしながら上記TC
Pとガラス基板上の端子との接続状態の観察方法を、ア
クティブマトリクス型の液晶表示装置の駆動制御を行う
半導体装置のCOGによる実装に適応しようとすると、
ガラス基板上の端子が透明導電膜に限定されない事か
ら、端子が不透明な導電膜から成る場合には、接続状態
の観察が不能になり、この様な装置にあっては、その場
での導通検査等を行え無い。したがってガラス基板に半
導体装置を接続した後、プロービング等の電気的接続検
査を行って、初めて導通不良が判明し、更にはその原因
となる半導体装置のずれや傾きが判明する事となり、接
続精度が著しく低下され、歩留まりが悪くなるという問
題を有していた。
However, the above TC
When an observation method of a connection state between P and a terminal on a glass substrate is adapted to COG mounting of a semiconductor device that performs drive control of an active matrix liquid crystal display device,
Since the terminals on the glass substrate are not limited to the transparent conductive film, if the terminals are made of an opaque conductive film, it is impossible to observe the connection state. Inspection cannot be performed. Therefore, after connecting the semiconductor device to the glass substrate, an electrical connection test such as probing is performed, and a conduction failure is found only for the first time. Further, a shift or inclination of the semiconductor device which causes the failure is found, and the connection accuracy is reduced. There is a problem that the yield is remarkably reduced and the yield is deteriorated.

【0005】そこで本発明は上記課題を除去するもの
で、基板上に形成される配線端子の材質に拘らず、配線
端子に対するバンプの当接状態を即座に検知可能であ
り、配線端子に対するバンプの導通状態を検知し、更に
は、配線端子に対するバンプの位置ずれや、傾きずれを
検知出来、これら検知結果に基ずきバンプ及び配線端子
の接続条件を調整可能とする事によりCOGによる半導
体装置の基板への接続精度を向上し、良好な特性を有す
る半導体装置の実装体及び半導体装置の実装方法を提供
する事を目的とする。
SUMMARY OF THE INVENTION The present invention has been made to solve the above problem, and it is possible to immediately detect the state of contact of a bump with a wiring terminal regardless of the material of the wiring terminal formed on the substrate, and to determine whether the bump of the bump with respect to the wiring terminal is present. The conductive state can be detected, and furthermore, the displacement and inclination of the bump with respect to the wiring terminal can be detected, and the connection conditions of the bump and the wiring terminal can be adjusted based on the detection result, thereby enabling the COG of the semiconductor device. It is an object of the present invention to provide a semiconductor device mounting body and a method for mounting a semiconductor device, which have improved connection accuracy to a substrate and have good characteristics.

【0006】[0006]

【課題を解決するための手段】本発明は上記課題を解決
するための手段として、電子装置の配線端子を有する本
体基板と、前記配線端子に対向して当接し前記電子装置
と導通する突起電極を有する半導体装置とを具備する半
導体装置の実装体において、前記半導体装置が、前記突
起電極と同一材質からなり前記突起電極の前記接続端子
への当接時に前記本体基板に当接し前記電子装置と非導
通の突起を有し、前記本体基板が前記突起との当接面を
反対の面から検知可能とするものである。
According to the present invention, as a means for solving the above-mentioned problems, there is provided a main substrate having wiring terminals of an electronic device, and a protruding electrode which is in contact with the wiring terminals and is electrically connected to the electronic device. Wherein the semiconductor device is made of the same material as the protruding electrode and is in contact with the main body substrate when the protruding electrode abuts on the connection terminal. It has a non-conductive protrusion, and enables the main substrate to detect a contact surface with the protrusion from an opposite surface.

【0007】又本発明は上記課題を解決するための手段
として、電子装置の配線端子を有する本体基板と、前記
配線端子に対向して当接し前記電子装置と導通する突起
電極を有する半導体装置とを具備する半導体装置の実装
方法において、前記半導体装置に更に前記突起電極と同
一材質からなり前記突起電極の前記配線端子への当接時
に前記本体基板に当接し前記電子装置と非導通の突起を
設け、この突起を前記本体基板にフェースダウンにて当
接する工程と、前記本体基板に当接された前記突起を前
記当接面と反対の面から検知する工程とを実施するもの
である。
According to another aspect of the present invention, there is provided a semiconductor device having a main body substrate having wiring terminals of an electronic device, and a semiconductor device having a protruding electrode which is in contact with the wiring terminals and is electrically connected to the electronic device. In the method for mounting a semiconductor device, the semiconductor device further comprises a protrusion which is made of the same material as the protruding electrode and which is in contact with the main body substrate when the protruding electrode is in contact with the wiring terminal, and which is not conductive with the electronic device. A step of contacting the projection with the main body substrate face down, and a step of detecting the projection contacted with the main body substrate from a surface opposite to the abutting surface.

【0008】そして本発明は上記手段により、本体基板
と突起との当接面を本体基板の反対の面から検知する事
により、配線端子に対するバンプの当接状態を検知し
て、COGによる接続精度を向上し、半導体装置の特性
向上を図るものである。
According to the present invention, the state of contact of the bump with the wiring terminal is detected by detecting the contact surface between the main substrate and the projection from the opposite surface of the main substrate by the above means, and the connection accuracy by COG is detected. To improve the characteristics of the semiconductor device.

【0009】[0009]

【発明の実施の形態】以下、本発明の第1の実施の形態
を図1乃至図6を参照して説明する。透明なガラスから
なる本体基板10上には、電子装置であり電極基板(図
示せず)間に液晶組成物(図示せず)を保持してなる液
晶表示素子11が設けられ、額縁領域10aには、半導
体装置である液晶ドライバチップ12の突起電極である
バンプ13と接続され、液晶表示素子11に制御信号を
入力するための配線端子14が設けられている。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. A liquid crystal display element 11, which is an electronic device and holds a liquid crystal composition (not shown), is provided between electrode substrates (not shown) on a main substrate 10 made of transparent glass. Are connected to bumps 13 which are projection electrodes of a liquid crystal driver chip 12 which is a semiconductor device, and are provided with wiring terminals 14 for inputting control signals to the liquid crystal display element 11.

【0010】一方、液晶ドライバチップ12には、登頂
面積がバンプ13の登頂面積と同じであり、バンプ13
と同一材質からなる突起であるダミーバンプ16が設け
られている。そしてこの様な液晶ドライバチップ12
を、透明接着剤である熱可塑接着剤中に導電性材料であ
る金属粒子17を分散させて成る異方性導電膜を介し本
体基板10にCOGにて接続する事となる。
On the other hand, the liquid crystal driver chip 12 has an ascending area equal to the ascending area of the bump 13.
And a dummy bump 16 which is a projection made of the same material as that of the first embodiment. And such a liquid crystal driver chip 12
Is connected to the main substrate 10 by COG via an anisotropic conductive film obtained by dispersing metal particles 17 as a conductive material in a thermoplastic adhesive as a transparent adhesive.

【0011】又図3は、COGボンダ18の概略構成を
示し、20は液晶ドライバチップ12を固定支持する加
熱加圧ツール、21は本体基板10を設置する透明なス
テージ、22は上下同時あるいはシャッタを装備して上
下別々に液晶ドライバチップ12及び本体基板10の位
置を検知する位置合わせカメラ光学系、23は位置合わ
せカメラ光学系22からの映像を表示するモニタ、24
はステージ21の下より本体基板10を観察する下部カ
メラ光学系、26は下部カメラ光学系24からの映像を
表示する下部モニタである。
FIG. 3 shows a schematic configuration of the COG bonder 18. Reference numeral 20 denotes a heating / pressing tool for fixedly supporting the liquid crystal driver chip 12, reference numeral 21 denotes a transparent stage on which the main body substrate 10 is set, and reference numeral 22 denotes an upper and lower simultaneous or shutter. , An alignment camera optical system for separately detecting the positions of the liquid crystal driver chip 12 and the main body substrate 10, a monitor 23 for displaying an image from the alignment camera optical system 22,
Reference numeral denotes a lower camera optical system for observing the main body substrate 10 from below the stage 21, and reference numeral 26 denotes a lower monitor for displaying an image from the lower camera optical system 24.

【0012】次にCOGボンダ18により本体基板10
に液晶ドライバチップ12を接続する工程を図6に示す
フローチャートを参照して説明する。先ず加熱加圧ツー
ル20及びステージ21に液晶ドライバチップ12及び
配線端子14を有する本体基板10をそれぞれ取り付け
た後、ステップ27に示す様に、位置合わせカメラ光学
系22を本体基板10及び液晶ドライバチップ12の間
に挿入し、配線端子14及びバンプ13の位置を検知
し、モニタ23に表示し、ステップ28に進む。ステッ
プ28では、検知結果より図示しない制御装置にて配線
端子14及びバンプ13の座標を出力し、駆動手段(図
示せず)にて加熱加圧ツール20又はステージ21を移
動し配線端子14及びバンプ13の座標を重ね合わせ、
ステップ30にて位置合わせカメラ光学系22を後退さ
せる。
Next, the main substrate 10 is moved by the COG bonder 18.
The process of connecting the liquid crystal driver chip 12 to the LCD will be described with reference to the flowchart shown in FIG. First, the main body substrate 10 having the liquid crystal driver chip 12 and the wiring terminals 14 is attached to the heating / pressing tool 20 and the stage 21, respectively. Then, as shown in step 27, the alignment camera optical system 22 is connected to the main body substrate 10 and the liquid crystal driver chip. 12, the positions of the wiring terminals 14 and the bumps 13 are detected and displayed on the monitor 23, and the process proceeds to step 28. In step 28, the coordinates of the wiring terminals 14 and the bumps 13 are output by a control device (not shown) from the detection result, and the heating / pressing tool 20 or the stage 21 is moved by a driving means (not shown) to move the wiring terminals 14 and the bumps 13. 13 coordinates are superimposed,
In step 30, the positioning camera optical system 22 is retracted.

【0013】次いでステップ31にて加熱加圧ツール2
0を降下し配線端子14にバンプ13を当接し加熱加圧
して異方性導電膜を熱硬化し配線端子14及びバンプ1
3をボンディングする。このときダミーバンプ16は、
本体基板10上に当接され、異方性導電膜にてボンディ
ングされる。そして、ステップ32にて、下部カメラ光
学系24により本体基板10裏側からダミーバンプ16
に挾まれる金属粒子17の粒子数を検出し、ステップ3
3にて、粒子数が許容範囲に達しているか否かを比較
し、許容範囲に達しており、これと同面積のバンプ13
及び配線端子14間における粒子数も同様であることか
らバンプ13及び配線端子14間で良好な導通が得られ
ると判断した場合は、ボンディング操作を終了する一
方、ダミーバンプ13位置の金属粒子17の数が少な
く、許容範囲に達していない場合は、バンプ13及び配
線端子14間の粒子数も少ない事からその導通が不良で
ある旨を判断し、ステップ34にて不良警告を発した後
終了する事となる。
Next, at step 31, the heating and pressing tool 2
0, the bump 13 is brought into contact with the wiring terminal 14, and is heated and pressurized to thermally cure the anisotropic conductive film.
3 is bonded. At this time, the dummy bumps 16
It is brought into contact with the main body substrate 10 and is bonded with an anisotropic conductive film. Then, in step 32, the lower camera optical system 24 allows the dummy bump 16
The number of metal particles 17 sandwiched between the two is detected, and step 3
At 3, it is compared whether or not the number of particles has reached an allowable range.
When it is determined that good conduction can be obtained between the bump 13 and the wiring terminal 14 because the number of particles between the wiring terminals 14 is the same, the bonding operation is terminated while the number of metal particles 17 at the position of the dummy bump 13 is determined. If the number of particles is less than the allowable range, the number of particles between the bump 13 and the wiring terminal 14 is also small, so that it is determined that the continuity is defective. Becomes

【0014】但し金属粒子17の粒子数の検知は、下部
カメラ光学系24にて検知したダミーバンプ16及び本
体基板10間の金属粒子17の正反射画像を基に、つぶ
れた金属粒子17の総面積と、正常につぶれた金属粒子
17の1個当たりの面積から算出する。
However, the number of the metal particles 17 is detected based on the specular reflection image of the metal particles 17 between the dummy bump 16 and the main substrate 10 detected by the lower camera optical system 24. Is calculated from the area per one of the normally crushed metal particles 17.

【0015】この様に構成すれば、配線端子14が透明
でないにも拘らず、ダミーバンプ16を透明な本体基板
10下方から検知し、ダミーバンプ16位置における金
属粒子17の粒子数を認識する事により、バンプ13及
び配線端子14間の粒子数を同等と認識して導通状態を
検知出来、液晶ドライバチップ12の実装時の良否を判
別可能となる。
With this configuration, the dummy bumps 16 are detected from below the transparent main body substrate 10 and the number of the metal particles 17 at the positions of the dummy bumps 16 is recognized, even though the wiring terminals 14 are not transparent. By recognizing that the number of particles between the bump 13 and the wiring terminal 14 is equivalent, the conduction state can be detected, and it is possible to determine whether the liquid crystal driver chip 12 is mounted or not.

【0016】次に本発明の第2の実施の形態を図7を参
照して説明する。尚この第2の実施の形態は、第1の実
施の形態において液晶ドライバチップが登頂面積の異な
る複数種のバンプを有するものであり、他は第1の実施
の形態と同一である事から、同一部分については同一符
号を付しその説明を省略する。
Next, a second embodiment of the present invention will be described with reference to FIG. Note that the second embodiment is different from the first embodiment in that the liquid crystal driver chip has a plurality of types of bumps having different ascending areas, and is otherwise the same as the first embodiment. The same parts are denoted by the same reference numerals, and description thereof will be omitted.

【0017】即ち本実施の形態の液晶ドライバチップ3
6には、登頂面積の大きい第1のバンプ37及び登頂面
積の小さい第2のバンプ38が突設され、更に登頂面積
が第2のバンプ38と同一のダミーバンプ40が形成さ
れている。そしてCOGボンダ18は、本体基板10上
のそれぞれ第1及び第2のバンプ37、38の登頂面積
と同じ面積を有する配線端子(図示せず)と第1及び第
2のバンプ37、38とのボンディングを行うが、ボン
ディング後、下部カメラ光学系24にて本体基板10裏
面よりダミーバンプ40と本体基板間の金属粒子17の
数を検知し、面積の小さい第2のバンプ38と配線端子
(図示せず)間の導通が良好で有る旨を判断すれば、面
積の大きい第1のバンプ37における導通状態も良好で
あると類推し、配線端子(図示せず)と両バンプ37、
38間の導通の良否を判別するものである。
That is, the liquid crystal driver chip 3 of the present embodiment
In FIG. 6, a first bump 37 having a large ascending area and a second bump 38 having a small ascending area are protruded, and a dummy bump 40 having the same ascending area as the second bump 38 is formed. The COG bonder 18 is connected to a wiring terminal (not shown) having the same area as the top area of the first and second bumps 37 and 38 on the main substrate 10 and the first and second bumps 37 and 38, respectively. Bonding is performed. After bonding, the number of the metal bumps 17 between the dummy bumps 40 and the main body substrate is detected from the back surface of the main body substrate 10 by the lower camera optical system 24, and the second bumps 38 having a small area and wiring terminals (shown in FIG. If it is determined that the conduction between them is good, it is assumed that the conduction state of the first bump 37 having a large area is also good, and a wiring terminal (not shown) and both bumps 37,
This is to determine the quality of conduction between the 38.

【0018】この様に構成すれば、登頂面積の異なる第
1及び第2のバンプ37、38を本体基板10にCOG
にて接続する場合でも、面積の小さい第2のバンプ38
と同一登頂面積のダミーバンプ40における金属粒子1
7の粒子数を認識する事により、第1のバンプ37に比
し、導通不良を生じ易い面積の小さい第2のバンプ38
及び配線端子(図示せず)間の導通状態の良否を判定す
るのみで、面積の大きい第1のバンプ37の導通状態の
良否の判別をカバー出来、各サイズ毎に良否を判定する
事なく、実装時の良否判定が可能と成る。
According to this structure, the first and second bumps 37 and 38 having different ascending areas are formed on the main substrate 10 by COG.
The second bump 38 having a small area is
Metal particles 1 in the dummy bump 40 having the same ascending area
By recognizing the number of particles 7, the second bump 38, which has a smaller area where conduction failure is more likely to occur than the first bump 37.
Only by judging the quality of the conduction state between the wiring terminals (not shown), it is possible to cover the judgment of the quality of the conduction state of the first bump 37 having a large area, without judging the quality of each size. Pass / fail judgment at the time of mounting becomes possible.

【0019】次に本発明の第3の実施の形態を図8及び
図9を参照して説明する。尚この第3の実施の形態は、
第1の実施の形態のダミーバンプ16を液晶ドライバチ
ップ12に2個設けるものであり、他は第1の実施の形
態と同一である事から、同一部分については同一符号を
付しその説明を省略する。
Next, a third embodiment of the present invention will be described with reference to FIGS. Note that this third embodiment is
Since two dummy bumps 16 according to the first embodiment are provided on the liquid crystal driver chip 12 and the other components are the same as those of the first embodiment, the same portions are denoted by the same reference numerals and description thereof is omitted. I do.

【0020】本実施の形態にあっては第1及び第2のバ
ンプ41a、41bを有する液晶ドライバチップ42の
対角線上の2箇所に、面積の小さい第2のバンプ41b
と同一登頂面積、同一材質からなる第1及び第2のダミ
ーバンプ43、44を設け、本体基板(図示せず)への
当接時における両ダミーバンプ43、44位置における
金属粒子(図示せず)のつぶれ具合により、液晶ドライ
バチップ42の傾きを検知する事となる。
In the present embodiment, the second bumps 41b having a small area are provided at two positions on the diagonal of the liquid crystal driver chip 42 having the first and second bumps 41a and 41b.
First and second dummy bumps 43 and 44 made of the same material and having the same ascending area are provided, and the metal particles (not shown) at the positions of the dummy bumps 43 and 44 at the time of contact with the main body substrate (not shown) are provided. The inclination of the liquid crystal driver chip 42 is detected based on the degree of the collapse.

【0021】即ちCOGボンダ18により本体基板(図
示せず)に液晶ドライバチップ42を接続する工程は、
ステップ27からステップ31迄は第1の実施の形態の
図6にて説明したフローチャートと同様であるものの、
その後は、図9のフローチャートに示す様に、ステップ
46にて下部カメラ光学系24により図示しない本体基
板裏側から、第1及び第2のダミーバンプ43、44が
当接される2箇所の金属粒子のつぶれ具合あるいは金属
粒子の片寄りを検出し、ステップ47にて金属粒子のつ
ぶれ具合が均等であるか否かあるいは金属粒子が片寄っ
ているか否かを比較し、両ダミーバンプ43、44位置
でのつぶれ具合が均等である場合あるいは金属粒子の片
寄りが無い場合は、ボンディング操作を終了する一方、
両ダミーバンプ43、44における金属粒子のつぶれ具
合が均一で無かったりあるいは片寄りがあり、加熱加圧
ツール20や液晶ドライバチップ42が傾いている場合
は、ステップ48に進み、傾き量を算出してオフセット
量に変換し、次の接続工程のため加熱加圧ツール20の
傾き状態のオフセット設定を自動的に行った後、ボンデ
ィング操作を終了する。
That is, the step of connecting the liquid crystal driver chip 42 to the main body substrate (not shown) by the COG bonder 18 includes:
Steps 27 to 31 are the same as the flowchart described in FIG. 6 of the first embodiment,
Thereafter, as shown in the flowchart of FIG. 9, in step 46, the lower camera optical system 24 removes two metal particles from the back side of the main body substrate (not shown) where the first and second dummy bumps 43 and 44 come into contact. The degree of crushing or the deviation of the metal particles is detected, and in step 47, it is compared whether the degree of crushing of the metal particles is uniform or whether the metal particles are deviated, and the crushing at the positions of the dummy bumps 43 and 44 is performed. If the condition is uniform or there is no deviation of the metal particles, the bonding operation is terminated,
If the degree of crushing of the metal particles in the dummy bumps 43 and 44 is not uniform or uneven, and the heating / pressing tool 20 or the liquid crystal driver chip 42 is inclined, the process proceeds to step 48 to calculate the amount of inclination. After converting to the offset amount and automatically performing the offset setting of the inclined state of the heating and pressing tool 20 for the next connection step, the bonding operation is completed.

【0022】尚、金属粒子のつぶれ具合の検知は、下部
カメラ光学系24にて検知した正反射直径の大きさで知
る事が出来、金属粒子の片寄りの検知も、下部カメラ光
学系24にて検出した正反射量により知る事が出来る。
The state of the metal particles being crushed can be detected by the size of the regular reflection diameter detected by the lower camera optical system 24, and the detection of the deviation of the metal particles can also be detected by the lower camera optical system 24. Can be known from the amount of specular reflection detected.

【0023】この様に構成すれば、2個の、ダミーバン
プ43、44を透明な本体基板下方から検知して、液晶
ドライバチップ42の傾きを検知し、この検知結果から
COGボンダ18のオフセット設定を自動的に行う事に
より、液晶ドライバチップ42を傾きを生じること無く
良好に接続でき、その実装時の信頼性が向上される。
With such a configuration, the two dummy bumps 43 and 44 are detected from below the transparent main body substrate, the inclination of the liquid crystal driver chip 42 is detected, and the offset setting of the COG bonder 18 is determined from the detection result. The automatic connection enables the liquid crystal driver chip 42 to be connected well without tilting, thereby improving the reliability at the time of mounting.

【0024】次に本発明の第4の実施の形態を図10乃
至図12を参照して説明する。尚この第4の実施の形態
は、第1の実施の形態のダミーバンプ16と対向する本
体基板10上に、位置合わせのための中空のパターンを
形成するものであり、他は第1の実施の形態と同一であ
る事から、同一部分については同一符号を付しその説明
を省略する。
Next, a fourth embodiment of the present invention will be described with reference to FIGS. In the fourth embodiment, a hollow pattern for positioning is formed on the main body substrate 10 facing the dummy bumps 16 of the first embodiment, and the others are the same as those of the first embodiment. Since the configuration is the same as that of the embodiment, the same reference numerals are given to the same components, and the description thereof will be omitted.

【0025】本実施の形態にあっては本体基板10のダ
ミーバンプ16との当接位置に、配線端子14形成と同
時に形成される、ロ字方の位置合わせパターン51が設
けられている。この位置合わせパターン51の中空部5
1aは、ダミーバンプ16の登頂と嵌まりあう形状とな
っており、当接時における、中空部51aとダミーバン
プ16とのずれを検知する事により、バンプ13と配線
端子14とのずれを検知する事となる。
In the present embodiment, a rectangular alignment pattern 51 formed at the same time as the formation of the wiring terminals 14 is provided at a position where the main substrate 10 abuts on the dummy bump 16. Hollow portion 5 of this alignment pattern 51
1a has a shape that fits with the top of the dummy bump 16 and detects a displacement between the bump 13 and the wiring terminal 14 by detecting a displacement between the hollow portion 51a and the dummy bump 16 at the time of contact. Becomes

【0026】即ちCOGボンダ18により本体基板10
に液晶ドライバチップ12を接続する工程は、ステップ
27からステップ31迄は第1の実施の形態の図6にて
説明したフローチャートと同様であるものの、その後
は、図12のフローチャートに示す様に、ステップ52
にて下部カメラ光学系24により本体基板10裏側か
ら、ダミーバンプ16が当接される位置にて、位置合わ
せパターン51とダミーバンプ16とのずれを検出し、
ステップ53にてずれを生じているか否かを比較し、位
置合わせパターン51の中空部51aとダミーバンプ1
6とが隙間なく嵌まり合い、ずれが無い場合は、ボンデ
ィング操作を終了する一方、図11(イ)に示す位置ず
れの様に中空部51aとダミーバンプ16との間にD
1、D2の隙間を検知した場合、あるいは図11(ロ)
に示す軸ずれの様に中空部51aとダミーバンプ16と
の傾きαを検知した場合等、位置ずれ或いは軸ずれを生
じている場合は、ステップ54に進み、位置ずれ量或い
は軸ずれ量を算出してオフセット量に変換し、次の接続
工程のため加熱加圧ツール20或いはステージ21の位
置状態のオフセット設定を自動的に行った後、ボンディ
ング操作を終了する。
That is, the main substrate 10 is provided by the COG bonder 18.
The process of connecting the liquid crystal driver chip 12 to the step is the same as the flowchart described in FIG. 6 of the first embodiment from step 27 to step 31, but thereafter, as shown in the flowchart of FIG. Step 52
The lower camera optical system 24 detects a displacement between the alignment pattern 51 and the dummy bump 16 from the back side of the main body substrate 10 at a position where the dummy bump 16 abuts,
In step 53, it is determined whether or not there is a shift, and the hollow portion 51a of the alignment pattern 51 and the dummy bump 1 are compared.
If there is no gap between the dummy bump 16 and the hollow bump 51, the bonding operation is terminated, as shown in FIG.
1, when the gap of D2 is detected, or as shown in FIG.
In the case where a misalignment or a misalignment has occurred such as when the inclination α between the hollow portion 51a and the dummy bump 16 is detected as in the misalignment shown in FIG. After that, the position of the heating / pressing tool 20 or the stage 21 is automatically set for the next connection step, and the bonding operation is completed.

【0027】尚位置ずれ及び軸ずれの検知は、下部カメ
ラ光学系24にて位置合わせパターン51上の2点以上
の位置を検知して位置合わせパターン51の座標値を算
出する一方、ダミーバンプ16においても上記2点以上
の位置と対応する位置を検知してダミ−バンプの座標値
を算出して、それぞれの座標値から、ずれ量(x、y、
θ)を算出する。
The position deviation and the axis deviation are detected by detecting the positions of two or more points on the alignment pattern 51 by the lower camera optical system 24 and calculating the coordinate values of the alignment pattern 51, while detecting the position of the dummy bump 16. Also, the positions corresponding to the positions of the two or more points are detected, the coordinate values of the dummy bumps are calculated, and the deviation amounts (x, y,
θ) is calculated.

【0028】この様に構成すれば、位置合わせパターン
51とダミーバンプ16とを透明な本体基板下方から検
知してずれ量を認識する事により、COGによるバンプ
13と配線端子14とのずれを検知し、この検知結果か
らCOGボンダ18の位置ずれのオフセット設定を自動
的に行う事により、液晶ドライバチップ12を位置ずれ
を生じること無く良好に接続出来、実装時の信頼性が向
上される。
With this configuration, the displacement between the bump 13 and the wiring terminal 14 due to COG is detected by detecting the displacement amount by detecting the alignment pattern 51 and the dummy bump 16 from below the transparent main body substrate. By automatically setting the offset of the displacement of the COG bonder 18 based on the detection result, the liquid crystal driver chip 12 can be connected well without causing the displacement, and the reliability at the time of mounting is improved.

【0029】次に本発明の第5の実施の形態を図13を
参照して説明する。尚この第5の実施の形態は、第4の
実施の形態において、下部カメラ光学系24にて本体基
板とダミーバンプとの当接状態を検知する前は、異方導
電性膜を硬化する事無く、バンプ及び配線端子を単に当
接した状態のまま、下部カメラ光学系24にてダミーバ
ンプ位置を検知し、検知結果に応じて位置ずれや軸ずれ
を生じていた場合は、異方性導電膜を硬化する事なく液
晶ドライバチップ12を除去するものであり、他は第4
の実施の形態と同一である事から、同一部分については
同一符号を付しその説明を省略する。
Next, a fifth embodiment of the present invention will be described with reference to FIG. In the fifth embodiment, before the lower camera optical system 24 detects the contact state between the main substrate and the dummy bumps in the fourth embodiment, the anisotropic conductive film is not cured. When the position of the dummy bump is detected by the lower camera optical system 24 while the bump and the wiring terminal are kept in contact with each other, and if the position shift or the axis shift occurs according to the detection result, the anisotropic conductive film is removed. The liquid crystal driver chip 12 is removed without being cured.
Since the present embodiment is the same as the above-described embodiment, the same portions are denoted by the same reference numerals and description thereof will be omitted.

【0030】即ちCOGボンダ18により本体基板(図
示せず)に液晶ドライバチップ12を接続する工程は、
ステップ27からステップ30迄は第1の実施の形態の
図6にて説明したフローチャートと同様であるものの、
その後は、図13のフローチャートに示す様に、ステッ
プ57にて加熱加圧ツール20を降下し配線端子14に
バンプ13を当接加圧してステップ58に進む。このと
きダミーバンプ16は、位置合わせパターン51位置に
て本体基板10上に当接される、そして、ステップ58
にて、下部カメラ光学系24により本体基板10裏側か
ら、位置合わせパターン51とダミーバンプ16との位
置ずれを検出し、ステップ60にて位置ずれを生じてい
るか否かを比較し、位置合わせパターン51の中空部5
1aとダミーバンプ16とが隙間なく嵌まり合い、位置
ずれが無い場合は、ステップ61に進む一方、中空部5
1aとダミーバンプ16との間に隙間や傾きを検知し、
位置ずれ或いは軸ずれを生じている場合は、ステップ6
2に進む。
That is, the step of connecting the liquid crystal driver chip 12 to the main body substrate (not shown) by the COG bonder 18 includes:
Steps 27 to 30 are the same as the flowchart described in FIG. 6 of the first embodiment,
Thereafter, as shown in the flowchart of FIG. 13, the heating / pressing tool 20 is lowered in step 57 to abut and press the bump 13 against the wiring terminal 14, and the process proceeds to step 58. At this time, the dummy bump 16 is brought into contact with the main body substrate 10 at the position of the alignment pattern 51, and
At step 60, the lower camera optical system 24 detects the misalignment between the alignment pattern 51 and the dummy bumps 16 from the back side of the main body substrate 10 and compares whether or not the misalignment has occurred at step 60. Hollow part 5
If the dummy bump 1a and the dummy bump 16 are fitted without any gap and there is no displacement, the process proceeds to step 61, while the hollow portion 5
1a and the gap between the dummy bump 16 and the inclination are detected,
If a position shift or axis shift has occurred, step 6
Proceed to 2.

【0031】ステップ61では加熱加圧ツール20にて
加熱加圧して異方性導電膜を熱硬化し配線端子14及び
バンプ13のボンディングを終了する。一方ステップ6
2では、位置ずれ量或いは軸ずれ量を算出してオフセッ
ト量に変換し、次の接続工程のため加熱加圧ツール20
或いはステージ21の位置状態のオフセット設定を自動
的に行った後、ステップ63にて本体基板10から液晶
ドライブチップ12を除去し、操作を終了する。尚この
時点では異方性導電膜は硬化されておらず、液晶ドライ
バチップ12は容易に除去可能と成る。
In step 61, the anisotropic conductive film is thermally cured by heating and pressing with the heating and pressing tool 20, and the bonding of the wiring terminals 14 and the bumps 13 is completed. Step 6
In step 2, the amount of positional deviation or the amount of axial deviation is calculated and converted into an offset amount.
Alternatively, after the offset of the position of the stage 21 is automatically set, the liquid crystal drive chip 12 is removed from the main body substrate 10 in step 63, and the operation is terminated. At this point, the anisotropic conductive film is not cured, and the liquid crystal driver chip 12 can be easily removed.

【0032】この様に構成すれば、合わせずれを生じて
いた場合は、液晶ドライブチップ12はボンディングさ
れる事無く直ちに除去されるので、不良品の製造を未然
に防止出来、実装時の信頼性をより向上出来る。
With such a configuration, if misalignment has occurred, the liquid crystal drive chip 12 is immediately removed without being bonded, so that the production of defective products can be prevented beforehand, and the reliability during mounting can be reduced. Can be further improved.

【0033】尚本発明は上記実施の形態に限られるもの
でなく、その趣旨を変えない範囲での変更は可能であっ
て、例えば突起電極と配線端子の接合剤は、透明であれ
ば任意であり、光硬化性樹脂を用いる等しても良い。
又、突起の大きさも限定されないが、半導体装置に形成
される各種突起電極のうち登頂面積が最小の突起電極以
下の大きさにすれば、全ての突起電極における導通の良
否の判別をカバー出来る。更に突起電極と配線端子との
接続工程も任意であり、検知手段による突起当接面の検
知工程前は異方性導電膜等を硬化する事なく、良好な当
接を検知した場合は異方性導電膜を硬化して接続を行う
ものの、第5の実施の形態で述べた様に、位置ずれや軸
ずれを検知した場合は、異方性導電膜を硬化せずに半導
体装置を除去するのと同様に、導通不良や半導体装置の
傾斜を検知した場合等にも、突起電極と配線端子とを接
続する事無く直ちに半導体装置を除去する様にしても良
い。
The present invention is not limited to the above-described embodiment, but can be changed without departing from the spirit of the invention. For example, the bonding agent between the protruding electrode and the wiring terminal may be any one as long as it is transparent. Yes, a photo-curable resin may be used.
Also, the size of the projection is not limited, but if the peak area of the various projection electrodes formed in the semiconductor device is smaller than the minimum projection electrode, it is possible to cover the determination of the good or bad conduction of all the projection electrodes. In addition, the process of connecting the protruding electrode and the wiring terminal is optional, and before the process of detecting the protruding abutting surface by the detecting means, the anisotropic conductive film is not cured, and if a good abutment is detected, it is anisotropic. Although the connection is made by curing the conductive film, as described in the fifth embodiment, when the positional deviation or the axis deviation is detected, the semiconductor device is removed without curing the anisotropic conductive film. Similarly to the above, the semiconductor device may be removed immediately without connecting the protruding electrode and the wiring terminal even when a conduction failure or a tilt of the semiconductor device is detected.

【0034】[0034]

【発明の効果】以上説明したように本発明によれば、C
OGのフェースダウン方式において、突起の本体基板と
の当接面を本体基板裏面より検知する事により、本体基
板上に形成される配線端子が不透明な材質であっても、
配線端子に対する電極基板の当接状態を判別可能と成
る。したがってプロービング等による導通検査を行う以
前にその導通の良否検査が可能になり、更には検知され
た電極基板のずれや、半導体装置の傾きに応じて直ちに
半導体装置の接続条件を調整し、あるいは当接不良の半
導体装置を除去出来る事から、半導体装置の基板への接
続精度の向上を図れ、接続時の歩留まりを向上出来る。
As described above, according to the present invention, C
In the face down method of the OG, by detecting the contact surface of the protrusion with the main body substrate from the back surface of the main body substrate, even if the wiring terminal formed on the main body substrate is made of an opaque material,
The contact state of the electrode substrate with respect to the wiring terminal can be determined. Therefore, it is possible to inspect the continuity of the continuity before conducting the continuity inspection by probing or the like, and further adjust the connection condition of the semiconductor device immediately according to the detected displacement of the electrode substrate or the inclination of the semiconductor device, or Since the semiconductor device having poor connection can be removed, the connection accuracy of the semiconductor device to the substrate can be improved, and the yield at the time of connection can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施の形態の本体基板を示す一
部省略斜視図である。
FIG. 1 is a partially omitted perspective view showing a main body substrate according to a first embodiment of the present invention.

【図2】本発明の第1の実施の形態の液晶ドライバチッ
プを電極基板側から見た斜視図である。
FIG. 2 is a perspective view of the liquid crystal driver chip according to the first embodiment of the present invention as viewed from an electrode substrate side.

【図3】本発明の第1の実施の形態のCOGボンダを示
す概略構成図である。
FIG. 3 is a schematic configuration diagram illustrating a COG bonder according to the first embodiment of the present invention.

【図4】本発明の第1の実施の形態の液晶ドライバチッ
プの本体基板への実装状態を示す概略説明図である。
FIG. 4 is a schematic explanatory view showing a state in which the liquid crystal driver chip according to the first embodiment of the present invention is mounted on a main body substrate.

【図5】本発明の第1の実施の形態のダミーバンプを本
体基板裏面から検知した一部平面図である。
FIG. 5 is a partial plan view of the dummy bumps according to the first embodiment of the present invention, which is detected from the back surface of the main body substrate.

【図6】本発明の第1の実施の形態の液晶ドライバチッ
プの接続工程を示すフローチャートである。
FIG. 6 is a flowchart showing a connection process of the liquid crystal driver chip according to the first embodiment of the present invention.

【図7】本発明の第2の実施の形態の液晶ドライバチッ
プを電極端子側から見た平面図である。
FIG. 7 is a plan view of a liquid crystal driver chip according to a second embodiment of the present invention as viewed from an electrode terminal side.

【図8】本発明の第3の実施の形態の液晶ドライバチッ
プを電極端子側から見た平面図である。
FIG. 8 is a plan view of a liquid crystal driver chip according to a third embodiment of the present invention as viewed from an electrode terminal side.

【図9】本発明の第3の実施の形態の液晶ドライバチッ
プの接続工程を示すフローチャートである。
FIG. 9 is a flowchart illustrating a connection process of a liquid crystal driver chip according to a third embodiment of the present invention.

【図10】本発明の第4の実施の形態のダミーバンプを
本体基板裏側から検知した一部平面図である。
FIG. 10 is a partial plan view illustrating a dummy bump according to a fourth embodiment of the present invention, which is detected from the back side of a main body substrate.

【図11】本発明の第4の実施の形態のダミーバンプと
位置合わせバターンとのずれを示し(イ)はその位置ず
れを示す概略説明図、(ロ)はその軸ずれを示す概略説
明図である。
FIGS. 11A and 11B are schematic explanatory views showing a displacement between a dummy bump and an alignment pattern according to a fourth embodiment of the present invention, wherein FIG. 11A is a schematic explanatory view showing the positional displacement, and FIG. is there.

【図12】本発明の第4の実施の形態の液晶ドライバチ
ップの接続工程を示すフローチャートである。
FIG. 12 is a flowchart illustrating a connection process of a liquid crystal driver chip according to a fourth embodiment of the present invention.

【図13】本発明の第5の実施の形態の液晶ドライバチ
ップの接続工程を示すフローチャートである。
FIG. 13 is a flowchart illustrating a connection process of a liquid crystal driver chip according to a fifth embodiment of the present invention.

【符号の説明】[Explanation of symbols]

10…本体基板 11…液晶表示素子 12…液晶ドライバチップ 13…バンプ 14…配線端子 16…ダミーバンプ 17…金属粒子 18…COGボンダ 20…加熱加圧ツール 21…ステージ 22…位置合わせカメラ光学系 24…下部カメラ光学系 DESCRIPTION OF SYMBOLS 10 ... Main body board 11 ... Liquid crystal display element 12 ... Liquid crystal driver chip 13 ... Bump 14 ... Wiring terminal 16 ... Dummy bump 17 ... Metal particle 18 ... COG bonder 20 ... Heating and pressing tool 21 ... Stage 22 ... Positioning camera optical system 24 ... Lower camera optics

Claims (16)

【特許請求の範囲】[Claims] 【請求項1】 電子装置の配線端子を有する本体基板
と、前記配線端子に対向して当接し前記電子装置と導通
する突起電極を有する半導体装置とを具備する半導体装
置の実装体において、 前記半導体装置が、前記突起電極と同一材質からなり前
記突起電極の前記接続端子への当接時に前記本体基板に
当接し前記電子装置と非導通の突起を有し、 前記本体基板が前記突起との当接面を反対の面から検知
可能な材質からなる事を特徴とする半導体装置の実装
体。
1. A semiconductor device package comprising: a main body substrate having a wiring terminal of an electronic device; and a semiconductor device having a protruding electrode which is opposed to the wiring terminal and is in conduction with the electronic device. The device has a protrusion made of the same material as the protruding electrode and being in contact with the main body substrate when the protruding electrode is in contact with the connection terminal and being non-conductive with the electronic device. A semiconductor device package comprising a material whose contact surface can be detected from an opposite surface.
【請求項2】 電子装置の配線端子を有する透明な本体
基板と、前記配線端子に対向して当接し前記電子装置と
導通する突起電極を有する半導体装置とを具備する半導
体装置の実装体において、 前記半導体装置が、前記突起電極と同一材質からなり前
記突起電極の前記配線端子への当接時に前記本体基板に
当接し前記電子装置と非導通の突起を有し、 前記本体基板が前記突起との当接面に遮光体を有しない
事を特徴とする半導体装置の実装体。
2. A semiconductor device package comprising: a transparent main body substrate having a wiring terminal of an electronic device; and a semiconductor device having a protruding electrode which is opposed to the wiring terminal and is electrically connected to the electronic device. The semiconductor device has a protrusion which is made of the same material as the protruding electrode and which is in contact with the main body substrate when the protruding electrode is in contact with the wiring terminal, and which is not electrically connected to the electronic device. Wherein the light-shielding body is not provided on the contact surface of the semiconductor device.
【請求項3】 突起の登頂部の面積が、最小の突起電極
の登頂部の面積以下の面積である事を特徴とする請求項
1又は請求項2のいずれかに記載の半導体装置の実装
体。
3. The semiconductor device package according to claim 1, wherein the area of the top of the protrusion is smaller than the area of the top of the smallest protrusion electrode. .
【請求項4】 電子装置の配線端子を有する本体基板
と、前記配線端子に対向して当接し前記電子装置と導通
する突起電極を有する半導体装置とを具備する半導体装
置の実装方法において、 前記半導体装置に更に前記突起電極と同一材質からなり
前記突起電極の前記配線端子への当接時に前記本体基板
に当接し前記電子装置と非導通の突起を設け、この突起
を前記本体基板にフェースダウンにて当接する工程と、 前記本体基板に当接された前記突起を前記当接面と反対
の面から検知する工程とを具備する事を特徴とする半導
体装置の実装方法。
4. A method of mounting a semiconductor device, comprising: a main body substrate having wiring terminals of an electronic device; and a semiconductor device having a protruding electrode which is opposed to the wiring terminals and is electrically connected to the electronic device. The device is further provided with a projection which is made of the same material as the protruding electrode and which is in contact with the main body substrate when the protruding electrode abuts on the wiring terminal and is non-conductive with the electronic device. And a step of detecting the protrusion contacted with the main body substrate from a surface opposite to the contact surface.
【請求項5】 突起電極を配線端子に当接後であって接
着前に、突起の当接面を検知する事を特徴とする請求項
4に記載の半導体装置の実装方法。
5. The method according to claim 4, wherein a contact surface of the projection is detected after the projection electrode is in contact with the wiring terminal and before bonding.
【請求項6】 電子装置の配線端子を有する透明な本体
基板と、前記配線端子に対向して当接し前記電子装置と
導通する突起電極を有する半導体装置とを具備する半導
体装置の実装方法において、 前記半導体装置に更に前記突起電極と同一材質からなり
前記突起電極の前記配線端子への当接時に前記本体基板
に当接し前記電子装置と非導通の突起を設け、導電性材
料を含有する透明接着剤を介し前記突起を前記本体基板
にフェースダウンにて当接する工程と、 前記本体基板及び前記突起間に介在される前記導電性材
料の量を前記本体基板の当接面と反対の面から検知し、
前記突起電極の前記電子装置との導通状態を検知する工
程とを具備する事を特徴とする半導体装置の実装方法。
6. A method of mounting a semiconductor device, comprising: a transparent main body substrate having wiring terminals of an electronic device; and a semiconductor device having a protruding electrode which is in contact with the wiring terminals and is electrically connected to the electronic device. The semiconductor device is further provided with a projection which is made of the same material as the protruding electrode and which is in contact with the main substrate when the protruding electrode abuts on the wiring terminal and which is non-conductive with the electronic device, and which includes a transparent material containing a conductive material. Contacting the protrusion with the body substrate face down via an agent, and detecting an amount of the conductive material interposed between the body substrate and the protrusion from a surface opposite to a contact surface of the body substrate. And
Detecting a conductive state of the bump electrode with the electronic device.
【請求項7】 電子装置の配線端子を有する透明な本体
基板と、前記配線端子に対向して当接し前記電子装置と
導通する突起電極を有する半導体装置とを具備する半導
体装置の実装方法において、 前記半導体装置に更に前記突起電極と同一材質からなり
前記突起電極の前記配線端子への当接時に前記本体基板
に当接し前記電子装置と非導通の突起を設け、導電性材
料を含有する透明接着剤を介し前記突起を前記本体基板
にフェースダウンにて当接する工程と、 前記本体基板及び前記突起間に介在される前記導電性材
料の量を前記本体基板の当接面と反対の面から検知し、
前記突起電極の前記電子装置との導通状態を検知する工
程と、 前記検知工程にて前記突起電極及び前記電子装置間の導
通不良が検知された場合は、前記フェースダウン工程に
よる当接位置を調整する工程とを具備する事を特徴とす
る半導体装置の実装方法。
7. A method of mounting a semiconductor device, comprising: a transparent main body substrate having wiring terminals of an electronic device; and a semiconductor device having a protruding electrode which is in contact with the wiring terminals and is electrically connected to the electronic device. The semiconductor device is further provided with a projection which is made of the same material as the protruding electrode and which is in contact with the main substrate when the protruding electrode abuts on the wiring terminal and which is non-conductive with the electronic device, and which includes a transparent material containing a conductive material. Contacting the protrusion with the body substrate face down via an agent, and detecting an amount of the conductive material interposed between the body substrate and the protrusion from a surface opposite to a contact surface of the body substrate. And
Detecting a conduction state of the protruding electrode with the electronic device; and adjusting a contact position by the face-down process if a conduction failure between the protruding electrode and the electronic device is detected in the detecting step. A method of mounting a semiconductor device.
【請求項8】 突起電極を配線端子に当接後であって接
着前に、前記突起電極の導通状態を検知し導通不良が検
知された場合は半導体装置を除去する事を特徴とする請
求項6又は請求項7のいずれかに記載の半導体装置の実
装方法。
8. The semiconductor device according to claim 1, wherein after the protruding electrode is brought into contact with the wiring terminal and before the bonding, the conductive state of the protruding electrode is detected, and if a conduction failure is detected, the semiconductor device is removed. A method for mounting the semiconductor device according to claim 6.
【請求項9】 電子装置の配線端子を有する透明な本体
基板と、前記配線端子に対向して当接し前記電子装置と
導通する突起電極を有する半導体装置とを具備する半導
体装置の実装方法において、 前記半導体装置に更に前記突起電極と同一材質からなり
前記突起電極の前記配線端子への当接時に前記本体基板
に当接し前記電子装置と非導通の複数の突起を設け、前
記本体基板にフェースダウンにて当接する工程と、 前記本体基板に対する前記複数の突起の当接による圧着
状態を前記本体基板の当接面と反対の面から検知し、前
記半導体装置の前記本体基板に対する傾きを検知する工
程とを具備する事を特徴とする半導体装置の実装方法。
9. A method for mounting a semiconductor device, comprising: a transparent main body substrate having wiring terminals of an electronic device; and a semiconductor device having a protruding electrode which is in contact with the wiring terminals and is electrically connected to the electronic device. The semiconductor device is further provided with a plurality of protrusions made of the same material as the protruding electrodes and abutting on the main body substrate when the protruding electrodes are in contact with the wiring terminals and being non-conductive with the electronic device, and face-down on the main body substrate. And a step of detecting a pressing state of the plurality of protrusions against the main body substrate from a surface opposite to a contact surface of the main body substrate, and detecting an inclination of the semiconductor device with respect to the main body substrate. A method of mounting a semiconductor device, comprising:
【請求項10】 電子装置の配線端子を有する透明な本
体基板と、前記配線端子に対向して当接し前記電子装置
と導通する突起電極を有する半導体装置とを具備する半
導体装置の実装方法において、 前記半導体装置に更に前記突起電極と同一材質からなり
前記突起電極の前記配線端子への当接時に前記本体基板
に当接し前記電子装置と非導通の複数の突起を設け、前
記本体基板にフェースダウンにて当接する工程と、 前記本体基板に対する前記複数の突起の当接による圧着
状態を前記本体基板の当接面と反対の面から検知し、前
記半導体装置の前記本体基板に対する傾きを検知する工
程と、 前記検知工程にて前記半導体装置の傾きが検知された場
合は、傾き量を算出し前記フェースダウン工程による当
接時の傾きを前記傾き量に応じて調整する工程とを具備
する事を特徴とする半導体装置の実装方法。
10. A method for mounting a semiconductor device, comprising: a transparent main body substrate having wiring terminals of an electronic device; and a semiconductor device having a protruding electrode which is in contact with the wiring terminals and is electrically connected to the electronic device. The semiconductor device is further provided with a plurality of protrusions made of the same material as the protruding electrodes and abutting on the main body substrate when the protruding electrodes are in contact with the wiring terminals and being non-conductive with the electronic device, and face-down on the main body substrate. And a step of detecting a pressing state of the plurality of protrusions against the main body substrate from a surface opposite to a contact surface of the main body substrate, and detecting an inclination of the semiconductor device with respect to the main body substrate. When the inclination of the semiconductor device is detected in the detection step, the inclination amount is calculated, and the inclination at the time of contact in the face-down step is adjusted according to the inclination amount. And a mounting method for a semiconductor device.
【請求項11】 半導体装置を導電性材料を含有する透
明接着剤を介して本体基板に当接し、複数の突起の当接
面における前記導電性材料のつぶれ具合を検知して圧着
状態を検知する事を特徴とする請求項9又は請求項10
のいずれかに記載の半導体装置の実装方法。
11. A semiconductor device is brought into contact with a main body substrate via a transparent adhesive containing a conductive material, and a state of pressure contact is detected by detecting a degree of crushing of the conductive material on a contact surface of a plurality of projections. Claim 9 or Claim 10
The method for mounting a semiconductor device according to any one of the above.
【請求項12】 突起電極を配線端子に当接後であって
接着前に、前記突起電極の圧着状態を検知し半導体装置
の傾きを検知した場合は、前記半導体装置を除去する事
を特徴とする請求項9乃至請求項11のいずれかに記載
の半導体装置の実装方法。
12. The semiconductor device according to claim 1, wherein the semiconductor device is removed when the pressure contact state of the projection electrode is detected and the inclination of the semiconductor device is detected after the projection electrode is brought into contact with the wiring terminal and before bonding. The method of mounting a semiconductor device according to claim 9.
【請求項13】 電子装置の配線端子を有する透明な本
体基板と、前記配線端子に対向して当接し前記電子装置
と導通する突起電極を有する半導体装置とを具備する半
導体装置の実装方法において、 前記半導体装置に更に前記突起電極と同一材質からなり
前記突起電極の前記配線端子との当接時に前記本体基板
に当接し前記電子装置と非導通の突起を設け、前記本体
基板にフェースダウンにて当接する工程と、 前記本体基板に対する前記突起の当接ずれを前記本体基
板の当接面と反対の面から検知し、前記突起電極及び前
記配線端子間の当接ずれを検知する工程とを具備する事
を特徴とする半導体装置の実装方法。
13. A method for mounting a semiconductor device, comprising: a transparent main body substrate having wiring terminals of an electronic device; and a semiconductor device having a protruding electrode which is in contact with the wiring terminals and is electrically connected to the electronic device. The semiconductor device is further provided with a projection which is made of the same material as that of the protruding electrode and which is in contact with the main body substrate when the protruding electrode comes into contact with the wiring terminal and which is not electrically connected to the electronic device, and the main body substrate is face down. Contacting, and detecting a contact deviation of the protrusion with respect to the main substrate from a surface opposite to a contact surface of the main substrate, and detecting a contact deviation between the projecting electrode and the wiring terminal. A method of mounting a semiconductor device.
【請求項14】 電子装置の配線端子を有する透明な本
体基板と、前記配線端子に対向して当接し前記電子装置
と導通する突起電極を有する半導体装置とを具備する半
導体装置の実装方法において、 前記半導体装置に更に前記突起電極と同一材質からなり
前記突起電極の前記配線端子との当接時に前記本体基板
に当接し前記電子装置と非導通の突起を設け、前記本体
基板にフェースダウンにて当接する工程と、 前記本体基板に対する前記突起の当接ずれを前記本体基
板の当接面と反対の面から検知し、前記突起電極及び前
記配線端子間の当接ずれを検知する工程と、 前記検知工程にて前記突起電極及び前記配線端子間の当
接ずれが検知された場合は、当接ずれ量を算出し前記フ
ェースダウン工程による当接位置を前記当接ずれ量に応
じて調整する工程とを具備する事を特徴とする半導体装
置の実装方法。
14. A method for mounting a semiconductor device, comprising: a transparent main body substrate having wiring terminals of an electronic device; and a semiconductor device having a protruding electrode which is in contact with the wiring terminals and is electrically connected to the electronic device. The semiconductor device is further provided with a projection which is made of the same material as that of the protruding electrode and which is in contact with the main body substrate when the protruding electrode comes into contact with the wiring terminal and which is not electrically connected to the electronic device, and the main body substrate is face-down. Contacting, detecting a contact deviation of the projection with respect to the main substrate from a surface opposite to a contact surface of the main substrate, and detecting a contact deviation between the projecting electrode and the wiring terminal; If a contact displacement between the protruding electrode and the wiring terminal is detected in the detecting step, the contact displacement is calculated and the contact position in the face-down step is adjusted according to the contact displacement. A method of mounting a semiconductor device.
【請求項15】 突起電極を配線端子に当接後であって
接着前に、前記突起電極の当接ずれを検知した場合は、
半導体装置を除去する事を特徴とする請求項13又は請
求項14のいずれかに記載の半導体装置の実装方法。
15. When a contact shift of the projecting electrode is detected after the projecting electrode has been brought into contact with the wiring terminal and before bonding,
The method for mounting a semiconductor device according to claim 13, wherein the semiconductor device is removed.
【請求項16】 本体基板が、突起との当接位置に前記
突起先端と嵌合する中空のパターンを有し、 前記突起先端と前記中空のパターンとの嵌合ずれを検知
する事により前記突起の当接ずれを検知する事を特徴と
する請求項13乃至請求項15のいずれかに記載の半導
体装置の実装方法。
16. The main body substrate has a hollow pattern fitted to the tip of the projection at a contact position with the projection, and detecting the misalignment between the tip of the projection and the hollow pattern to detect the projection. The mounting method of a semiconductor device according to claim 13, wherein a contact shift of the semiconductor device is detected.
JP15195296A 1996-06-13 1996-06-13 Mounting method of semiconductor device Expired - Fee Related JP3657696B2 (en)

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Application Number Priority Date Filing Date Title
JP15195296A JP3657696B2 (en) 1996-06-13 1996-06-13 Mounting method of semiconductor device

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JP2000031202A true JP2000031202A (en) 2000-01-28
JP3657696B2 JP3657696B2 (en) 2005-06-08

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1477841A1 (en) * 2002-06-06 2004-11-17 Alps Electric Co., Ltd. Liquid crystal display device and manufacturing method thereof
KR100504220B1 (en) * 1997-10-22 2005-11-16 나녹스 가부시키가이샤 Chip On Glass Liquid Crystal Display
JP2009150835A (en) * 2007-12-21 2009-07-09 Omron Corp Optical inspection method and optical inspection device
WO2019188116A1 (en) * 2018-03-30 2019-10-03 株式会社ジャパンディスプレイ Organic el display device and method for producing organic el display device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100504220B1 (en) * 1997-10-22 2005-11-16 나녹스 가부시키가이샤 Chip On Glass Liquid Crystal Display
EP1477841A1 (en) * 2002-06-06 2004-11-17 Alps Electric Co., Ltd. Liquid crystal display device and manufacturing method thereof
JP2009150835A (en) * 2007-12-21 2009-07-09 Omron Corp Optical inspection method and optical inspection device
WO2019188116A1 (en) * 2018-03-30 2019-10-03 株式会社ジャパンディスプレイ Organic el display device and method for producing organic el display device

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