JP2000030362A - Computer architecture capable of actuating circuit and program of related mass storage, that is, mass storage peripheral device arranged away from the device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make actuatable the circuit and program of a mass storage peripheral device arranged away from the device by providing an interface between the mass storage peripheral device and a host computer and a control circuit for receiving information detected with a medium used in the computer. SOLUTION: The signal detected by a sensor 15 is transmitted to a pre-amplifier 20 through a flexible cable 17, and the sensor 15 is positioned to a selectable place on a data medium 14 by a positioning mechanism 22. The output of the pre-amplifier 20 is transmitted to a read/write-in channel circuit 24, and a read/ write-in channel applies various functions such as filter action and analog/digital conversion, automatic gain control pulse detection, encoding/decoding in respective read/write-in path to the amplified analog data read by the sensor 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvements in computer architecture and, more particularly, in computer architectures capable of operating circuitry and programs of mass storage peripheral devices located remotely from the device. Related to improvements.

[0002]

BACKGROUND OF THE INVENTION Mass storage peripherals have played a major role in the development of modern computers. Typical mass storage peripherals include hard and floppy disk drives.
Drive, CD-ROM drive, DVD device and the like. A typical mass storage peripheral device that can be associated with a computer is a variety of electronic devices for operating the device, configured such that the device can be used as versatile as possible with various processors or computer types. Have a circuit. Typically, for example, mass storage peripherals are configured together with a rotating data medium on which at least data can be read and in which data can be written. I have. Such devices typically include a motor that rotates the medium, and one or more head devices that can read data from the medium and move to selectable locations on the medium to store the data. Including. In order to control the rotation of the motor and the selective positioning of the head, the printed wiring board is often provided with an associated electronic circuit as an assembly with the rotating medium.

The particular electronics that can be provided on any particular mass storage device can vary depending on the type and type of peripheral in question. For example, a typical electronic circuit for a hard disk drive (HDD) assembly is a servo or motor control circuit that rotates a motor, a data
It includes a voice coil control circuit for positioning the head, a data preamplifier circuit for amplifying a signal read by the head from the rotating medium, a read channel processing circuit for initial processing of the read data, and a control circuit. The control circuit includes buffers for speed adjustment and signal timing.
It may include memory elements, signal interface circuits for interfacing data and other signals with computer buses and control circuits, error correction and control circuits, and the like. Such circuits are typically mounted as a number of integrated circuit devices, possibly as many as nine separate integrated circuit chips, on a printed wiring board associated with a particular peripheral device. The electronic circuit of the hard disk drive
Typically, one or more buses provide the host
Connected to the corresponding bus on the "motherboard" of the computer. The motherboard may have its own supporting circuits for the peripheral device, such as line drive circuits and data processing circuits for delivering and controlling various signals to or from the peripheral device. Each particular mass storage device may have its own particular hardware and software characteristics, and since such characteristics may be unique to such devices, they are typically May have to have their own customized firmware to properly initialize the associated computer so that the device can be addressed and access its data. Among other things, such firmware transfers addresses from the translator to the cylinders, heads, sectors,
It may also include information on how to translate to a particular arrangement of mass storage devices such as zones. Such peripherals are typically supplied with custom firmware and loaded when the associated computer is initialized into system RAM. In most cases, software drivers may also be required.
This software driver can be provided by a generic driver, often supplied with computer operating system software, and in other cases, especially when certain peripherals are special or common. May be provided separately by the manufacturer of a particular peripheral device if it has different characteristics. Therefore, changes that can be used for any peripheral device, especially hardware changes, must be compatible with existing computer hardware architecture and design, and are therefore limited. Will be understood.

As data access speeds increase, hardware and software approaches are being developed to increase the speed of data transfer with such mass storage devices. One such prevailing approach is to provide a peripheral component interconnect (PCI) bus. The PCI bus is designed to be independent of both the processor and the computer system architecture, in addition to increasing the speed of access to the data of the peripherals, regardless of the CPU or host system computer architecture used. , PCI electrical requirements, protocols and hardware interface requirements remain the same. This allows the same peripheral computer device to be connected to a variety of different host systems without requiring a different version of the device for any type of host system that is to be used with the device. The PCI bus architecture allows relocatable extended ROM location addresses to be used with associated peripherals. For details of the PCI bus characteristics associated with mass storage peripherals, see PCT Application No. WO 97/1850, assigned to the assignee of this application.
5. See Title of Invention, "Method and Apparatus for Operating Mass Memory Peripheral Computer Device Connected to Host Computer". This application is cited here. In addition, the mass memory storage peripheral may include customized extended BIOS data that is loaded into the system RAM during the relevant computer initialization. Details of specific BIOS schemes can be found in PCT Application No. WO 97/1409, assigned to the assignee of this application.
5. It is described in the title of the invention "System for providing BIOS in host computer", and this application is cited here. One goal of mass storage peripheral device manufacturers is:
The goal is to reduce the cost of the equipment as much as possible. For this purpose, the integration level of the electronic circuit is increased, and the cost of the integrated circuit for a predetermined function is reduced due to the reduction in the shape of the semiconductor. However, these reductions were not primarily at the system level. It will be appreciated that using this scheme, the required electronics and hardware requirements will be similar to the PCI bus.

[0005]

SUMMARY OF THE INVENTION Accordingly, in view of the foregoing, it is an object of the present invention to operate a circuit and program for a mass storage peripheral device associated with a computer which is located remotely from the device. Is to provide an improved computer architecture. It is another object of the present invention to provide an improved computer architecture of the type described, which is located away from mass storage peripherals, for example, located on a computer motherboard and associated mass storage A single integrated circuit is provided to control at least some functions of the peripheral device. It is another object of the present invention to provide an improved computer architecture of the type described, providing a single unit for controlling associated mass storage peripherals of the type designed for use with a PCI bus. Integrated circuit is provided. It is yet another object of the present invention to provide an improved computer architecture of the type described wherein a single PCI mass storage integrated circuit for controlling one or more associated mass storage peripherals Is provided. It is yet another object of the present invention to provide an improved computer architecture of the type described, thereby reducing the cost of peripheral equipment associated with that architecture, including the required device equipment, It can be lower than the cost of the equipment used. It is yet another object of the present invention to provide a computer architecture that relaxes computer design requirements to accommodate a wide variety of mass storage peripherals without requiring prior knowledge of the specific mass storage device specifications. It is to be. These and other objects, features and advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description of the invention when taken in conjunction with the accompanying drawings and the appended claims.

An association of the type having a computer readable medium, a sensor for detecting information on the medium, and a data amplifier for amplifying information detected on the medium to produce an amplified data signal. A computer architecture is provided for use with a host computer with a mass storage peripheral device. This computer
The architecture consists of mass storage peripherals and host
It includes an interface to a computer and control circuitry for at least one mass storage peripheral at a host computer for receiving information detected on a medium used by the computer. The control circuit preferably transmits information to a bus mastering bus of the host computer, for example, a PCI bus or a 1394 type bus. Mass storage peripherals
Drive assembly, hard disk drive assembly, CD-ROM disk drive assembly, DVD disk drive assembly, floppy disk drive assembly,
It may be a high capacity floppy disk drive assembly, a miniature storage device, or the like. Mass storage peripherals
It may have a motor for rotating the medium, the servo circuit may be located on the host computer and connected to an interface for operating the motor, and may be located on the mass storage peripheral. ,
Alternatively, they may be partially arranged in the host computer and partially arranged in the mass storage peripheral device. The mass storage peripheral device may further include a positioning mechanism for positioning the sensor, and the computer architecture includes circuitry located on the host computer and connected to the interface to operate the positioning mechanism. Is also good. The computer architecture may include a read channel circuit for receiving the amplified data signal. The read channel circuit may be partly included in the host computer, or in the mass storage peripheral, or in each case.

In accordance with another broad aspect of the invention, a computer readable medium, a sensor for detecting information on the medium, and an amplifier for amplifying information detected on the medium, respectively, to provide an amplified data signal A computer architecture is provided for use in a host computer with a plurality of associated mass storage peripherals of the type having a data amplifier for generating the same. The computer architecture includes an interface between the mass storage peripheral and the host computer, and at least one mass storage peripheral at the host computer for receiving information detected on the medium of the device for use in the computer. A control circuit. The control circuit may include a plurality of control circuits associated with each of the plurality of mass storage peripherals, or one control circuit may include a host computer bus mastering device.
It may be configured to transmit information to a bus. The computer architecture may further include a servo circuit located on the host computer and connected to an interface for operating the motor of the mass storage peripheral device. In accordance with yet another broad aspect of the invention, a rotatable, computer-readable data medium, a motor for rotating the medium, a sensor for detecting information on the medium, and amplifying information detected on the medium. A computer architecture is provided for use with an associated mass storage peripheral of the type having a data amplifier for performing the operations. The computer architecture has a circuit board that includes circuits for controlling the operation of the computer, and an interface between the mass storage peripheral device and the circuit board. A control circuit on the circuit board receives signals directly from the data amplifier for use in the computer and a servo circuit is provided for driving the motor.

[0008]

DETAILED DESCRIPTION OF THE INVENTION It is an object of the present invention to provide a mass storage peripheral and its associated host, as will be described in greater detail below.
This is achieved by the configuration and arrangement of computers. The term "host computer" is used for the central processing unit (CP).
U), memory, and a bus mastering bus, and are used to select any device that can operatively associate a mass storage device with it. The bus mastering bus is a bus that allows a device to issue a memory access request without requiring intervention or involvement of a CPU, and may be provided in a wiring board (circuit board). , "Mother board", or may be contained in an integrated circuit chip, for example, a CPU chip, or may be a cable or the like. An example of a suitable bus mastering bus is the well-known P
It is a CI bus or a 1394 bus. (PCI is an abbreviation for Peripheral Computer Interconnect. PCI is a high speed, wideband, 32/64 bit, 33/66 MHz processor independent expansion bus.) However, any suitable bus mastering bus Please be aware that you can use. Briefly, the present invention is realized by arranging many operating circuits, programs, and firmware conventionally provided on a wiring board of a peripheral device in a host computer. That is, for example, a control device for a mass storage peripheral device is located in a host computer, such as on a motherboard. Other circuits may also be located in the host computer, including a servo circuit that rotates the peripheral motor and a voice coil actuation circuit that locates the peripheral device's data sensor. As a result, the amount and expense of electronic circuits conventionally provided in peripheral devices are removed from the device and located at a location remote from the device. This has the effect of reducing the overall cost of the particular mass storage peripheral device to which the present invention pertains. This can also reduce the total number of components. A block diagram of the data processing path of a computer system 10 having a host computer 11 and a mass storage peripheral device 12 is shown in FIG. 1, showing the type and location of components according to a preferred embodiment of the present invention. A mass storage peripheral device comprises a data medium 14 and a medium 14
And at least a sensor 15 for reading data from the memory. As will be appreciated by those skilled in the art, the physical form of the data medium and sensors will depend on the particular form of the device in question. For example, the idea of the present invention is to use hard disk drives, floppy disk drives, high-density floppy
It is contemplated that it may be applicable to mass storage peripherals such as disk drives, CD-ROM drives, DVD drives, miniature drives, and other similar drives.

[0009] Typically, the signal detected by sensor 15 is passed through a “flex cable” 17 to a preamplifier 20. The preamplifier 20 may be configured on the flex cable 17 or may be separate therefrom. The sensor 15 is positioned by the positioning mechanism 22 in a known manner to a selectable location on the data medium 14. The output of the preamplifier is connected to a read / write channel circuit 24. As shown by the dashed line,
This circuit may be entirely within the mass storage peripheral device 12, may be entirely within the host computer 11, or may be partially within each,
This will be described in more detail later. The read / write channel provides filtering, analog-to-digital conversion in each read / write path, automatic gain control, pulse detection, and read / write functions for the amplified analog data read by head 15. It performs various functions such as encoding / decoding. The output on line 26 from the read / write channel is raw digital data, which is passed to a peripheral controller 28. In the read mode, the controller 28 receives the raw digital data on line 26 and formats it with a formatter or sequencer circuit 30. Thereafter, the formatted data is error-corrected by an error correction and control circuit (ECC) 32, and then is put into a second buffer 34 under the control of a buffer manager 33. ECC circuit 32
Is to use the error correction portion of the read data to ensure that the desired data is read correctly. In write mode, the effect is the same, but in reverse order. The ECC circuit 32 in the reverse path generates error correction data and attaches it to the data to be written to the medium 14. In the preferred embodiment of the present invention, the entire controller is provided in host computer 11, for example, in an integrated circuit on its motherboard. The controller 28 typically includes a bus control circuit 35, a servo logic circuit 37, a program ROM 39 and a processing engine 4 as shown in the figure.
Including 1. The output from controller 28 is the bus
It is connected to a mastering bus 36 from which data is written to or read from a memory, such as RAM 36, under the control of a memory manager 43. As previously mentioned, CPU 40 is incorporated as part of the host computer, but does not necessarily participate in controlling or directing data transfer to and from memory 38.

Most of the electronic circuitry required for the operation of the mass storage peripheral is preferably provided on the motherboard of the host computer, as shown in FIG. That is, the computer system 50 includes a wiring board 52 such as a motherboard of a host computer. Furthermore,
Preferably, the controller and other electronic circuits are contained in one integrated circuit 54, and the servo signal for rotating the peripheral device motor is in a second one integrated circuit 56. As shown, for example, three mass storage peripheral devices 5
8, 60, 62 are associated with the computer system 50. In the illustrated embodiment, mass storage peripheral 58 is a hard drive assembly (HDA). HDA is part of a typical hard disk drive (HDD). As can be seen, if the controls, servo circuits and other electronics are on the motherboard 52,
The components required for the drive are a data medium, a motor for rotating the medium, a sensor or head mechanism for reading or writing data on the medium, a preamplifier for amplifying data read from or written to the medium, and the like. Only the case that accommodates the parts. This minimal version of the HDD is referred to herein as the HDA. It will be readily appreciated that the cost of HDA is significantly less than the cost of a typical HDD of comparable capacity. In the illustrated embodiment, the mass storage peripheral device 60 may be a CD-ROM or a digital video device (DVD). Finally, in the illustrated embodiment, the mass storage peripheral device 62 includes a floppy drive, a mass floppy drive, a miniature
It may be a drive or other suitable device. Each peripheral device 58, 60, 62 may have an associated "personality ROM" 64, 66, 68, respectively. The personality ROM serves to maintain a physical data definition of the characteristics of the particular mass storage peripheral concerned. More specifically, the wiring board 52 of the host computer includes a PCI mass storage integrated circuit 54, a servo integrated circuit 56, a CPU 70 and its associated CPU chipset 72, and a RAM 73. One example chipset and CPU that can be used is Cyrix "MediaGX" product, whose "North Bridge" chipset is integrated with the host CPU,
Other system configurations can also be used. P shown
A bus mastering bus such as CI bus 74
The chipset 72 is interconnected with the PCI mass storage integrated circuit 54. Although PCI mass storage I / C 54 is shown as a separate chip, any particular computer
Note that it may be integrated with the chipset 74 provided in the system.

Turning now specifically to the PCI mass storage integrated circuit, in the illustrated embodiment, a single I / O containing the electronic circuitry necessary to support the three illustrated mass storage peripherals 58,60,62. / C. This circuit has 1
One or more digital signal processors (DP
S), including read channel, buffer manager, speed matching buffer, masked ROM, servo logic, formatting and error detection and correction (EDAC) circuitry. The particular circuits contained in the PCI mass storage I / C 54 are known, and the manner in which integrated circuits containing such circuits may be manufactured is known to those skilled in the art and will not be described further herein. As shown, the servo I / C 56
Preferably, it contains all the servo circuits necessary to rotate and control the motors of the associated mass storage peripherals 58, 60, 62. As shown, three separate servo circuits 74-76 may be integrated on a single chip. Instead, a single servo circuit may be used. It should be noted that the servo I / C is preferably located on the motherboard 52, and the servo circuits can be located at various locations. For example, a servo circuit can be located in each of the mass storage peripherals 58, 60, 62, but the cost and operational advantages are not fully realized. Alternatively, the servo circuits may be distributed, with some servo circuits located on the motherboard 52 and some located on the respective mass storage peripherals. One feature of the mass storage peripherals used in connection with the circuit arrangement shown in FIG. 2 is that a "personality ROM" 64, 66, 68 is provided for each of the mass storage peripherals 58, 60, 62. is there. As mentioned earlier, personality R
The OM has the information necessary to initialize and run the host computer correctly without the need for detailed driver software. The characteristic data items that can be included in the personality ROM of the mass storage peripheral are shown in the table below. The table is not exhaustive and other data items can be included as well. Furthermore, this data item is shown as an example and is not an absolute condition. Other configurations will be apparent to those skilled in the art.

[0012]

[Table 1]

[0013]

[Table 2]

[0014]

[Table 3]

[0015]

[Table 4]

[0016]

[Table 5]

[0017]

[Table 6]

A mass storage peripheral device 58 and a host computer motherboard 5 according to a preferred embodiment of the present invention.
A block diagram of a portion of a computer system showing an example of the interface 74 between the two is shown in FIG. That is, the servo I / C 56 is connected to the mass storage peripheral device 58.
Of the motor winding 76 for rotating and controlling the motor (not shown). The read (read) channel circuits 80, 80 ', 80''are shown in dashed lines to indicate where the circuits are possible, depending on the particular demands of the system and the mass storage peripheral. That is, the read channel circuit 80 may be entirely within the mass storage peripheral device 58 or may be entirely at the location 80 ′ within the PCI mass storage I / C 54. One part is in the mass storage device 58 and the other is in the mass storage device 5.
8 may be allocated. The read channel circuit is located on a separate chip or location 8 on the motherboard 52.
It may be provided on the integrated circuit at 0 ''. While the invention has been described in some detail and illustrated in the drawings, it is to be understood that this disclosure is merely exemplary and that those skilled in the art may, without departing from the scope of the invention set forth in the appended claims, It will be appreciated that various changes can be made to the combinations and arrangements of.

With respect to the above description, the following items are further disclosed. (1) An association of a type comprising a computer-readable medium, a sensor for detecting information on the medium, and a data amplifier for amplifying the information detected on the medium to generate an amplified data signal. A computer architecture for use in a host computer with a mass storage peripheral device, the interface between the mass storage peripheral device and the host computer, and for receiving the information detected on the medium used in the computer. Control circuitry for at least one of the mass storage peripherals at the host computer. (2) The computer architecture according to (1), wherein the control circuit transmits the information to a bus mastering bus of the host computer. (3) The computer architecture according to paragraph 2, wherein the bus mastering bus is a PCI bus. (4) The computer architecture of paragraph 2, wherein the bus mastering bus is a 1394 type bus. (5) The computer architecture according to paragraph 1, wherein the mass storage peripheral device is a disk drive assembly. (6) The computer architecture according to paragraph 1, wherein the mass storage peripheral device is a hard disk drive assembly. (7) The computer architecture according to paragraph 1, wherein the mass storage peripheral device is a CD-ROM disk drive assembly.
architecture. (8) The computer architecture according to paragraph 1, wherein the mass storage peripheral device is a DVD disk drive assembly. (9) The computer architecture according to (1), wherein the mass storage peripheral device is a floppy disk drive assembly.
architecture.

(10) The computer according to item 1
Architecture, where the mass storage peripherals are
A computer architecture that is a high-capacity floppy disk drive assembly. (11) The computer architecture according to paragraph 1, wherein the mass storage peripheral device is a small storage device. The computer architecture according to claim 1, wherein the mass storage peripheral device further comprises a motor for rotating the medium. (13) The computer architecture according to (12), wherein the servo circuit is disposed in the host computer and connected to the interface for operating the motor. The computer architecture of claim 12, wherein the servo circuit is located on the mass storage peripheral device and is connected to operate the motor. (15) The computer architecture according to (12), wherein the servo circuit is partially disposed on the host computer, partially disposed on the mass storage peripheral device, and configured to operate a motor. Computer architecture connected to said interface. The computer architecture of claim 1, wherein the mass storage peripheral device further comprises a positioning mechanism for positioning the sensor, wherein the computer architecture is located on the host computer. A computer architecture further comprising circuitry connected to the interface to operate the positioning mechanism. The computer architecture of claim 1, further comprising a read channel circuit connected to receive the amplified data signal. (18) The computer architecture according to item 17, wherein the read channel circuit is connected to the host circuit.
The computer architecture included in a computer.

(19) The computer architecture according to item 17, wherein the read channel circuit is included in the mass storage peripheral device.
architecture. 20. The computer architecture according to claim 17, wherein the read channel circuit is partially included in the host computer and partially included in the mass storage peripheral device. (21) A computer readable medium, a sensor for detecting information on the medium, and a data amplifier for amplifying the information detected on the medium to generate an amplified data signal. A computer architecture for use in a host computer with a plurality of associated mass storage peripheral devices of the type having an interface between the mass storage peripheral device and the host computer; and At least one at the host computer for receiving the information detected on the medium;
A control circuit for one of said mass storage peripherals. 22. The computer architecture according to claim 21, wherein the at least one control circuit includes a plurality of control circuits for a device associated with each of the plurality of mass storage peripheral devices. 23. The computer architecture of claim 21, wherein said at least one control circuit communicates said information to a bus mastering bus of said host computer. (24) The computer architecture according to paragraph 23, wherein the bus mastering bus is a PCI bus.
A computer architecture that is a bus. (25) The computer architecture according to paragraph 23, wherein the bus mastering bus is 139.
A computer architecture that is a type 4 bus. (26) The computer architecture according to paragraph 21, wherein at least one of the mass storage peripheral devices is provided.
One is the computer architecture, which is a disk drive assembly.

(27) The computer architecture according to paragraph 21, wherein at least one of the mass storage peripheral devices is a hard disk drive assembly. (28) The computer architecture according to paragraph 21, wherein at least one of the mass storage peripheral devices is provided.
The first is a computer architecture that is a CD-ROM disk drive assembly. (29) The computer architecture according to paragraph 21, wherein at least one of the mass storage peripheral devices is provided.
The first is the computer architecture, which is a DVD disk drive assembly. (30) The computer architecture according to paragraph 21, wherein at least one of the mass storage peripheral devices is provided.
The first is computer architecture, which is a floppy disk drive assembly. (31) The computer architecture according to paragraph 21, wherein at least one of the mass storage peripheral devices is provided.
One is the computer architecture, which is a high-capacity floppy disk drive assembly. (32) The computer architecture according to paragraph 21, wherein at least one of the mass storage peripheral devices is provided.
One is computer architecture, which is a small storage device. (33) The computer architecture according to paragraph 21, wherein at least one of the mass storage peripheral devices further includes a motor for rotating the medium, and the computer architecture further comprises the motor. A computer architecture including a servo circuit located on the host computer connected to the interface for operating. (34) The computer architecture according to paragraph 21, wherein at least one of the mass storage peripheral devices further includes a motor for rotating the medium, and a servo circuit for operating the motor. Computer architecture.

(35) The computer architecture according to paragraph 21, wherein at least one of the mass storage peripheral devices further includes a motor for rotating the medium, and for operating the motor, A computer architecture further comprising a servo circuit partially disposed on the host computer and partially disposed on the mass storage peripheral. (36) The computer architecture according to paragraph 21, wherein at least one of the mass storage peripherals further includes a positioning mechanism for positioning the sensor, wherein the computer architecture further comprises a host computer. A computer architecture including circuitry located at the computer and connected to the interface to operate the positioning mechanism. 37. The computer architecture of claim 21, further comprising a read channel circuit connected to receive the amplified data signal. (38) The computer architecture according to paragraph 37, wherein the read channel circuit is included in the host computer. (39) The computer architecture according to paragraph 37, wherein the read channel circuit is included in the mass storage peripheral device. (40) The computer architecture according to paragraph 37, wherein the read channel circuit is partially included in the host computer and partially included in the mass storage peripheral device. (41) A rotatable, computer-readable data medium, a motor for rotating the medium, a sensor for detecting information on the medium, and data for amplifying the information detected on the medium. A computer architecture for use with an associated mass storage peripheral of the type having an amplifier, the circuit board including circuitry for controlling operation of a computer, and an interface between the mass storage peripheral and the circuit board. And a control circuit on the circuit board for receiving a data signal directly from the data amplifier for use in the computer, and a servo circuit for driving the motor.

(42) A computer architecture according to item 41, wherein the control circuit interfaces with a bus mastering bus of the host computer. (43) The computer architecture according to item 42, wherein the bus mastering bus is a PCI bus.
A computer architecture that is a bus. (44) The computer architecture according to paragraph 42, wherein the bus mastering bus is 139.
A computer architecture that is a type 4 bus. (45) The computer architecture according to paragraph 41, wherein the mass storage peripheral device is a disk storage device.
A computer architecture that is a drive assembly. (46) The computer architecture according to paragraph 41, wherein the mass storage peripheral device is a hard disk drive assembly.
architecture. (47) The computer architecture according to item 41, wherein the mass storage peripheral device is a CD-RO.
A computer architecture that is an M disk drive assembly. 48. The computer architecture according to claim 41, wherein the mass storage peripheral device is a DVD disk drive assembly. (49) The computer architecture according to paragraph 41, wherein the mass storage peripheral device is a floppy disk drive assembly. (50) The computer architecture of paragraph 41, wherein the mass storage peripheral device is a high capacity floppy disk drive assembly. (51) The computer architecture according to paragraph 41, wherein the mass storage peripheral device is a small storage device.

(52) A computer architecture according to item 41, wherein the mass storage peripheral device further has a positioning mechanism for positioning the sensor, and the circuit board activates the positioning mechanism. Computer architecture including circuitry connected to said interface. 53. The computer architecture of claim 41, further comprising a read channel circuit connected to receive the amplified data signal. (54) The computer architecture according to paragraph 53, wherein the read channel circuit is included in the circuit board. (55) The computer architecture according to paragraph 53, wherein the read channel circuit is included in the mass storage peripheral device. 56. The computer architecture according to claim 53, wherein the read channel circuit is partially included in the circuit board and partially included in the mass storage peripheral device. (57) The computer architecture according to paragraph 41, wherein the computer architecture comprises:
When each is used with an associated plurality of mass storage peripherals of the type having a rotatable, computer-readable data medium and a motor for rotating the medium, each drives a respective one of the motors. A computer architecture further including a plurality of servo circuits. (58) The computer architecture of paragraph 57, wherein the plurality of servo circuits are included on a single integrated circuit chip of the circuit board. (59) A type having a computer-readable medium, a sensor for detecting information on the medium, and at least one data amplifier for amplifying the information detected on the medium to generate an amplified data signal. A computer architecture for use in a host computer with associated mass storage peripherals, comprising: an interface between the mass storage peripherals and the host computer; and a host computer for receiving information detected on a medium used by the computer. At least one in
Control circuitry for one of the mass storage peripherals. The control circuit preferably communicates information to a bus mastering bus of the host computer, for example, a PCI or 1394 bus.

[Brief description of the drawings]

FIG. 1 is a block diagram of a data processing path of a computer system having a host computer and a mass storage peripheral, showing the shape and location of each part according to a preferred embodiment of the present invention.

FIG. 2 is a computer system in which most of the electronic circuitry supporting the mass storage peripheral is located on a wiring board of a host computer in accordance with a preferred embodiment of the present invention.
FIG.

FIG. 3 is a block diagram of a portion of a computer system illustrating an example of an interface between a mass storage peripheral and a host computer in accordance with a preferred embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 10 computer architecture 11 host computer 12 mass storage peripheral device 14 medium 15 sensor 17 cable 20 preamplifier 22 positioning mechanism 24 read / write channel 26 line 28 controller 30 formatter 32 ECC 33 buffer manager 34 buffer 35 bus controller 36 bus 37 Servo logic 38 RAM 39 Program ROM 40 CPU 41 Processing engine 43 Memory manager

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G11B 33/02 301 G11B 33/02 301F

Claims (1)

[Claims] 1. A type comprising a computer readable medium, a sensor for detecting information on the medium, and a data amplifier for amplifying the information detected on the medium to generate an amplified data signal. A computer architecture for use on a host computer with associated mass storage peripherals, comprising: an interface between the mass storage peripherals and the host computer; and the information detected on the medium used by the computer. Control circuitry for at least one of said mass storage peripherals at said host computer to receive.