KR19990077504A - Computer architecture that enables operating circuitry and programs of an associated mass storage peripheral device to be located remotely from the device - Google Patents

Abstract

Use in a host computer having a tangible associated mass storage peripheral having a computer readable medium, a sensor for detecting information on the medium, and a data amplifier for amplifying the detected information on the medium to produce an amplified data signal. A computer architecture is provided. The computer architecture includes an interface between a mass storage peripheral device and a host computer, and at least one controller circuit for receiving mass information detected on a medium for use in the computer for mass storage peripheral devices within the host computer. The controller circuitry transfers information from the host computer onto a bus mastering bus, such as a PCI or 1394 type bus.

Description

COMPUTER ARCHITECTURE THAT ENABLES OPERATING CIRCUITRY AND PROGRAMS OF AN ASSOCIATED MASS STORAGE PERIPHERAL DEVICE TO BE LOCATED REMOTELY FROM THE DEVICE}

FIELD OF THE INVENTION The present invention relates to improvements in computer architecture, and more particularly to improvements in computer architecture that allow operating circuits and programs of mass storage peripherals to be located remotely from the device.

Mass storage peripherals have played a significant role in modern computer development. Typical mass storage devices include hard and floppy disk drives, CD-ROM drives, DVD devices, and the like.

Typical mass storage peripherals that can be associated with a computer have several electronic circuits for the operation of the device that are configured such that the device can be used as widely as possible with various processors or computer configurations. Typically, mass storage peripherals, for example, consist of a spinning data medium on which at least data can be read and sometimes data can be written. Such devices also generally include a motor that spins the medium, and one or more head devices that can move to selectable locations on the medium for reading and writing data from the medium. Associated electronic circuitry is often provided on a printed circuit board provided in an assembly with spinning media to control the rotation of the motor and the selective positioning of the head.

The particular electronic circuit in which any particular mass storage device may be provided may vary depending on the type and type of peripheral device considered. For example, a typical electronic circuit for a hard disk drive (HDD) assembly would be a servo or motor control circuit for spinning a motor, a voice coil control circuit for positioning a data head, amplifying a signal read by the head from a spinning medium. Data preamplifier circuitry, read channel processing circuitry for initial processing of the read data, and controller circuitry. The controller circuit may include buffer memory elements for speed matching and signal timing, signal interfacing circuitry for interfacing data and other signals to computer buses and control circuitry, error correction and control circuitry, and the like. Such circuits are typically contained within as many as nine separate integrated circuit chips and provided in a number of integrated circuit devices mounted on a printed circuit board associated with a particular peripheral device.

Hard disk drive electronics are typically connected to corresponding buses on a "mother board" of the host computer by one or more buses. The mother board may have its own supporting electronics for peripherals such as line driver circuits and data processing circuits to route and control various signals provided to / from the peripherals.

Because each particular mass storage peripheral can have its own specific hardware and software characteristics that can be unique, the mass storage device is typically also properly initialized for the associated computer to address and access the device's data. It may be required to include its own custom firmware. Among other things, such firmware may include information about how the address is translated from a computer to a particular arrangement of mass storage devices such as cylinders, heads, sectors, zones, etc. of the mass storage device. Such peripherals are typically supplied with on-demand firmware that is loaded into the system RAM upon initialization of the associated computer.

In most cases, a software driver may also be required. Such software drivers are often provided by generic drivers supplied with computer operating system software, and in other cases the drivers may be provided separately by the manufacturer of a particular peripheral, especially when the particular peripheral has special or unusual characteristics. . Therefore, it can be seen that when peripherals must be compatible with existing computer hardware architectures and designs, there are limitations in particular hardware variations that can be provided on any peripheral device.

As the speed of data access increases, hardware and software technologies have been developed to increase the data transfer rate to / from these mass storage devices. One such technology that is of interest is the preparation of a Peripheral Component Interconnect (PCI) bus. In addition to providing increased data access speeds to the data on peripherals, the PCI bus is a processor and computer system architecture independent of the remaining PCI electrical, protocol, and hardware interface requirements, regardless of the CPU or host system computer architecture being used. It is designed to be. This allows the same peripheral computer device to be connected to several different host computers without requiring different versions of the device for each type of host system for which the device is to be used.

In addition, the PCI bus architecture allows expansion ROM location addresses to be relocatable on associated peripherals. To further understand the PCI bus characteristics in connection with mass storage peripherals, the invention is used herein as a reference and assigned to this assignee, entitled "METHOD AND ARRANGEMENT FOR OPERATING A MASS MEMORY STORAGE PERIPHERAL COMPUTER DEVICE CONNECTED TO A" See HOST COMPUTER "PCT Application No. WO 97/18505.

The mass memory storage peripheral can also include on-demand extended BIOS data that is loaded into the system RAM upon initialization of the associated computer. Details of specific BIOS technologies are described in PCT application WO 97/14095, entitled "SYSTEM FOR PROVIDING BIOS TO HOST COMPUTER", which is hereby incorporated by reference and assigned to this assignee.

One goal of mass storage peripheral manufacturers is to reduce device costs as much as possible. This has been accepted primarily by increasing the level of electronic component integration, with reduced integrated circuit costs for the functions provided due to the shrinking of the semiconductor geometry. However, these reductions were not outstanding at the system level. Using this approach, we can see that the required electronics and hardware requirements are similar to the PCI bus.

Therefore, in view of the above description, it is an object of the present invention to provide an improved computer architecture that enables the operating circuitry and programs of a mass storage peripheral device associated with a computer to be located remotely from the device.

Another object of the invention is to provide at least some of the functions of a mass storage peripheral with which one integrated circuit is associated, for example an improved computer architecture of the type described above that is disposed away from the mass storage peripheral on a computer bed. It is to provide.

It is another object of the present invention to provide an improved computer architecture of the type described above in which one integrated circuit that controls the associated mass storage peripheral is designed for use with a PCI bus.

It is another object of the present invention to provide an improved computer architecture of the type described above in which one PCI mass storage integrated circuit is provided to control one or more associated mass storage peripherals.

It is a further object of the present invention to provide an improved computer architecture of the type described above which allows the cost of the peripheral devices associated with the architecture to be lower than the devices currently in use, including the required device electronics.

It is yet another object of the present invention to provide a computer architecture that does not require better knowledge than the specification of a particular mass storage device, and alleviates the design requirements of a computer to accommodate a wide range of mass storage peripherals.

Other objects, features and advantages of the present invention will become apparent to those skilled in the art from the following detailed description of the invention with reference to the accompanying drawings and claims.

A computer architecture is a host computer having a tangible associated mass storage peripheral having a computer readable medium, a sensor that detects information on the medium, and a data amplifier that amplifies the information detected on the medium to produce an amplified data signal. Provided for use in The computer architecture includes an interface between the mass storage peripheral device and the host computer, and minimal controller circuitry for the mass storage peripheral device within the host computer for receiving detected information on the medium for use in the computer. Preferably, the controller circuitry transfers information onto a bus mastering bus that is a PCI or 1394 type bus in the host computer.

Mass storage peripherals can be disk drive assemblies, hard disk drive assemblies, CD-ROM disk drive assemblies, DVD disk drive assemblies, floppy disk drive assemblies, high capacity floppy disk drive assemblies, small storage devices, and the like. The mass storage peripheral can have a motor that rotates the medium, and the servo circuit can be located within the host computer and connected to the interface to operate the motor, and can be located within the mass storage peripheral, or partly the host computer. And in part within a mass storage peripheral.

The mass storage peripheral may also have a positioning mechanism for positioning the sensor, and the computer architecture may include circuitry located within the host computer and connected to the interface to operate the positioning mechanism.

The computer architecture may include a read channel circuit connected to receive the amplified data signal. Read channel circuitry may be partially embedded within a host computer, within a mass storage peripheral, or each.

According to another broad aspect of the invention, a computer architecture comprises a computer amplifier of each type, a sensor for detecting information on the medium, and a data amplifier for amplifying the detected information on the medium to produce an amplified data signal. Provided for use in a host computer having a number of associated mass storage peripherals. The computer architecture includes an interface between the mass storage peripheral and the host computer, and at least one controller circuit for the mass storage peripheral in the host computer for receiving detected information on the medium of the device for use in the computer. The controller circuit may include a number of controller circuits for each associated device of the plurality of mass storage peripherals, or one controller circuit may be configured to transfer information onto a bus mastering bus in a host computer.

The computer architecture may also have servo circuitry located within a host computer connected to the interface for operating the motor of the mass storage peripheral device.

According to another broad aspect of the invention, a computer architecture is of a type that has a rotatable computer readable medium, a motor that rotates the medium, a sensor that detects information on the medium, and a data amplifier that amplifies the detected information on the medium. Provided for use with associated mass storage peripherals. Computer architectures have circuit boards that contain circuitry that controls the operation of the computer, and an interface between the mass storage peripherals and the circuit board. The controller circuit on the circuit board receives the data signal directly from the data amplifier for use in a computer, and a servo circuit is provided for driving the motor.

The same reference numbers are used for the same parts in the various drawings.

1 is a block diagram of a data processing path of a computer system having a host computer and mass storage peripherals, illustrating the configuration and location of the components, in accordance with a preferred embodiment of the present invention.

2 is a block diagram of a computer system in which most electronic components for supporting mass storage peripherals are disposed on a circuit board of a host computer, in accordance with a preferred embodiment of the present invention.

3 is a block diagram of a portion of a computer system, illustrating an example of an interface between a mass storage peripheral device and a host computer, in accordance with a preferred embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

11: host computer

12: Mass Storage Peripherals

14: data medium

15: sensor

20: preamplifier

22: positioning mechanism

24: read / write channel circuit

28: controller

37: servo logic

40: CPU

52: circuit board

54: mass storage integrated circuit

72: chipset

73: RAM

The object of the invention is achieved by the configuration and arrangement of the mass storage peripheral device and its associated host computer as described in more detail below. A “host computer” is used to refer to any device to which mass storage devices can be operatively associated and has a central processing unit (CPU), memory, and a bus mastering bus. Bus mastering bus is a bus that allows a device to make memory access requests without requiring coordination or relationship with the CPU, and may be located on a circuit board, or “parent plate”, and may be an integrated circuit chip, such as a CPU chip, It can be embedded in a cable or other chip. Examples of suitable bus mastering buses are the PCI bus or the 1394 bus, which are well known. (PCI stands for Peripheral Computer Interconnect. PCI is a high-speed, high-bandwidth, 32 / 64-bit, 33/66 MHz, processor-independent expansion bus.) However, it should be understood that any suitable bus mastering bus can be used. .

In brief, the present invention is realized by placing a number of operating circuits, programs, and firmware in a host computer that are traditionally located on a circuit board of a peripheral device. Thus, for example, the controller of the mass storage peripheral device is located in a host computer, such as on a bed plate. Additional circuitry may also be located within the host computer including servo circuitry to spin the motor of the peripheral device, and voice coil actuation circuitry for positioning the data sensor of the peripheral device. Thus, the amount and cost of electronic circuitry located in a conventional manner on the peripheral device is removed from the device and located away from the device. This has the effect of reducing the overall cost of certain mass storage peripherals of the present invention. This also makes it possible to reduce the total number of parts.

A block diagram of a data processing path of a computer system 10 having a host computer 11 and a mass storage peripheral 12 is shown in FIG. 1, which shows the configuration of components according to a preferred embodiment of the present invention. The location is shown. The mass storage peripheral device includes a data medium 14 and a sensor 15 for at least reading data from the medium 14. As will be apparent to those skilled in the art, the physical form of the data carrier and the sensor may vary depending on the particular type of device contemplated. For example, the principles of the present invention may be applicable to mass storage peripherals such as hard disk drives, floppy disk drives, high density floppy disk drives, CD-ROM drives, DVD drives, small drives, and other drives. Is expected.

Typically, the signal detected by the sensor 15 is communicated to the preamplifier 20 by a "flex cable" 17. Preamplifier 20 may be configured on flex cable 17, or may be separated from them. Sensor 15 is positioned by positioning mechanism 22 to a selectable position on data carrier 14 in a known manner.

The output of the preamplifier is read / write channel circuitry, which may be partially embedded in the mass storage peripheral device 12, entirely in the host computer 11, or in each of them, as described in more detail below, as indicated by the dotted lines. 24). The read / write channel is connected to amplified analog data read by the head 15 such as filtering, analog / digital conversion in each read and write path, automatic gain control, pulse detection, encoding / decoding for read / write functions, and the like. Implement a variety of functions. The output from the read / write channel on line 26 is raw digital data that is passed to the peripheral controller 28.

In read mode, controller 28 receives raw digital data on line 26 and formats it in formatter or procedure circuit 30. The formatted data is then error corrected in the error correction and control circuit (ECC) 32 and then buffered in the second buffer 34 under the control of the buffer manager 33. The function of the ECC circuit 32 is to use an error correction portion of the read data to ensure that the scheduled data can be used properly. In the write mode, the functions are the same, but in the reverse order. The reverse path ECC circuit 32 generates error correction data and attaches it to the data written in the medium 14. According to a preferred embodiment of the present invention, the entire controller is located within the host computer 11, for example on an integrated circuit on the mother board. Also, controller 28 typically includes bus controller circuit 35, servo logic 37, program ROM 39, and processing engine 41, as shown.

The output from the controller 28 is connected to the above-described bus mastered bus 36 which is written or read into a memory such as RAM 38 under the control of the memory manager 43. As described above, the CPU 40 is included as part of the host computer 11 but is not necessarily related to the control or derivation of data transfers to / from the memory 38.

Preferably, most of the electronic components required for the operation of the mass storage peripheral device are located on the mother plate of the host computer as shown in FIG. Therefore, the computer system 50 includes a circuit board 52 such as a mother board of a host computer. Also, preferably, the controller and other electronic components can be included in one integrated circuit 54 where a servo signal that spins the motor of the peripheral device is located in the second single integrated circuit 56. As shown, there are three large sample storage peripherals 58, 60, 62 with respect to the computer 50. In the illustrated embodiment, mass storage peripheral 58 is a hard disk assembly (HDA). HDA is part of a typical hard disk drive (HDD).

As can be seen, the most necessary components of the drive, such as controllers, servos, and other electronic components disposed on the mother board 52, are the data medium, the motor that spins the medium, reads data to or from the medium. A sensor or head mechanism for writing, a preamplifier that amplifies data to be read from or written to the medium, and a case housing the parts. This minimal version of HDD is referred to herein as HDA. It can be readily seen that the cost of HDA can be considerably cheaper than a typical HDD of compatible capacity. In the illustrated embodiment, mass storage peripheral 60 may be a CD-ROM or a digital video device (DVD). Finally, in the illustrated embodiment, mass storage peripheral 62 may be a floppy drive, a high capacity floppy drive, a small drive, or some other suitable device.

Each peripheral 58, 60 and 62 may also have an associated "real ROM" 64, 66 and 68, respectively. The reality ROM serves to maintain the actual data definition of certain associated mass storage peripheral characteristics.

More specifically, the circuit board 52 of the host computer includes the PCI mass storage integrated circuit 54, the servo integrated circuit 56, the CPU 70 and the CPU chipset 72 associated with it, and the RAM 73. Include. An example of a chipset and CPU that can be used is the Cyrix "MediaGX" product, where the "North Bridge" chipset is integrated with the host CPU and other system arrangements may be used as well. A bus mastering bus, such as the PCI bus 74 shown, interconnects the chipset 72 to the PCI mass storage integrated circuit 54. Although PCI mass storage I / C 54 is shown as a separate chip, it should be appreciated that this may be integrated into chipset 74 with any particular computer system.

Referring now specifically to PCI mass storage integrated circuits, one I / C is provided in the illustrated embodiment that includes the electronic components needed to support the three mass storage peripherals 58, 60 and 62 shown. . The circuitry includes one or more digital signal processors (DSPs), read channels, buffer managers, rate matching buffers, masked ROM, servo logic, formatting, and error detection and correction (EDAC) circuits. Certain circuits contained within PCI mass storage I / C 54 are known in the art, and the manner in which integrated circuits containing such circuits can be fabricated is also well versed in the art, and therefore, will no longer be discussed in detail herein. I will not explain.

Preferably, as shown, the servo I / C 56 includes all the servo circuits needed to spin and control the motors of the associated mass storage peripherals 58, 60, and 62. As shown, three separate servo circuits 74-76 can be integrated on one chip. Alternatively, one servo circuit can be used. It should be noted that the position of the servo I / C 56 on the base plate 52 is preferred, and the servo circuit can be positioned in various ways. For example, the servo circuit may be located on each mass storage peripheral 58, 60, and 62, although its cost and operational benefits may not be fully realized. Alternatively, the servo circuit may be distributed such that a portion of the servo circuit is located on the mother board 52 and a portion is located on each mass storage peripheral device.

One feature of the mass storage peripherals used in conjunction with the circuit arrangement shown in FIG. 2 is the preparation of "real ROM" 64, 66 and 68 with respective mass storage peripherals 58, 60 and 62, respectively. As discussed above, the substance ROM contains the information needed by the host computer to initialize to run properly without the need for detailed driver software. The characterization of data items that may be included in the substance ROM of mass storage peripherals is described in the following table. This table is not exhaustive and other data items may also be included. In addition, this table is described by way of example only, and is not an absolute requirement. Other arrangements may be apparent to those skilled in the art.

offset size Field name Explanation 0-1 2 Structure ID ID number for the current structure definition. The structure ID number described here is set to zero. This allows the firmware to know what structure is coming back from the mass storage device. 2-41 40 Identification string Vendor / Mass Storage Identification String. The left side is defined as a string. Blanks are filled to the right of them. 42-43 2 Physical heads Total number of physical heads in mass storage 44-45 4 Head count Total number of physical heads actually available in mass storage after manufacturing 46-49 4 Effective Head Flag Flag indicating which physical heads are active and available. This should be set to the number of valid heads remaining after the manufacturing process and should be used to indicate if a certain head de-allocation has been performed. The least significant bit (LSB) is for head 0 and the most significant bit (MSB) is for head 32. A value of 1 indicates that the head is available. 50-51 2 The number of accessible physical cylinders Total number of accessible read / write cylinders in mass storage. The first cylinder will start with a certain positive number (ie ≧ 0) of cylinder numbers. 52-53 2 Start cylinder for extended BIOS data area Starting physical cylinder for extended BIOS data area, starting position of contiguous areas on mass storage media without breaks or holes. 54-55 2 Number of Extended BIOS Area Cylinders Total number of physical cylinders in the extended BIOS data area 56-57 2 Start cylinder for utility data area Starting physical cylinder for the utility data area, starting position of the contiguous area on the mass storage medium without breaks or holes.

offset size Field name Explanation 58-59 2 Number of cylinders in the utility data area Total number of physical cylinders in the utility data area 60-61 2 The starting cylinder for the user data area Starting physical cylinder for the user data area. This area may be disconnected or contained within one of the following data areas: Extended BIOS Data Area Utility Data Area One, two or all of these grown defective areas If included in a user data area, the user data area cylinders do not include the number of cylinders in these areas. The user data area cylinder is defined to stop counting on the cylinder before one of these areas and to start counting immediately after one of these areas. Two or more of these areas can be grouped together into one large break in the user data area. The firmware must recognize the break and coordinate the logical to physical movement to properly read and write the user data. . 62-63 2 Number of user data area cylinders The total number of physical cylinders in the user data area 64-65 2 Starting cylinder of slippage defect area Starting physical cylinder for slipped defective area. This area must be physically continued after the last user data area cylinder. 66-67 2 Number of slipped defective area cylinders Total number of physical cylinders in the slippage defect area 68-69 2 Starting cylinder of grown defect area Starting position of the continuous region on the mass storage medium without starting physical cylinder breaks or hole portions for grown defective regions 70-71 2 Number of grown defect area cylinders Total number of physical cylinders in grown defect area 72-73 2 Number of logical cylinders The number of logical cylinders on the mass storage device to be displayed to the operating system. These numbers are provided by the mass storage device manufacturer. The firmware uses this value to present a logical model to the operating system when the LBA value is not used. 74-75 2 Number of logical heads The number of logical heads on mass storage that will be displayed to the operating system. These numbers are provided by the mass storage device manufacturer. The firmware uses this value to present a logical model to the operating system when the LBA value is not used. 76-77 2 Number of logical sectors per track Number of logical sectors per track on mass storage that will be displayed to the operating system. These numbers are provided by the mass storage device manufacturer. The firmware uses this value to present a logical model to the operating system when the LBA value is not used.

offset size Field name Explanation 78-81 4 Maximum User Area Logical Block Address Maximum user area logical block address. This number indicates the last valid logical block address on the drive. Note: This number is the maximum logical block address used on the drive. Logical block addresses are counted starting from zero. Therefore, if this number is reported as 999, the actual number of available user sectors is 1000. 82-83 2 Internal buffer byte count Number of internal data buffer bytes in mass storage 84-91 8 Firmware revision number Firmware revision number 92-93 2 Form element and manufacturing device type code The lower byte of this code is a form element code that describes the form element of the current mass storage device. This can be used to uniquely identify process related files and data for current mass storage devices. The file name can be made using this field data along with the capacity number and the HDA ID code. The following type element codes are defined. 'A'-1.8 "Type III Disk Drive 'B'-1.8" Type II Disk Drive 'C'-1.8 "Type I Disk Drive 'D'-2.5" * 12.5mm Height Disk Drive 'E'-2.5 "* 10 ㎜ height disk drive 'F'-2.5 "* 8 ㎜ height disk drive 'G'-3.0" * 1 "height disk drive 'H'-3.0" * 0.5 "height disk drive 'I'-3.5" full height disk drive 'J'-3.5 "* 1" Height Disk Drive 'K'-3.5 "* 0.5" Height Disk Drive 'L'-5.25 "Full Height Disk Drive 'M'-5.25" Half Height Disk Drive All other form element codes Reserved for future use. The upper byte of this code is a manufacturing device type code that uniquely distinguishes between mass storage devices and shape elements that have the same capacity. Use only for reporting purposes do. 94 One Fault method code The fault method code matches the firmware to what type of low level format is being used by the mass storage firmware. 95 One Fault structure code The fault structure code matches the firmware to which data structure was used to store the fault in. See Section 4.1.3 for a detailed description of the defined fault structure and what fault structure codes are assigned to each structure.

offset size Field name Explanation 96-97 2 Read channel and servo data area storage size The read channel and servo data area storage sizes match the firmware to how much host memory is required to store the read channel and servo data of the mass storage device. The firmware will use this number for memory allocation and assign that memory address to the mass storage device. This number is the number of memory bytes required by the mass storage device to store the read channel and servo data. 98-99 2 Maximum manufacturing defect data area storage size The maximum manufacturing defect data area storage size matches the firmware with how much host memory is required to store manufacturing defect data in the mass storage device. The firmware uses this number for memory allocation and will assign that memory address to the mass storage device, which is the number of memory bytes required by the mass storage device to store manufacturing defect data of the mass storage device. 100-101 2 Maximum growth defect data area storage size The maximum growth defect data area storage size matches the firmware how much host memory is required to store the growth defect data of the mass storage device. The firmware uses this number for memory allocation and will assign that memory address to the mass storage device, which is the number of memory bytes required by the mass storage device to store the growth defect data of the mass storage device. 102-125 24 reservation Reserve for future data 126-127 2 Number of zones Number of read / write zones defined for mass storage 128-255 (128+ (number of zones * bytes per zone) -1) Up to 128 bytes of data real- (number of zones * bytes per zone) Zone-specific data Zone specific data arrays contain one structure entry for each zone. This structure provides support for up to 32 zones. Each zone contains 4 bytes of data. 4 bytes of data * 32 zones = 128 bytes of maximum zone data 2 John's first cylinder John's first physical cylinder 2 Sectors Per Track Total number of sectors per track in the zone

In accordance with a preferred embodiment of the present invention, a block diagram of a portion of a computer system showing one example of an interface 74 between a mother board 52 of a host computer and a mass storage peripheral 58 is shown in FIG. Therefore, the servo I / C 56 is one of the coil windings A, B, C and CT of the motor winding 76 to spin and control a motor (not shown) of the mass storage peripheral 58. Provide the path of It should be noted that the read channel circuits 80, 80 'and 80 "are shown in dashed lines to show the possible locations of the circuit depending on the particular needs of the system and mass storage peripherals. It may be located entirely within the storage peripheral 58, and optionally may also be entirely located at a location 80'inside the PCI mass storage I / C 54. In addition, a portion may be located in the mass storage peripheral 58. Other portions may be allocated within the mass storage peripheral 58. In addition, the read channel circuitry may be located in a separate chip or in an integrated circuit at position 80 "on the mother board 52.

Thus, the computer architecture is improved so that the operating circuits and programs of the mass storage peripherals associated with the computer can be located far from the device.

In addition, a computer architecture is provided in which an integrated circuit controls at least some of the functions of the associated mass storage peripherals, for example, so that they are spaced apart from the mass storage peripherals on the computer bed.

In addition, the cost of peripheral devices associated with the architecture can be lower than the devices currently in use, including device electronics required.

In addition, it does not require greater knowledge than the specification of a particular mass storage device, and can alleviate the design requirements of a computer to accommodate a wide range of mass storage peripherals.

While the invention has been shown and described in accordance with several features, it is merely an example, and combinations of parts by those skilled in the art and without departing from the spirit and scope of the invention as set forth in the appended claims. Many changes in layout are possible.

Claims (58)

A host computer having a tangible mass storage peripheral having a computer readable medium, a sensor that detects information on the medium, and a data amplifier that amplifies the information detected on the medium to produce an amplified data signal. In a computer architecture for use in An interface between the mass storage peripheral and the host computer, and At least one controller circuit for receiving said information detected on said medium for use in said computer, for said mass storage peripheral device within said host computer. Computer architecture comprising a. The computer architecture of claim 1, wherein the controller circuitry passes the information onto a bus mastering bus in the host computer. 3. The computer architecture of claim 2, wherein the bus mastering bus is a PCI bus. 3. The computer architecture of claim 2, wherein the bus mastering bus is a 1394 bus. The computer architecture of claim 1, wherein the mass storage peripheral is a disk drive assembly. The computer architecture of claim 1, wherein the mass storage peripheral is a hard disk drive assembly. The computer architecture of claim 1, wherein the mass storage peripheral is a CD-ROM disk drive assembly. The computer architecture of claim 1, wherein the mass storage peripheral is a DVD disk drive assembly. The computer architecture of claim 1, wherein the mass storage peripheral is a floppy disk drive assembly. The computer architecture of claim 1, wherein the mass storage peripheral is a high capacity floppy disk drive assembly. The computer architecture of claim 1, wherein the mass storage peripheral is a small storage device. The computer architecture of claim 1, wherein the mass storage peripheral further comprises a motor to rotate the medium. 13. The computer architecture of claim 12, wherein the servo circuit is located in the host computer and connected to the interface to operate the motor. 13. The computer architecture of claim 12, wherein the servo circuit is located within the mass storage peripheral and is connected to operate the motor. 13. The computer architecture of claim 12, wherein the servo circuitry is located partially in the host computer, partially located in the mass storage peripheral, and connected to the interface to operate the motor. The device of claim 1, wherein the mass storage peripheral further comprises a positioning mechanism for positioning the sensor, wherein the computer architecture is located within the host computer and connected to the interface to operate the positioning mechanism. Computer architecture, characterized in that it further comprises. 2. The computer architecture of claim 1, further comprising read channel circuitry coupled to receive the amplified data signal. 18. The computer architecture of claim 17, wherein the read channel circuitry is embedded in the host computer. 18. The computer architecture of claim 17, wherein the read channel circuitry is embedded in the mass storage peripheral. 18. The computer architecture of claim 17, wherein the read channel circuitry is partially embedded in the host computer and partially embedded in the mass storage peripheral. A number of associated mass storage peripherals of a type each having a computer readable medium, a sensor for detecting information on the medium, and a data amplifier for amplifying the detected information on the medium to produce an amplified data signal. In a computer architecture for use in a host computer having: An interface between the mass storage peripheral and the host computer, and At least one controller circuit for receiving said information detected on said medium of said device for use in said computer, for said mass storage peripheral device in said host computer. Computer architecture comprising a. 22. The computer architecture of claim 21, wherein the at least one controller circuit comprises a plurality of controller circuits for each associated peripheral of the plurality of mass storage peripherals. 22. The computer architecture of claim 21, wherein the at least one controller circuit conveys the information on a bus mastering bus in the host computer. 24. The computer architecture of claim 23 wherein the bus mastering bus is a PCI bus. 24. The computer architecture of claim 23 wherein the bus mastering bus is a 1394 bus. 22. The computer architecture of claim 21 wherein at least one of the mass storage peripherals is a disk drive assembly. 22. The computer architecture of claim 21 wherein at least one of the mass storage peripherals is a hard disk drive assembly. 23. The computer architecture of claim 21, wherein at least one of the mass storage peripherals is a CD-ROM disk drive assembly. 22. The computer architecture of claim 21, wherein at least one of the mass storage peripherals is a DVD disk drive assembly. 22. The computer architecture of claim 21 wherein at least one of the mass storage peripherals is a floppy disk drive assembly. 23. The computer architecture of claim 21, wherein at least one of the mass storage peripherals is a high capacity floppy disk drive assembly. 23. The computer architecture of claim 21, wherein at least one of the mass storage peripherals is a small storage device. 22. The device of claim 21, wherein at least one of the mass storage peripherals further comprises a motor for rotating the medium, the computer architecture further comprising a servo circuit, the servo circuit being connected to the interface. A computer architecture located in the host computer to operate the motor. 22. The computer architecture of claim 21, wherein at least one of the mass storage peripherals further comprises a motor for rotating the medium and a servo circuit connected to operate the motor. 22. The device of claim 21, wherein at least one of the mass storage peripherals further comprises a motor for rotating the medium, partially located within the host computer and partially located within the mass storage peripheral. And a servo circuit for operating the motor. 22. The device of claim 21, wherein at least one of the mass storage peripherals further comprises a positioning mechanism for positioning the sensor, wherein the computer architecture is located within the host computer and connected to the interface. And further comprising circuitry for operating the positioning mechanism. 22. The computer architecture of claim 21, further comprising read channel circuitry coupled to receive the amplified data signal. 38. The computer architecture of claim 37, wherein the read channel circuitry is embedded in the host computer. 38. The computer architecture of claim 37, wherein said read channel circuitry is embedded in said mass storage peripheral device. 38. The computer architecture of claim 37, wherein the read channel circuitry is partially embedded in the host computer and partially embedded in the mass storage peripheral device. Use with tangible associated mass storage peripherals having a rotatable computer readable data medium, a motor that rotates the medium, a sensor that detects information on the medium, and a data amplifier that amplifies the information detected on the medium. In the computer architecture to A circuit board comprising circuitry for controlling the operation of a computer An interface between the mass storage peripheral and the circuit board, A controller circuit on the circuit board for receiving a data signal directly from the data amplifier for use in the computer, and Servo circuit driving the motor Computer architecture comprising a. 42. The computer architecture of claim 41 wherein the controller circuitry interfaces to a bus mastering bus in the host computer. 43. The computer architecture of claim 42 wherein the bus mastering bus is a PCI bus. 43. The computer architecture of claim 42 wherein the bus mastering bus is a 1394 bus. 42. The computer architecture of claim 41 wherein the mass storage peripheral is a disk drive assembly. 42. The computer architecture of claim 41 wherein the mass storage peripheral is a hard disk drive assembly. 42. The computer architecture of claim 41 wherein the mass storage peripheral is a CD-ROM disk drive assembly. 42. The computer architecture of claim 41 wherein the mass storage peripheral is a DVD disk drive assembly. 42. The computer architecture of claim 41 wherein the mass storage peripheral is a floppy disk drive assembly. 42. The computer architecture of claim 41 wherein the mass storage peripheral is a high capacity floppy disk drive assembly. 42. The computer architecture of claim 41 wherein the mass storage peripheral is a small storage device. 42. The device of claim 41, wherein the mass storage peripheral further comprises a positioning mechanism for positioning the sensor, and wherein the circuit board includes circuitry connected to the interface to operate the positioning mechanism. Computer architecture. 42. The computer architecture of claim 41 further comprising read channel circuitry coupled to receive the amplified data signal. 54. The computer architecture of claim 53 wherein the read channel circuit is included on the circuit board. 54. The computer architecture of claim 53 wherein the read channel circuitry is embedded in the mass storage peripheral device. 55. The computer architecture of claim 53, wherein the read channel circuitry is partially included on the circuit board and partially embedded in the mass storage peripheral device. 42. The computer architecture of claim 41, wherein the computer architecture for use with a plurality of tangible mass storage peripherals of a type each having a rotatable computer readable data medium and a motor for rotating the medium, respectively. And a plurality of servo circuits for driving. 59. The computer architecture of claim 57, wherein the plurality of servo circuits are embedded in one integrated circuit chip on the circuit board.