JP2000029687A - Method and device for packing and unpacking data on central processing unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method and a device for packing and unpacking data on a CPU with improved machine performance. SOLUTION: A memory array 120 is provided with plural memory addresses, a register 110 is provided with a most significant byte 112 and a least significant byte 114 and a pointer 150 and an index value indicate the memory address 142 provided with a high-order memory value 140 and a low-order memory value 138. In the case that the index value is an odd number (even number), a byte value is read from the high-order memory value 140 (low-order memory value 138) and stored in the most significant byte 112 (least significant byte 114) of the register and the byte value read from the register 110 is stored in the high-order memory value 140 (low-order memory value 138) of the memory address 142.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates generally to central processing units and, more particularly, to a method and apparatus for packing and unpacking data.

[0002]

The retrieval and storage of data using memory arrays and registers is well known in the art and is used in almost all computer architecture applications. A central processing unit (CPU) reads and writes data from and to a memory in the course of executing an operation. These operations are 1
It can occur on machines that can be addressed with 6 bits or more. However, operations may require byte (8 bit) sized data. The CPU receives an instruction to retrieve a byte-sized data word from memory. For example, this instruction
It is generated from software running in U and data necessary to execute the software. Then the CPU
Receives a 16-bit data word from the memory array, but requires additional operations on the data before it can be used in an 8-bit application.

[0003] These operations are known as packing and unpacking. Packing is an operation that groups two or more characters into one word. Unpacking is the inverse operation of packing,
Separates two or more characters stored in one word. The device can perform these operations to read a byte from the memory location and merge that byte with other bytes in the CPU registers. However, more instructions are needed to perform the opposite task, writing a byte to a given storage location.

[0004] High-level languages such as "C" process byte-sized data when performing operations. Many advanced embedded applications, such as disk drives, handle 16-bit data types. Byte size data can be processed by these sophisticated embedded applications, but not very often. As system RAM requirements increase, additional software routines are required to perform the required byte operations while performing the processing of byte-size data available for 16-bit operations. Become.

[0005] The solution to the 8-bit to 16-bit compatibility problem has been the design of 8-bit addressable machines. However, using an 8-bit addressable machine reduces the device address range by half. In addition, byte addressable machines require that all on-chip memory be addressable as 8-bit memory. The large address range obtainable by 16-bit machines is not accessible on these 8-bit machines. Another solution has been to use software instructions to implement the function of retrieving byte-sized data from 16-bit memory. The use of software instructions degrades machine performance due to increased code size and increased RAM requirements. As travel time increases, efficiency and performance decrease.

[0006]

SUMMARY OF THE INVENTION From the foregoing, there is a need for a method of packing and unpacking data in a central processing unit without compromising address range capabilities, i.e., without increasing system RAM requirements. It will be understood that there is. In accordance with the present invention, there is provided a method and apparatus for packing and unpacking data on a central processing unit with substantially eliminating or reducing disadvantages and problems associated with conventional data processing operations.

[0007] An apparatus for packing and unpacking data on a central processing unit is disclosed. The apparatus includes a memory array having a plurality of memory addresses, and a pointer and an index value point to a memory address in the memory array. The memory address has an upper memory value (high memory value) and a lower memory value (low memory value). The device further includes a byte value that is read from a higher memory value if the index value is odd and from a lower memory value if the index value is even. The apparatus further includes a register having a most significant byte and a least significant byte. The byte value is stored in the most significant byte when commanded by the central processing unit and in the least significant byte when commanded by the central processing unit. The apparatus further includes a packing instruction that retrieves a byte value from the memory address into a register. The apparatus further includes an unpacking instruction that reads a byte value from a register to a memory address in the memory array.

In another embodiment, a method for packing and unpacking data on a central processing unit according to the present invention comprises:
Includes two steps. The first step involves using a pointer and an index value to indicate a memory address in the memory array. The memory address has an upper memory value and a lower memory value. The second step involves retrieving the byte value from the memory address, where the byte value is read from the upper memory value if the index value is odd and from the lower memory value if the index value is even. Is read. The third step involves writing a byte value to the register. A register can have a most significant byte and a least significant byte. The fourth step involves reading a byte value from a register. The fifth step involves storing the byte value in the upper memory value if the index value is odd, and storing the byte value in the lower memory value if the index value is even.

A technical advantage of the present invention is that a method is provided for packing and unpacking data on a central processing unit. Another technical advantage of the present invention is that efficient processing of 8-bit data is achieved on a 16-bit addressable machine. Another technical advantage of the present invention is that it does not require sophisticated system RAM requirements or execute with additional software instructions.
The ability to pack and unpack 8-bit data in bit memory. Another technical advantage of the present invention is that
The ability to process 8-bit data together using a high-level language such as "C". Another technical advantage of the present invention is that there is no need to modify 16-bit memory so that it can be addressed as 8-bit memory. Another technical advantage of the present invention is that the disclosed method works efficiently. Another technical advantage of the present invention is that the number of instructions that perform packing and unpacking tasks in a central processing unit is reduced. Another technical advantage of the present invention is that advanced embedded applications that handle 16-bit data types can run on the same architecture that handles byte operations. Another technical advantage of the present invention is that the disclosed invention incorporates existing addressing modes.

[0010]

BRIEF DESCRIPTION OF THE DRAWINGS For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which like reference numerals designate like parts, and in which: FIG.

[0011] Embodiments of the present invention and its advantages are best understood by referring to the accompanying drawings in detail. In the drawings, like reference numbers indicate similar parts. 1 to 3 illustrate an apparatus and method for packing and unpacking data on a central processing unit according to an embodiment of the present invention.

FIG. 1 shows a central processing unit (CPU) 100. CPU 100 may be any 16-bit addressable machine that can perform processing on byte-sized (8-bit) data.

The register 110 and the memory array 120 may be provided on the CPU 100. The register 110 may be a 16-bit register, and the memory array 120
Any 16-bit memory that stores data as 16-bit words may be used. These 16-bit words include two 8-bit or byte-sized data words.

In accordance with the present invention, byte size data is packed and unpacked from a 16-bit memory, such as shown in memory array 120, into a 16-bit register, such as the register shown in register 110. Register 110 may include a most significant byte 112 and a least significant byte 114. In one embodiment, the most significant byte 112 includes the upper byte (bits 8-15) of the register 110. Also, the most significant byte 112 can store a byte size data word. The least significant byte 114 contains the lower byte (bits 0-7) of the register 110. Like the most significant byte 112, the least significant byte 114 can store a byte size data word.

The register 110 can read and write data from and to the memory array 120. In the memory array 120, the memory address 124 is a 16-bit
It is a memory register. Also, the memory address 12
8, 132, 136, 142 are 16-bit memory registers in the memory array 120. Memory address 124 is at the top of the stack of memory array 120, as indicated by pointer 150. Pointer 150 points to the top of memory array 120. Pointer 150 can cooperate with registers to indicate which memory address is to be accessed during operation in CPU 100.

The memory address 124 is stored in the register 11
Like 0, it can be divided into two sections. Least significant byte section (ie, lower memory value)
Can be used to specify bits 0-7 of memory address 124. The most significant byte section (ie, the upper memory value) is at memory address 1
24 can be used to specify bits 8-15. When placed together, the upper and lower memory values form a 16-bit word at memory address 124. As shown in FIG.
Has word 1 stored in its register. Memory addresses 128, 132, and 136 also have upper and lower memory values indicating the most significant byte and least significant byte in each register. For example, memory address 1
28 can store a 16-bit word 2;
Address 132 can store 16-bit word 3, and memory address 136 can store 16-bit word 4. The memory address 142 indicates the Nth 16-bit word stored in the memory array 120. This N-th 16-bit word has a lower memory value of 13
8 and an upper memory value 140.

When CPU 100 issues an instruction to retrieve data from memory array 120, pointer 150 becomes
Adjust itself to the top of the memory array 120. CPU1
The instructions from 00 can indicate the memory address (ie, storage location) of the desired data. Offset 152 from pointer 150 can be used to indicate a memory address and then a 16-bit word to be read from memory array 120. Offset 152 includes an index value that is twice the offset value provided by CPU 100. Alternatively, the CPU 100 can issue an index value that is used to determine the offset 152. In one embodiment, these index values are used to indicate the upper and lower memory values of the memory address. For example,
At memory address 124, the lower memory value designating bits 0-7 has an index value of "0".
The upper memory value of the memory address 124 has an index value of “1”. Therefore, memory address 1
The 24 bits 8 to 15 have an index value of “1”. Further, 16-bit word 1 includes a lower memory value having an index value of “0” and an upper memory value having an index value of “1”. Offset 152 to indicate the offset required to read the 16-bit word.
Can be determined by dividing the index value by “2”. The 16-bit word contains an upper or lower memory value that correlates with the index value. For example, CP
If the data requested by U100 has an index value of "0", then offset 152 is equal to the value of "0" divided by "2" (ie, "0"). Thus, pointer 150 is separated from the 16-bit word by "0" (ie, points to memory address 124). When an index value of “1” is received,
Offset 152 is again "0", indicating memory address 124. The index value of “2” is “1”
, Which indicates that the desired data is "1" away from pointer 150 (i.e., pointing to memory address 128). If the index value is odd and becomes a fraction with respect to the offset 152, the fraction is rounded down and the offset 1
52 may be rounded to the next integer less by "1". In one embodiment, the lower memory value of the memory address has an even index value and the upper memory value of the memory address has an odd index value. Therefore, the memory
At address 142, the lower memory value 138 has an even index value and the upper memory value 140 has an odd index value. Offset 1 from pointer 150
52 indicates the Nth 16-bit word of memory array 120. The index value in memory address 142 is divided by "2" to determine offset 152.

As shown by arrow 160, data can move between memory array 120 and register 110 during operation in CPU 100. For operations in the CPU 100, such as running software, data is extracted from the memory array at a location indicated by the offset 152 and the pointer 150, and the register 11
Would be commanded to be moved to zero. In particular, a user may write a software function to retrieve data from memory array 120 to register 110 for use in a software routine. In one embodiment, an index value that indicates an 8-bit word (ie, a byte value) in memory array 120 is stored in register 110.
Can be used to retrieve the 8-bit word stored in.
This byte value can be stored in either the most significant byte 112 or the least significant byte 114. The index value received with the instruction indicates that the upper or lower memory value at the specified memory address is to be retrieved. As shown at offset 152, these instructions treat the index value from pointer 150 as a byte offset value rather than a 16-bit offset value. If necessary, other instructions from CPU 100 can use offset 152 to indicate a 16-bit offset.

Referring to FIG. 2, a method for packing data on a CPU according to the present invention is disclosed. By packing the data, CPU 100 retrieves the 8-bit word and combines the 8-bit word with other data to form a 16-bit word. In one embodiment, an instruction to retrieve byte-size data from memory array 120 is received from CPU 100. The byte size data (ie, byte value) is stored in a memory address (eg, memory address 12) in memory array 120.
4). Memory array 120 may include a 16-bit word or, alternatively, two 8-bit words (ie,
16-bit register containing two byte-size words). Therefore, according to the present invention, the memory array 1
The 8-bit word in 20 can be packed into register 110.

In step 210, the packing instruction is C
It is received from the PU 100. This instruction can have a specified memory address in memory array 120. At step 212, the memory address received in the instruction from CPU 100 is used to determine an index value for pointer 150. This index value is used to identify a memory address from which data for packing operation is read. The offset 152 from the pointer 150 is equal to the index value divided by "2", as disclosed in FIG. Upon finding the specified memory address, step 214 determines whether the index value is even or odd. As disclosed in step 216, the odd index value indicates that the upper memory value of the specified register is fetched from memory array 120.
The high memory value is equal to bits 8-15 of the register specified in step 210 (ie, the most significant byte). If the index value is even, step 218
, The lower memory value of the specified register is retrieved from the memory array 120. The lower memory value is equal to bits 0-7 of the designated register (ie, the least significant byte), as indicated by the packing instruction from step 210. Thus, changes can be made to the 16-bit word address bytes retrieved from memory array 120. This change is caused by the opposing byte of the fetched 16-bit word.
"Read-out" executed so that the contents of e) are not changed
Corresponds to a "modify-write" operation. In addition, pointer 150 will still have one such as memory address 124.
"C" because it points to a 6-bit memory address
The compiler can use the above modes.

When the appropriate byte value is retrieved from memory array 120, register 110 (most significant byte 112)
Alternatively, this byte value can be moved to the least significant byte 114). In step 220, a determination is made as to where the retrieved byte value is stored in register 110. In step 210, the CPU 1
The instruction received from 00 may include the location where the byte value will be stored. If the instruction indicates that the byte value is stored in the most significant byte 112,
Step 222 is performed. Step 222 stores this byte value in bits 8-15 of register 110. Step 224 determines whether bits 0-7 of register 110
Indicate that the least significant byte 114 composed of If the byte value is stored in the least significant byte 114, step 226 is performed. Step 22
6 stores a byte value in bits 0 to 7 of the register 110.

In step 228, bits 8 to 15 constituting the most significant byte 112 of the register 110 are set to "0". Therefore, the byte value of the register 110 is treated as an unsigned value. According to the present invention, a special sign extension instruction (specialsign extension instru
ction: “SXTB”) to convert this byte value to a signed byte value. Therefore,
This operation allows byte values to be officially treated as signed or unsigned values. However, when the most significant byte 112 is loaded with a byte value, as disclosed in step 224, the least significant byte 114 remains unchanged.

When the byte value has been stored in the register 110, step 230 returns control to the CPU 100.
The byte value retrieved from step 216 or step 218 can be used in CPU 100 operations such as executing a software command.

For example, CPU 100 issues an instruction to take out a byte value from memory array 120 and store it in register 110. This byte value has an index value of "5". Therefore, the desired byte value also has an offset 152 of "2". Using the offset 152 from the pointer 150 stores the desired byte value 16
Memory address 132 is indicated as a bit word. Since this byte value has an index of "5",
Bits 8-15 of memory address 132 are read, and the byte value is derived from these 8 bits. C
The instruction from PU 100 further indicates that the byte value is stored in least significant byte 114 of register 110. Therefore, bits 8 to of memory address 132
Fifteen 8-bit words are written to the least significant byte 114. This time, bits 8-15 of register 132 include bits 0-7 of register 110.

Referring to FIG. 3, the CPU 1 according to the present invention
A method for unpacking data on 00 is disclosed. By unpacking the data, the CPU 10
A 0 separates the byte value from the 16-bit word of register 110 and stores it in memory array 120. In one embodiment, an unpacking instruction is received from CPU 100. The unpacking operation is performed to perform the inverse operation of packing. In step 312, register 110 is designated as the register from which the byte value is read. In step 314, it is determined from the instruction received in step 310 whether the most significant byte 112 or the least significant byte 114 is to be read from the register 110. If the most significant byte 112 is indicated in step 314, step 316 is executed. In step 316, a byte value is extracted from bits 8 to 15 forming the most significant byte 112 of the register 110. If step 314 indicates that the least significant byte 114 is to be read, step 318 is performed. In step 318, a byte value is extracted from bits 0 to 7 constituting the least significant byte 114 of the register 110. Therefore, this byte value is stored in register 110
Is the byte size word read from.

In step 320, the index value of the byte value determines whether the byte value is stored in a register of memory array 120 as an upper memory value or a lower memory value. The index value is also translated to offset 152 to indicate the memory address where the byte value is stored. Step 320 determines whether the index value is even or odd. If the index value is odd, step 322 is executed. In step 322, a byte value is stored in bits 8 to 15 of the memory address in the memory array 120. In step 324, bits 0-7 of the memory address are not changed. Thus, an odd index value indicates that the byte value read in step 316 or step 318 is stored in the most significant byte section of the specified memory address.

If the index value is an even number in step 320, step 326 is executed. Step 32
6 stores a byte value in bits 0 to 7 constituting the least significant byte of the specified address. In step 328, bits 8-15 of the specified address are not changed. Therefore, the even index value is calculated in step 3
16 or the byte value read in step 318 is
Indicates to be stored in the least significant byte section of the specified memory address. Also, this byte value can be combined with the 16-bit word at the specified address without changing the opposite 8 bits of the specified address. Moreover, the other bytes of the specified address have different index values than the stored byte values. In step 330, the 16-bit word is stored at the specified address, as indicated by pointer 150 and the index value divided by "2" (ie, offset 152). In step 332, control returns to CPU100.

For example, CPU 100 stores
Issue an instruction to move a byte value from 0 to a memory address in memory array 120. This instruction indicates that the byte value is to be read from the most significant byte 112. Therefore, the byte value is equal to bits 8 to 15 of the register 110 of the CPU 100. This byte value is then stored in the memory array 120 at the location specified by the index value. If this byte value has an index value of "6", this byte value is "3"
Has an offset 152 of Offset 15
2 is three addresses away from pointer 150. That is, the pointer points to memory address 136.
Pointing to. The index value of even "6" is
This indicates that the least significant byte memory at memory address 136 stores this byte value. For this reason,
This byte value is stored in bits 0-7. Thus, bits 8-15 of register 110 are stored in bits 0-7 of memory address 136 according to the disclosed method.

Thus, it is apparent that there has been provided, in accordance with the present invention, an apparatus and method for packing and unpacking data on a central processing unit that satisfies the advantages set forth above. While the invention has been described in detail, it should be understood that various changes, substitutions, and modifications can be made therein. For example, while the data words are described as being 8-bit words and 16-bit words, the data words processed may have different bit sizes. Many other embodiments are readily ascertainable by one skilled in the art and may be made without departing from the spirit and scope of the invention as defined by the appended claims.

With respect to the above description, the following items are further disclosed. (1) A method of packing and unpacking data on a central processing unit, wherein a memory address in a memory array is specified using a pointer and an index value, wherein the memory address is an upper memory value and Having a lower memory value, and extracting a byte value from the memory address, wherein the byte value is read from the upper memory value if the index value is odd, and If even, read from the lower memory value; write the byte value to a register; read the byte value from the register; if the index value is odd, the upper memory value The byte value is stored in the lower byte if the index value is even. Comprising storing said byte value to re values, the method.

(2) The method of claim 1, wherein said register further comprises a most significant byte and a least significant byte. 3. The method of claim 2, wherein said writing step further comprises writing said byte value to said most significant byte. 4. The method of claim 2, wherein said writing step further comprises storing said byte value in said least significant byte. 5. The method of claim 4, wherein said writing step further comprises setting said most significant byte equal to zero. 6. The method of claim 2, wherein said reading step further comprises reading said byte value from said most significant byte. (7) the reading step further includes reading the byte value from the least significant byte of the register;
3. The method according to claim 2. (8) The method of claim 1, wherein said memory address is a 16-bit register. (9) The method of claim 1, wherein said byte value is an 8-bit word. (10) the register is a 16-bit register;
The method of claim 1. 11. The method of claim 2, wherein said most significant byte and said least significant byte comprise an 8-bit word. 12. The method of claim 5, wherein the writing step further comprises receiving a special sign extension instruction such that a byte value stored in the least significant byte of the register is converted to a signed byte value. Method.

(13) An apparatus for packing and unpacking data on a central processing unit, wherein the memory array has a plurality of memory addresses, and a pointer and an index value designate a memory address of the memory array. A memory array in which the memory address includes an upper memory value and a lower memory value; and a memory array read from the upper memory value if the index value is odd, and the lower memory if the index value is even. A register having a byte value read from the value, a most significant byte and a least significant byte, wherein when instructed by the central processing unit, the byte value is stored in the most significant byte;
A register that, when commanded by the central processing unit, stores the byte value in the least significant byte; a packing instruction that retrieves the byte value from the memory address and writes the byte value into the register; An unpacking instruction for reading the byte value from the memory address to the memory address.

(14) A method of processing data on a central processing unit, wherein a memory address having an upper memory value and a lower memory value of a memory array is designated using a pointer and an index value, and the index value is If the odd value is read from the upper memory value, and if the index value is even, the byte value read from the lower memory value is extracted from the memory address.
Executing a packing instruction to write the byte value to a register; reading the byte value from the register; writing the byte value to the upper memory value if the index value is odd; Executing an unpacking instruction that stores the byte value at the memory address by writing the byte value to the lower memory value. 15. The method of claim 14, wherein said register comprises a most significant byte and a least significant byte, and wherein said byte value is stored in said most significant byte or said least significant byte.

(16) An apparatus for processing data on a central processing unit, comprising: a memory array having a plurality of memory addresses; and an upper memory value and a lower memory indicated by a pointer and an index value in the memory array. A memory address having a value, a register having a most significant byte and a least significant byte, and the upper memory value if the index value is odd, and the lower memory value if the index value is even. A packing instruction for retrieving a byte value from said memory address equal to and storing said byte value in said most significant byte or said least significant byte; and said byte value read from said most significant byte or said least significant byte From the register, and when the index value is odd, the upper In memory value, anda unpacking instruction for storing the byte value in the memory address in the lower memory value when the byte value is an even number, device.

(17) An apparatus for packing and unpacking data on a central processing unit (100) is disclosed. The apparatus includes a memory array having a plurality of memory addresses. In the memory array (120), the pointer (150) and the index value specify a memory address (142) having an upper memory value (140) and a lower memory value (138). The byte value is read from the upper memory value (140) when the index value is odd, and is read from the lower memory value (138) when the index value is even. The byte value is stored in a register (110) having a most significant byte (112) and a least significant byte (114). The apparatus further includes a packing instruction for reading a byte value from the memory address (142) and saving the byte value to the register (110). The apparatus further includes an unpacking instruction that reads a byte value from the register (110) to the memory address (142). In addition, the central processing unit (1
00), a method for packing and unpacking data is disclosed. The method includes pointing to a memory address (142) of the memory array (120) using the pointer (150) and the index value. memory·
The address (142) has an upper memory value (140) and a lower memory value (138). The method further includes retrieving a byte value from the memory address (142). The byte value is read from the upper memory value (140) when the index value is odd, and is read from the lower memory value (138) when the index value is even. The method further includes writing a byte value to the register (110). The method further includes reading a byte value from the register (110). The method further includes storing the byte value in the upper memory value (140) if the index value is odd and storing the byte value in the lower memory value (138) if the index value is even.

[Brief description of the drawings]

FIG. 1 is a simplified block diagram of a memory array and registers for use with a CPU according to one embodiment of the present invention.

FIG. 2 is a flowchart of a method for packing data on a CPU according to one embodiment of the present invention.

FIG. 3 is a flowchart of a method for unpacking data on a CPU according to one embodiment of the present invention.

[Explanation of symbols]

 0, 1, 2, 3 16-bit word 100 Central processing unit 110 Register 112 Most significant byte (MSB) 114 Least significant byte (LSB) 120 Memory array 124, 128, 132, 136 Memory address 138 Lower memory value 140 Upper memory Value 142 Nth memory address 150 Pointer 152 Offset 160 Arrow indicating data transfer path

Claims (2)

[Claims] 1. A method of packing and unpacking data on a central processing unit, the method comprising: specifying a memory address in a memory array using a pointer and an index value, wherein the memory address is a higher memory. Retrieving a byte value from the memory address, the byte value being read from the upper memory value if the index value is odd; If the value is even, read from the lower memory value; writing the byte value to a register; reading the byte value from the register; if the index value is odd, the higher value Store the byte value in the memory value, and if the index value is even, Comprising storing said byte value into serial low memory value, the method. 2. An apparatus for packing and unpacking data on a central processing unit, comprising: a memory array having a plurality of memory addresses;
A pointer and an index value specifying a memory address of the memory array, the memory address including an upper memory value and a lower memory value, and reading from the upper memory value if the index value is odd. A byte value read from the lower memory value if the index value is an even number, and a register having a most significant byte and a least significant byte. A register stored in the most significant byte and where the byte value is stored in the least significant byte when instructed by the central processing unit; fetching the byte value from the memory address and storing the byte value in the register A packing instruction to write the byte value from the register to the memory address. An unpacking instruction to read.