JP2000029431A - Method and device for driving plasma display - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a driving device of plasma display in which a display panel is stably driven without a malfunction even though the spacing between discharging cells is made narrower, and a high quality video is displayed. SOLUTION: A detecting circuit 4 detects the light emitting pixel ratio of one screen from R, G and B digital data of A/D converting circuits 1, 2 and 3 and inputs the ratio into a control pulse power supply 5 as a signal Vcont. The power supply 5 reduces the subfield reset voltage to a lower level for the low ratio picture and increases the voltage to a higher level for the high ratio picture in accordance with the light emitting pixel ratio. A signal processing circuit 7 executes the process required for the display against the R, G and B digital signals from the circuits 1, 2 and 3. A driving circuit 8 inserts control pulses, that are required for a display, into the signals from the circuit 7 from the power supply 5 and converts the signals into the voltage to turn on plasma display panel 9. Thus, even though the spacing between discharging cells is made narrower, the generation of bright spots on a dark screen is prevented, a reset discharge is surely executed on a bright screen, no malfunction occurs and the panel 9 is stably driven.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method and an apparatus for driving a plasma display, and more particularly to a method and an apparatus for driving a control voltage for controlling discharge of a discharge cell in a plasma display.

[0002]

2. Description of the Related Art In recent years, a conventional cathode ray tube (CRT)
In place of the display device, a flat panel display device that is thin and lightweight, has little screen distortion, and is hardly affected by terrestrial magnetism, and is sealed with liquid crystal or plasma is becoming widespread.

[0003] Among them, a plasma display device, which is a self-luminous type, has a wider viewing angle, and is relatively easy to produce a large panel, has attracted attention as a next-generation color image display device.

[0004] In such a plasma display device, as shown in FIG.
0 are two-dimensionally arranged corresponding to the horizontal and vertical resolutions. Further, one pixel 900 includes a red (R) discharge cell 901, a green (G) discharge cell 902, and a blue (B)
And discharge cells 903, and a color display is realized by controlling the amount of light emitted from each of the discharge cells 901, 902, and 903.

Next, FIG. 10 shows an outline of an electrode structure of each discharge cell of a general three-electrode AC plasma display.
In FIG. 10, reference numerals 901, 902, and 903 denote red (R), green (G), and 901 respectively. Blue (B) discharge cell, 91
0 is a common sustain electrode, 911 is an independent sustain electrode independent for each line, and 907, 908 and 909 are address electrodes.

In order to cause the discharge cells 910, 902, and 903 to emit light, an environment where discharge is easily generated in the discharge cells by an address discharge between the address electrodes 907, 908, and 909 and the independent sustain electrode 911 is formed. A sustain pulse is applied between the common sustain electrode 910 and the independent sustain electrode 911. Thus, the cell specified by the address discharge during the address control period is discharged.

The phosphors 904, 905 and 906 applied in the cells emit light by the ultraviolet rays generated by the discharge,
R, G, and B light emission is performed. Note that this light emission intensity is almost proportional to the number of sustain pulses.

In a plasma display device,
A so-called subfield method is employed as a method of controlling the light emission amount of each of the R, G, and B discharge cells to display an intermediate gradation. In this subfield method, as shown in FIG. 11, one field is divided into a plurality of subfields on a time axis, and a unique emission weight is assigned to each subfield, and the presence or absence of light emission in each subfield is controlled. Thus, the gradation of the luminance is expressed.

FIG. 11 shows an example in which one field is divided into six subfields SF0 to SF5. Then, in the example shown in FIG. 11, in the subfield SF0 at the head of the field, an entire reset period 90a in which all the discharge cells are unconditionally subjected to the reset discharge, and an address period 92a following this period 90a. , And a sustain period 93a.

In subfields SF1 to SF5 other than subfield SF0, SF reset periods 91b to 91f in which only the discharge cells emitted in the previous subfield are selectively reset-discharged, address periods 92b to 92f, and sustain periods 93b to 93f. It is composed of

In subfields SF0 to SF5,
The respective sustain periods 93a, 93b, 93c, 9
The ratio of the luminance emitted in 3d, 93e, and 93f is 1:
The number of sustain pulses is set so as to be 2: 4: 8: 16: 32. Then, the combination of the number of pulses in these subfields causes the subfield SF0
To SF5 from which no light emission occurs in any of the subfields SF5 to SF5 to gradation "63" (= 1 + 2 + 4 + 8 + 16 + 32) in which all the six subfields SF0 to SF5 emit light.
The gradation can be expressed.

The subfield reset periods 91b to 91f provided in these subfields SF1 to SF5
In this case, only the discharge cells that emit light in the previous subfield are selectively subjected to reset discharge and initialized, so that light emission due to unnecessary reset discharge can be suppressed and a high-contrast display can be performed.

A driving method using a combination of the above two types of reset discharge, ie, the entire reset period and the subfield reset period, is disclosed in, for example, Japanese Patent Application Laid-Open No. 8-27876.
No. 6 and JP-A-10-3281 have detailed descriptions.

[0014]

However, if the voltage value of the subfield reset pulse for initializing the discharge cell is high, discharge occurs only at the rising portion of the reset pulse, and wall charges are formed. I will. When such wall charges are formed, even in a discharge cell that does not perform an address discharge, light emission is generated by a sustain pulse, and a bright spot is generated in a region of an originally black image, thereby deteriorating the image quality.

When the voltage value of the reset pulse is high,
Leakage of electric charges in the vicinity of the discharge cell that emits light easily causes discharge at the rising portion of the reset pulse, so that erroneous light emission is likely to occur, and bleeding occurs at edges and lines, thereby significantly deteriorating image quality. .

Conversely, if the voltage value of the subfield reset pulse is set low, there is a problem that the reset discharge is not performed correctly and malfunctions even when the immediately preceding subfield is turned on.

In general, the above-described problem is avoided by setting the voltage of the subfield reset pulse to a voltage value at which a desired reset operation can be performed without causing bright spots or line bleeding in a black region. It is possible.

However, if the distance between the discharge cells is made smaller in order to increase the definition and resolution of the display panel, the display panel is susceptible to the leakage of charges from the adjacent discharge cells. As a result, bleeding easily occurs at the edge portion and the line. For this reason, in order to prevent the occurrence of bright spots and line bleeding in the black region, it is necessary to set the voltage value of the subfield reset pulse even lower.

On the other hand, in order to perform a desired reset discharge without malfunction, the voltage value of the reset pulse needs to be equal to or higher than a predetermined voltage value. However, there has been a problem that the width of the set voltage that satisfies the condition for performing a desired reset discharge is narrowed, or there is no voltage that satisfies the condition. This makes it difficult to drive the display panel stably without malfunction.

As described above, in a high-definition and high-resolution plasma display device, since it is easily affected by discharge of an adjacent cell, a case where a very small number of cells of the display panel emit light and a case where most of the display panel emit light are used. The discharge environment of each discharge cell greatly changes when the cell emits light.

Therefore, the optimum voltage value of the control pulse is
It varies depending on the number of light emitting cells in the screen, and the operating margin decreases (or there is no margin) when the fixed voltage is set. And high resolution,
It was difficult to improve the image quality.

An object of the present invention is to provide a plasma display capable of stably driving a display panel without malfunction and displaying a high-quality image even when the distance between discharge cells is narrowed. It is an object of the present invention to realize a display driving method and apparatus.

[0023]

In order to achieve the above object, the present invention is configured as follows. (1) In a method for driving a plasma display, which includes a plurality of discharge cells, and displays a video signal by a control pulse for controlling discharge and a drive pulse for causing the discharge cells to emit light, a voltage of the control pulse in accordance with display contents of the video signal Control.

(2) Preferably, in the above (1),
The voltage of the control pulse is controlled based on the number of cells or pixels that emit light at a certain luminance or higher in the screen.

(3) Preferably, in the above (1) or (2), one field image is divided into a plurality of subfields, and the voltage-controlled control pulse is applied to the discharge cells for each of the subfields. Is a subfield reset pulse that initializes

(4) Preferably, in (1) or (2) above, one field image is divided into a plurality of subfields, and the voltage-controlled control pulse is applied to each discharge cell in each of the subfields. Is an address control pulse for controlling the presence or absence of light emission.

(5) Preferably, the above (1),
In (2), (3) or (4), the plasma display is a three-electrode AC type.

(6) In a plasma display driving apparatus comprising a plurality of discharge cells and displaying a video signal by a control pulse for controlling discharge and a driving pulse for causing the discharge cell to emit light, the plasma display driving device responds to display contents of the video signal. And control means for controlling the voltage of the control pulse.

(7) Preferably, in the above (6),
The voltage of the control pulse is controlled based on the number of cells or pixels that emit light at a certain luminance or higher in the screen.

(8) Preferably, in the above (6), one field image is divided into a plurality of subfields, and the voltage-controlled control pulse is used to initialize a discharge cell for each subfield. This is a field reset pulse.

(9) Preferably, in the above (6) or (7), one field image is divided into a plurality of subfields, and the voltage-controlled control pulse is applied to each discharge cell in each of the subfields. Is an address control pulse for controlling the presence or absence of light emission.

(10) Preferably, the above (6),
(7) In (8) or (9), the plasma display is a three-electrode AC type.

If the voltage of the control pulse is controlled in accordance with the display content of the video signal, it is possible to appropriately control the case where only a small number of discharge cells emit light and the case where most of the discharge cells emit light. The image quality can be improved by controlling the display image.

In the case where the black display area is wide and the priming effect from the adjacent discharge cells is small, the address discharge can be reliably performed by increasing the address applied voltage.

[0035]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of a display driving device for a plasma display according to an embodiment of the present invention. In FIG. 1, 1 is an A / D conversion circuit for converting a red (R) signal into digital data, 2 is an A / D conversion circuit for converting a green (G) signal into digital data, and 3 is a blue (B) signal. A to convert to digital data
/ D conversion circuit. 7 is a signal processing circuit,
The signal processing circuit 7 is a circuit that performs processing necessary for display on the R, G, and B digital signals from the A / D conversion circuits 1, 2, and 3.

Reference numeral 8 denotes a driving circuit.
This circuit inserts a control pulse or the like necessary for panel display into a signal from the signal processing circuit 7 and converts the signal into a voltage or a current necessary for lighting the display panel. Reference numeral 9 denotes a display panel using a plasma display;
Is a detection circuit for detecting a light emission ratio of a video signal based on R, G, B digital data from the A / D conversion circuits 1, 2, and 3. Reference numeral 5 denotes a control pulse power supply for determining voltage values of various control pulses inserted in the drive circuit 8, and reference numeral 6 denotes a drive power supply for supplying a sustain pulse to the display panel 9.

From the R, G, and B digital data, the detection circuit 4 determines whether the display image is an image containing a large amount of black level, a signal in which line blur is conspicuous, or pixels having a certain luminance or more emit light over a wide range. Then, a light-emitting pixel ratio (described later) indicating whether the pattern is a target pattern is detected.

The luminous pixel ratio detected by the detection circuit 4 is
The signal Vcont is input to the control pulse power supply 5, and the control pulse power supply 5 controls the voltage value of the control pulse according to the light emitting pixel ratio. That is, the control pulse power supply 5 controls the subfield reset voltage to be low in an image having a small number of light emitting cells and a low light emitting pixel ratio, and to be high in an image having a high light emitting pixel ratio.

The control pulse power supply 5 sets a high address voltage for an image having a small number of light emitting cells and a low light emitting pixel ratio, and sets a low address voltage for an image having a high light emitting pixel ratio.

With the above-described configuration, it is possible to set the control pulses such as the subfield reset and the address to the optimum voltage in accordance with the ratio of the light emitting pixels of the display image, thereby performing a stable display with less malfunction. be able to.

In the plasma display, the main light emission of the panel is performed by applying a sustain pulse, and thus the power consumption by the sustain pulse is the largest. For this reason, the drive power supply 6 for generating the sustain pulse is also a circuit corresponding to high power.

On the other hand, the control pulse power supply 5 is a power supply for generating control pulses other than sustain pulses such as full reset, subfield reset, address, etc. Circuit. In the display driving device of the present invention, since the power supply voltage of the control pulse power supply 5 with low power consumption is controlled, it is not necessary to control a large power supply control element, and a stable and high image quality display is achieved by adding a small and simple circuit. It can be performed.

In a general three-electrode AC system as a plasma display system, a relatively high voltage signal is applied to a sustain electrode, and a low voltage is applied to an address electrode. Therefore, a sustain pulse that contributes to light emission can be supplied from the drive power supply 6 to the sustain electrode, and the address voltage can be supplied independently from the control pulse power supply 5 to the address electrode.

Also, a subfield reset pulse,
By superimposing and adding the voltage from the control pulse power supply 5 to the voltage of the sustain pulse from the drive power supply 6, the control pulse power supply 5 can be clearly separated as a lower voltage and lower power supply for all the reset pulses. As described above, in the three-electrode AC type plasma display, the advantage of the present invention of controlling the voltage of the control pulse power supply 5 of small size and small power becomes remarkable.

When an image having a large number of illuminated cells and a high ratio of light-emitting pixels is displayed, the power consumption of the sustain pulse for light emission is increased. The power consumption of the circuit 8 can be reduced, and the power consumption of the entire display driving device can be reduced.

Further, in the configuration example shown in FIG. 1, the digital data immediately after A / D conversion is inputted to the detection circuit 4, and the digital data corresponding to the processing delay in the signal processing circuit 7 is time-dependent. , It is possible to detect the ratio of the light-emitting pixels in advance. For this reason, the processing delay time in the signal processing circuit 7 can be assigned to the time delay associated with the averaging of the detection signal and the control pulse power supply control.

Therefore, even when the image content changes suddenly, the control pulse voltage can be quickly changed to the optimum value. Further, the configuration may be such that a light emitting pixel ratio is detected from an analog signal before A / D conversion.

In the configuration example shown in FIG. 1, both the subfield reset voltage and the address voltage are controlled.
The other may be a fixed voltage.

The voltage of the control pulse, which is not limited to the sub-field reset voltage and the address voltage, changes depending on the number of lighting cells and the discharge voltage changes depending on the number of lit cells, and the optimal voltage fluctuates accordingly, is controlled by the light emitting pixel ratio. The configuration conforms to the gist of the present invention.

Hereinafter, the details of the specific operation will be described. For simplicity, a method and apparatus for controlling only the subfield reset voltage based on the content of the image to be displayed will be described.

A driving signal waveform of the display driving device according to the embodiment of the present invention will be described with reference to FIGS.
FIG. 2 shows an outline of the signal waveform of the first subfield SF0 located at the head of one field, and is composed of three periods: an entire reset period 90a, an address period 92a, and a sustain period 93a.

In the entire reset period 90a, the time width is 10 μm.
All reset pulses Rpm of about s are applied from the common sustain electrode. This reset pulse Rpm has a fixed voltage VR = 340 V, and discharge occurs between the common sustain electrode and the independent sustain electrode. A large amount of wall charge is accumulated between the sustain electrodes due to the discharge at the rise of the previous reset pulse Rpm, but self-erase discharge occurs due to the wall charge between the sustain electrodes at the fall of all the reset pulses Rpm, and the wall charge is reduced. Reset.

A voltage is also applied to the address electrode in accordance with the total reset pulse Rpm, but this is an auxiliary for preventing discharge between the common sustain electrode and the address electrode.

In the address period 92a, a scan pulse Scp is sequentially applied to the independent sustain electrodes, and a line scan is performed. During this line scanning, the scan pulse Scp
By applying the address pulse Adp to the line to which is applied, a discharge occurs between the address electrode and the independent sustain electrode. This discharge triggers a transition to a discharge between the independent sustaining electrode and the common sustaining electrode, thereby forming wall charges. By repeating the above operation and performing line scanning, wall charges are formed in desired cells in the display panel.

In the sustain period 93a following the address period 92a, the sustain pulse Sup is alternately applied to the common sustain electrode and the independent sustain electrode, and the address period 92a is applied.
The sustain discharge is performed only in the cell in which the wall charge is formed in a.

The second subfield SF1 to the sixth subfield S following the first subfield SF0 shown in FIG.
In the subfield F5, a subfield reset period 91b is provided instead of the entire reset period 90a. FIG. 3 shows the configuration of the second subfield period SF1 as an example. As shown in FIG. 3, the second sub-field SF1 includes an SF (sub-field) reset period 91.
b, an address period 92b, and a sustain period 93b.

In the subfield reset period 91b,
Subfield reset pulse Rp having a time width of about 1 μs
s is applied from a common sustain electrode. Since the reset pulse Rps has a shorter time width of 1 μs than the entire reset pulse Rpm, it is not possible to discharge all cells unconditionally, and the sustain discharge is performed in the immediately preceding subfield, and only the cells are discharged. Discharge occurs.

This is because in the cells lit in the previous subfield, the wall charges and the like generated by the sustain discharge remain, so that the discharge is performed at high speed with the application of the voltage, but the cells were not lit in the previous subfield. In the cell, it takes time from the charge separation to the discharge.
This is based on the fact that discharge does not start with a pulse of about s.

The subfield reset period 91b
The configuration of the subsequent address period 92b and sustain period 93b is the same as the configuration of the first subfield SF0 shown in FIG. Further, the number of repetitions of the sustain pulse for realizing the respective light emission weights in the subsequent subfields SF2 to SF5 is different in each subfield, but is realized by the same configuration as the first subfield SF0. .

As described above, by selectively performing the reset discharge by the subfield reset pulse Rps, it is possible to prevent the floating of black caused by unnecessary reset discharge and to perform a high quality display.

However, when the interval between discharge cells is narrowed to realize a high-definition, high-resolution display panel, the rise of the subfield reset pulse Rps is caused by the leakage of space charges from neighboring light emitting cells. In some cases, a weak discharge is generated in the portion, and wall charges are formed. Unlike the correct reset operation, since the wall charges are not reset by the self-erasing discharge, a subfield that does not originally emit light emits due to the remaining wall charges.

When such erroneous light emission occurs, bright spots on a black screen and line bleeding occur, resulting in remarkable image quality deterioration. This erroneous light emission is caused by the subfield reset pulse Rps
Can be avoided by lowering the voltage VRS of
If the voltage of RS is lowered, the original reset discharge cannot be performed correctly, which causes a malfunction.

In the display driving method and apparatus according to the present invention, the voltage VRS of the subfield reset pulse Rps is changed according to the content of the display signal. That is,
The voltage VRS of the subfield reset pulse Rps is lowered for an image with a small number of light emitting pixels where bright spots or line bleeding are conspicuous, and the voltage VRS of the subfield reset pulse Rps is increased for an image with a large number of light emitting pixels. By doing so, malfunction is prevented, and stable and high-quality display is performed.

Specific Subfield Reset Pulse R
FIG. 4 shows an example of the control characteristic of the voltage VRS of ps. FIG.
Indicates the ratio of the number of cells that emit light at a specific luminance or higher among all the discharge cells of one screen on the horizontal axis, and the subfield reset pulse voltage VRS on the vertical axis.
Is shown in the figure. And
An emission pixel ratio of 0% indicates an all black screen, and an emission pixel ratio of 1
00% indicates all white.

As shown in FIG. 4, in the case of the all-white display in which all the discharge cells are turned on, the subfield reset pulse voltage VRS is set to 290 V, and in the case of the all-black display in which all the discharge cells are turned off. Is set so that the subfield reset pulse voltage VRS = 250V. Then, as the light-emitting pixel ratio changes from 0% to 100%, the sub-field reset pulse voltage VRS is increased to 250%.
It is controlled to have a linear characteristic such that the voltage rises at an inclination from V and becomes 290 V. As described above, by controlling the subfield reset pulse voltage VRS in accordance with the light emitting pixel ratio, it is possible to prevent bright spots on a black screen and line bleeding, and to accurately perform reset discharge, thereby achieving high-quality display. Can be realized.

Next, a specific configuration of the detection circuit 4 shown in FIG. 1 will be described with reference to FIG. In FIG. 5, 401,
402 and 403 are two-input OR circuits for performing a logical sum operation,
04 is a 3-input OR circuit, 405 is a resistor, and 406 is a capacitor. The input of the OR circuit 401 receives a signal R7 of the most significant bit of the R signal converted into a digital signal and a signal R6 of the next weight.

The input of the OR circuit 402 includes a signal G7 of the most significant bit of the G signal converted into a digital signal.
And the next weight signal G6. Further, to the input of the OR circuit 403, a signal B7 of the most significant bit of the B signal converted into a digital signal and a signal B6 of the next weight are input.

The output signals of the OR circuits 401, 402 and 403 are further input to a three-input OR circuit 404,
An OR operation is performed in the R circuit 404. OR circuit 404
Is smoothed by a CR integration circuit composed of a resistor 405 and a capacitor 406, and is output as a control signal Vcont.

The signal R7 of the most significant bit when digitally converted into an 8-bit signal from level 0 to 255 is
When the level of the R signal is equal to or higher than 128 levels, the level becomes “H” level. Further, the signal R6 of the next weight becomes "H" level when the level of the R signal is in the range of 64-127 and 192-255.

By performing a logical OR operation on R7 and R6 in the OR circuit 401, a signal which becomes "H" level when the R signal level is 64 or more can be obtained. Similarly,
The output of the OR circuit 402 is a signal which becomes “H” level when the level of the G signal is 64 or more, and the output of the OR circuit 403 is a signal which becomes “H” level when the level of the B signal is 64 or more.

Further, OR circuits 401, 402, 403
Are ORed by the three-input OR circuit 404, so that any one of the R, G, and B signals has a level of 64
In this case, it is possible to obtain a signal that goes to the “H” level.

The above R7, R6, G7, G6, B7, B6
Are sequentially ORed for all pixels in one screen.
Input to the circuits 401, 402, and 403 and the OR circuit 40
By performing a smoothing process on the output signal of No. 4 by the CR integration circuit, a temporal ratio in which any one of the R, G, and B signals in one screen becomes 64 or more can be obtained as a voltage value. Then, this voltage value is output as the control signal Vcont.

The signal indicating the ratio of the luminescent pixels (64 levels or more) in one display screen can be obtained by an analog voltage value by the detection circuit 4 executing the above processing. By setting the time constant of the integration circuit formed by the resistor 405 and the capacitor 406 to 10 to 20 ms, it is possible to output an average light-emitting pixel ratio in one field period. When the output logic level of the OR circuit 404 is 0 V when the output logic level is “L” and 4 V when the output logic level is “H”, Vcont = 0 when the light emitting pixel ratio is 0%.
V, Vcont = 4 V when the light emitting pixel ratio is 100%, and a control voltage almost proportional to the light emitting pixel ratio can be obtained.

Next, the control of the control pulse voltage inside the control pulse power supply 5 shown in FIG. 1 will be specifically described.
FIG. 6 is a diagram showing a main part of the subfield reset voltage control circuit of the control pulse power supply 5.

In FIG. 6, 500 is an output control transistor, 501 is an error amplifier, 502 and 503 are resistors having a resistance value ratio of 9: 1, 504 is a voltage adding circuit, 505
Is a reference power supply having a reference voltage of 25V.

The control voltage Vcont from the detection circuit 4 is added to the reference potential 25 V of the reference power supply 505 by the voltage addition circuit 504 and input to the positive input terminal of the error amplification circuit 501. The output signal of the error amplifier 501 is input to the base of the output control transistor 500, and the subfield reset voltage controlled to a predetermined voltage is output from the emitter of the transistor 500.

An unstable voltage of 300 V is applied to the collector of the transistor 500, and the emitter is grounded via the resistors 502 and 503. The subfield reset voltage output from the subfield reset control circuit is connected to the resistors 502 and 503.
, And is input to the negative input terminal of the error amplifier 501.

With such a configuration, the error amplifier 501
Controls the output control transistor 500 so that the potential difference between the positive input and the negative input becomes zero. Therefore, the potential obtained by dividing the subfield reset voltage by one-tenth is always equal to the voltage of the positive input. It works.

That is, feedback control is performed so that the subfield reset voltage has a voltage value which is ten times the positive input voltage of the error amplifier.

The operation of the subfield reset voltage control circuit shown in FIG. 6 will be described below. The light emitting pixel ratio is 0%, and the control voltage Vcont from the detection circuit 4 is 0 V
, The voltage value added by the reference voltage 25 V of the reference power supply 505 and the voltage addition circuit 504 is 25 V,
The output subfield reset voltage is increased by 10 times to 250 V by feedback control.

When the light emitting pixel ratio is 50%, the control voltage Vcont from the detection circuit 4 becomes about 2 V,
Reference voltage 25V of reference power supply 505 and voltage adding circuit 504
Is approximately 27V. As a result, the output subfield reset voltage is about 270V.

Next, when the light emitting pixel ratio becomes 100%, the control voltage Vcont from the detection circuit 4 becomes 4 V, and the reference voltage 25 V of the reference power supply 505 and the voltage addition circuit 5
The voltage value added in 04 becomes 29V. The output subfield reset voltage is 290V.

With the configuration of the subfield reset voltage control circuit as described above, it is possible to control the SF reset voltage with respect to the emission pixel ratio having the characteristics shown in FIG.

According to the above-described first embodiment of the present invention, the subfield reset pulse voltage is controlled according to the light emission pixel ratio in one screen, and the subfield reset pulse voltage is increased as the light emission ratio increases from 0%. Since the pulse voltage is increased, even if the distance between discharge cells is narrowed, bright spots and line bleeding on dark screens are prevented, and reset discharge on bright screens is prevented. A method and apparatus for driving a plasma display capable of reliably driving the display panel without malfunction and stably driving the display panel and capable of displaying a high-quality image can be realized.

Next, a second embodiment of the present invention will be described. The second embodiment of the present invention is an example in which the control characteristic of the subfield reset voltage VSR with respect to the light emitting pixel ratio is a non-linear characteristic as shown in FIG. In the second embodiment, the configuration other than the subfield reset voltage control circuit is the same as that of the first embodiment, so that illustration and detailed description thereof are omitted.

In FIG. 7, the subfield reset voltage VSR is 25 when the light emitting pixel ratio is 0% to 25%.
When the voltage exceeds 0 V and 25%, the voltage linearly increases with a slope from 250 V, becomes 290 V at 50%, and increases from 50% to 100 V.
% Is controlled to be 290V.

In the second embodiment, the light emission ratio is 0% to
In the case of 25%, it is possible to reliably prevent the occurrence of bright spots and line bleeding in a dark screen, and to execute the reset discharge in a bright screen reliably when the light emission ratio is 50% to 100%. it can.

In the example of FIG. 7, the light emission ratio is 0% to 2%.
At 5%, the subfield reset voltage VSR is set to 2
Although the voltage is set to 50 V, the voltage VSR may be set to 250 V up to other light emission ratios. For example, when the light emission ratio is 0% to 10%, the voltage VSR is 250 V, 10%
Exceeds 250 V, it increases linearly with a slope from 250 V,
It becomes 290V at 0%, and 2 from 50% to 100%.
It is also possible to control so as to be 90V.

The non-linear characteristic of the subfield reset voltage as shown in FIG. 7 can be realized by limiting the amplitude of the positive input voltage of the error amplifier circuit 501 by the amplitude limiting circuit as shown in FIG.

In the amplitude limiting circuit of FIG.
07 is a diode, 508 and 509 are limiting voltage sources for determining a voltage for limiting the amplitude, and V1 and V2 (V1 <V
The voltage of 2) is generated.

The terminal A 'of the amplitude limiting circuit is connected to the diode 5
07, and the cathode of the diode 507 is grounded from the positive electrode of the limited voltage source 509 to the negative electrode. Further, the terminal A ′ of the amplitude limiting circuit is connected to the cathode of the diode 506, and the anode of the diode 506 is grounded from the plus electrode to the minus electrode of the limited voltage source 508. In addition,
For ease of explanation, it is assumed that the diodes 506 and 507 operate ideally.

By connecting the terminal A connected to the positive input terminal of the error amplifier 501 of the subfield reset voltage control circuit shown in FIG. 6 to the terminal A 'of the amplitude limiting circuit shown in FIG. And the voltage source 509 to limit the voltage at the terminal A so as not to be higher than the voltage V2.
Is limited so as not to be lower than the voltage V1.

The specific operations of the subfield reset voltage control circuit and the amplitude limiting circuit are as follows.
The ratio of the resistance values of the resistors 502 and 503 in FIG. 6 is 39: 1.
It is set to be. As a result, the subfield reset voltage, which is the output voltage, is divided into 1/40 by the resistors 502 and 503 and fed back to the negative input terminal of the error amplifier 501. Therefore, a voltage 40 times the positive input voltage of error amplifier 501 is output as the subfield reset voltage.

The reference voltage of the reference voltage source 505 is 5.0.
The amplitude upper limit voltage V2 of the voltage source 509 of the amplitude limiting circuit shown in FIG. 8 is set to 7.25 V, and the amplitude upper limit voltage V1 of the voltage source 508 is set to 6.25 V. Further, the detection circuit 4 shown in FIG.
Shall be output.

The control voltage Vcont takes a value of 0 to 1 V during a period in which the light emitting pixel ratio is 0 to 25%, and the value added by the adding circuit 504 to the voltage of 5.25 V of the reference voltage 505 is 5.2.
5 to 6.25 V, but within this range, the lower limit voltage of the amplitude limiting circuit of FIG. 8 is limited to 6.25 V.

As a result, the ratio of the light emitting pixels is 0 to 25.
In the% period, the potential of the terminal A becomes 6.25 V, the subfield reset voltage becomes 40V, which is 250 V, and this voltage 250 V is output from the subfield reset voltage control circuit.

In the period where the light emitting pixel ratio is 25 to 50%,
The control voltage Vcont becomes a value of 1 V to 2 V, and the addition circuit 50
In step 4, the value added to the reference voltage 505 with the voltage 5.25 V is 6.25 to 7.25 V, which is within the range of the amplitude limit, and 250 (= 6.25 × 40) according to this voltage.
290 (= 7.25 × 40) V is output as the subfield reset voltage.

Further, when the light emitting pixel ratio increases to 50% or more and the control voltage Vcont becomes a value of 2 V or more, the addition circuit 5
In step 04, the voltage added to the voltage 5.25V of the reference voltage source 505 becomes a value of 7.25V or more, so that the voltage is limited to 7.25V.

Therefore, 290 (= 7.25 × 40) V is output in the region where the light emitting pixel ratio is 50% or more.
By the operation as described above, the control characteristic of the subfield reset voltage with respect to the light emitting pixel ratio shown in FIG. 7 can be realized.

By realizing the control characteristic of the subfield reset voltage with respect to the luminous pixel ratio as shown in FIG. 7, in an image having a luminous pixel ratio of about 25% and a wide black display area, the subfield reset voltage is set to 250.
V on a bright screen with a luminous pixel ratio of 50% or more, the subfield reset voltage can be set to the normal 290 V, and malfunctions on a bright screen can be reliably prevented, and bright spots and lines on a dark screen can be blurred. Occurrence can be reliably prevented.

That is, according to the second embodiment, as in the first embodiment, even when the distance between the discharge cells is narrowed, the bright spots and lines on the dark screen are not affected. A method and apparatus for driving a plasma display capable of preventing bleeding, reliably performing reset discharge on a bright screen, stably driving a display panel without malfunction, and displaying a high-quality image. Can be realized.

In the specific examples shown in FIGS. 2 to 8 described above, the subfield reset voltage is controlled in accordance with the light emitting pixel ratio. However, as shown in the example of FIG.
A configuration in which the address voltage is controlled in accordance with the ratio of the light emitting pixels may be employed. In this case, the voltage VA of the address pulse Adp shown in FIGS. 2 and 3 may be controlled.

When the light emitting pixel ratio is small and the priming effect from the peripheral pixels is small, the address voltage VA is set high (for example, 75 V). When the light emitting pixel ratio is large, the address voltage VA is set low (for example, 55 V). ) The setting may be made. With such a configuration, it is possible to optimally control the address discharge, thereby preventing malfunction and saving power.

Further, the address voltage control circuit of the control pulse power supply 5 replaces the adder circuit 504 of the subfield reset voltage control circuit shown in FIG. 6 with a subtraction circuit, and subtracts the control voltage Vcont from the reference voltage source 505. Thus, when the light emitting pixel ratio is low, the control pulse voltage is increased,
When the light emitting pixel ratio is high, the configuration can be such that the control pulse voltage can be controlled to be low.

The range of the voltage to be controlled and the like are determined by the feedback resistors 502, 5 and 5 of the circuit shown in FIG.
03, the reference voltage source 505, and the reference voltage sources 506 and 507 shown in FIG.

It is to be noted that the present invention is not limited to the subfield reset voltage and the address voltage, but may vary depending on the number of light emitting pixels.
It is also possible to adopt a configuration in which the discharge environment changes due to the influence of the adjacent discharge cells and the optimum voltage fluctuates accordingly, and the voltage of the control pulse is controlled by the ratio of the light emitting pixels.

[0107]

Since the present invention is configured as described above, it has the following effects. The subfield reset pulse voltage is controlled in accordance with the light emission pixel ratio in one screen, and when the light emission ratio is high, the subfield reset pulse voltage is increased, so that the interval between the discharge cells is reduced. Even if it does, the occurrence of bright spots and lines on a dark screen is prevented, and a reset discharge is reliably executed on a bright screen without malfunction.
A method and apparatus for driving a plasma display capable of stably driving a display panel and displaying a high-quality image can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a display driving device of a plasma display according to an embodiment of the present invention.

FIG. 2 is a waveform diagram of a drive signal in a first subfield (SF0).

FIG. 3 is a waveform diagram of a drive signal in a second subfield (SF1).

FIG. 4 is a characteristic diagram showing control characteristics of a subfield reset voltage with respect to a light emitting pixel ratio.

FIG. 5 is a block diagram showing a configuration of a detection circuit 4 shown in FIG.

FIG. 6 is a block diagram illustrating a configuration of a voltage control unit of the control pulse power supply illustrated in FIG. 1;

FIG. 7 is a characteristic diagram showing another control characteristic of a subfield reset voltage with respect to a light emitting pixel ratio.

FIG. 8 is a block diagram showing a configuration of an amplitude limiting circuit provided inside a control pulse power supply.

FIG. 9 is an explanatory diagram illustrating pixels and discharge cells of a display panel.

FIG. 10 is an explanatory diagram illustrating electrode arrangement of a discharge cell.

FIG. 11 is an explanatory diagram showing the arrangement of subfields in one field.

[Explanation of symbols]

 1, 2, 3 A / D conversion circuit 4 Detection circuit 5 Control pulse power supply 6 Panel drive power supply 7 Signal processing circuit, 8 Drive circuit 9 Display panel 90a All reset period 91b to 91f Subfield reset period 92a to 92f Address period 93a to 93f Sustain period 401, 402 Two-input OR gate 403 Two-input OR gate 404 Three-input OR gate 405, 502 Resistor 406 Capacitor 500 Output control transistor 501 Error amplifier 503 Resistance 504 Adder circuit 505, 508 Reference voltage source 506, 507 Diode 509 Reference Voltage source 900 Display pixel 901 R discharge cell 902 G discharge cell 903 B discharge cell 904 R phosphor 905 G phosphor 906 B phosphor 907, 908 Address electrode 909 Address electrode 910 Common sustain electrode 11 independent sustain electrodes

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Hiroshi Otaka 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Information Media Business Unit of Hitachi, Ltd. (72) Inventor Takahisa Mizuta Yoshida, Totsuka-ku, Yokohama-shi, Kanagawa No. 292, Hitachi, Ltd. Information Media Business Headquarters, Hitachi, Ltd. (72) Inventor Takeo Masuda 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture F-term, Information Media Business Headquarters, Hitachi, Ltd. DD09 EE29 EE30 FF12 GG12 HH02 HH04 JJ02 JJ03 JJ04 JJ05

Claims (10)

[Claims] 1. A method for driving a plasma display, comprising a plurality of discharge cells and displaying a video signal by a control pulse for controlling discharge and a drive pulse for causing the discharge cells to emit light, comprising the steps of: A method for driving a plasma display, characterized by controlling a voltage of the plasma display. 2. The plasma display driving method according to claim 1, wherein the voltage of the control pulse is controlled based on the number of cells or pixels that emit light at a certain luminance or higher in the screen. Drive method. 3. The method of driving a plasma display according to claim 1, wherein one field image is divided into a plurality of sub-fields, and said voltage-controlled control pulse initializes a discharge cell for each of said sub-fields. A method for driving a plasma display, comprising a subfield reset pulse to be converted. 4. The method of driving a plasma display according to claim 1, wherein one field image is divided into a plurality of subfields, and said voltage-controlled control pulse is emitted from each discharge cell in each of said subfields. A driving method of a plasma display, which is an address control pulse for controlling presence / absence of the pixel. 5. The method of driving a plasma display according to claim 1, wherein the plasma display is a three-electrode AC type. 6. A plasma display driving apparatus comprising a plurality of discharge cells and displaying a video signal by a control pulse for controlling discharge and a driving pulse for causing the discharge cell to emit light, wherein the control pulse is controlled according to the display content of the video signal. A plasma display driving device comprising control means for controlling a voltage of the plasma display. 7. The plasma display driving device according to claim 6, wherein the voltage of the control pulse is controlled based on the number of cells or pixels that emit light at a certain luminance or higher in the screen. Drive. 8. A plasma display driving apparatus according to claim 6, wherein one field image is divided into a plurality of subfields, and said voltage-controlled control pulse is used to initialize a discharge cell for each of said subfields. A plasma display driving device, which is a reset pulse. 9. A plasma display driving device according to claim 6, wherein one field image is divided into a plurality of subfields, and said voltage-controlled control pulse is used to control the light emission of each discharge cell for each of said subfields. A plasma display driving device, which is an address control pulse for controlling presence / absence. 10. The driving device for a plasma display according to claim 6, wherein the plasma display is a three-electrode AC type.