JP2000028394A - Capacitance-type detecting apparatus - Google Patents
Capacitance-type detecting apparatusInfo
- Publication number
- JP2000028394A JP2000028394A JP10200059A JP20005998A JP2000028394A JP 2000028394 A JP2000028394 A JP 2000028394A JP 10200059 A JP10200059 A JP 10200059A JP 20005998 A JP20005998 A JP 20005998A JP 2000028394 A JP2000028394 A JP 2000028394A
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- JP
- Japan
- Prior art keywords
- circuit
- output
- sensor
- signal
- input terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
Landscapes
- Measuring Fluid Pressure (AREA)
- Indication And Recording Devices For Special Purposes And Tariff Metering Devices (AREA)
- Transmission And Conversion Of Sensor Element Output (AREA)
- Measurement Of Current Or Voltage (AREA)
Abstract
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００１】この発明は、外力、圧力、加速度等を検出
する静電容量式ＰＷＭ出力センサを用いた静電容量式検
出装置に関する。The present invention relates to a capacitance type detection device using a capacitance type PWM output sensor for detecting external force, pressure, acceleration and the like.
【０００２】[0002]
【従来の技術】従来のこの種の静電容量式検出装置は図
８に示すように、矩形波発生器６と静電容量式ＰＷＭ出
力センサ８とＰＷＭパルス復調器１０で構成される。静
電容量式ＰＷＭ出力センサ（以下センサと言う）８には
例えばデューティ比５０％の矩形波の駆動信号Ｓ０が印
加される。駆動信号Ｓ０は抵抗器Ｒ１とコンデンサＣ１
より成る第１の時定数回路及び抵抗器Ｒ２とコンデンサ
Ｃ２より成る第２の時定数回路を介してＡＮＤ回路７の
二つの入力端子にそれぞれ与えられる。2. Description of the Related Art As shown in FIG. 8, this type of conventional capacitance-type detection device comprises a rectangular wave generator 6, a capacitance-type PWM output sensor 8, and a PWM pulse demodulator 10. A drive signal S0 of a rectangular wave having a duty ratio of, for example, 50% is applied to a capacitance type PWM output sensor (hereinafter referred to as a sensor) 8. The drive signal S0 includes a resistor R1 and a capacitor C1.
And a second time constant circuit comprising a resistor R2 and a capacitor C2.
【０００３】Ｒ１、Ｃ１の時定数τ１とＲ２、Ｃ２の時
定数τ２とは、例えば標準圧力のとき、τ１＝τ２に設
定されており、これら時定数回路の出力Ｓ１、Ｓ２は例
えば図９Ａに示すような歪んだ波形となる。時定数τ
１，τ２を調整することにより、ＡＮＤ回路７の出力に
は図９Ｂのように、例えばデェーティ比５０％の波形が
得られる。The time constant τ1 of R1 and C1 and the time constant τ2 of R2 and C2 are set to τ1 = τ2 at a standard pressure, for example. The outputs S1 and S2 of these time constant circuits are shown in FIG. The waveform becomes distorted as shown. Time constant τ
By adjusting 1, τ2, a waveform having a duty ratio of, for example, 50% is obtained at the output of the AND circuit 7 as shown in FIG. 9B.
【０００４】コンデンサＣ１，Ｃ２の容量は圧力等によ
って差動的に変化する。例えば圧力が標準値から減少す
ると、その変化に応じて、Ｃ１の容量が減少し、Ｃ２の
容量が増加する。その結果、時定数τ１は減少し、τ２
は増加し、センサ出力Ｓ３のデューティ比は５０％より
減少する。また、圧力が標準値から増加すると、逆にデ
ューティ比は５０％より増加する。[0004] The capacitances of the capacitors C1 and C2 change differentially with pressure or the like. For example, when the pressure decreases from the standard value, the capacity of C1 decreases and the capacity of C2 increases according to the change. As a result, the time constant τ1 decreases and τ2
Increases, and the duty ratio of the sensor output S3 decreases from 50%. When the pressure increases from the standard value, the duty ratio increases more than 50%.
【０００５】次にＰＷＭパルス復調器１０について説明
する。入力端子１１よりの入力ＰＷＭパルスＳ３は排他
的論理和回路より成る振幅可変回路２１の一方の入力端
へ供給され、他方の入力端は接地される。振幅可変回路
２１の出力は平滑フィルタ２２で平滑され、その平滑出
力は比較増幅器２３の非反転入力端へ供給される。基準
電源２４の基準電圧Ｅr がバイアスバランス回路２５を
通じて比較増幅器２３の反転入力端へ印可される。Next, the PWM pulse demodulator 10 will be described. The input PWM pulse S3 from the input terminal 11 is supplied to one input terminal of an amplitude variable circuit 21 composed of an exclusive OR circuit, and the other input terminal is grounded. The output of the amplitude variable circuit 21 is smoothed by a smoothing filter 22, and the smoothed output is supplied to a non-inverting input terminal of a comparison amplifier 23. The reference voltage Er of the reference power supply 24 is applied to the inverting input terminal of the comparison amplifier 23 through the bias balance circuit 25.
【０００６】比較増幅器２３の出力は出力端子１５へ供
給されると共に、差動増幅器２６の反転入力端へ供給さ
れる。差動増幅器２６の非反転入力端に出力基準電圧Ｅ
roが印加される。この差動増幅器２６の反転入力端と直
列に、コンデンサ２８と抵抗素子２９の並列回路が挿入
され、また差動増幅器２６の反転入力端と出力端の間に
抵抗素子３１が接続される。差動増幅器２６、コンデン
サ２８、抵抗素子２９，３１より成る帰還増幅器３３は
高域通過フィルタ（比較増幅器２３と組み合わせた閉ル
ープで低域通過フィルタとなる）としても動作してい
る。差動増幅器２６の出力端は振幅可変回路２１の排他
的論理和回路の動作電源端子に接続されて帰還電圧ＶF
が印加される。The output of the comparison amplifier 23 is supplied to the output terminal 15 and to the inverting input terminal of the differential amplifier 26. The output reference voltage E is applied to the non-inverting input terminal of the differential amplifier 26.
ro is applied. A parallel circuit of a capacitor 28 and a resistance element 29 is inserted in series with the inverting input terminal of the differential amplifier 26, and a resistance element 31 is connected between the inverting input terminal and the output terminal of the differential amplifier 26. The feedback amplifier 33 including the differential amplifier 26, the capacitor 28, and the resistance elements 29 and 31 also operates as a high-pass filter (a low-pass filter in a closed loop combined with the comparison amplifier 23). The output terminal of the differential amplifier 26 is connected to the operation power supply terminal of the exclusive OR circuit of the amplitude variable circuit 21 and receives the feedback voltage V F
Is applied.
【０００７】従って振幅可変回路２１から出力されるパ
ルスは幅が入力ＰＷＭパルスＳ３の幅と一致し、振幅が
帰還電圧ＶF にほぼ等しくなる。入力端子１１よりの入
力ＰＷＭパルスＳ３のデューティ比が５０％で、出力端
子１５の出力電圧Ｖ0 が出力基準電圧Ｅr0、例えば５Ｖ
になるように基準電圧Ｅ r を調整する。Therefore, the output from the amplitude variable circuit 21 is
The width is equal to the width of the input PWM pulse S3, and the amplitude is
Feedback voltage VFIs almost equal to Input from input terminal 11
When the duty ratio of the power PWM pulse S3 is 50% and the output terminal
Output voltage V of child 150Is the output reference voltage Er0, For example, 5V
So that the reference voltage E rTo adjust.
【０００８】ＰＷＭパルスＳ３のデューティ比が５０％
を越えると、平滑フィルタ２２の出力レベルが上がりこ
れに応じて比較増幅器２３の出力Ｖ0 が増加し、その増
加分が差動増幅器２６で反転増幅され、帰還電圧ＶF 、
即ち振幅可変回路２１の電源電圧が減少し、従って、振
幅可変回路２１の出力はパルスの振幅が減少し、平滑フ
ィルタ２２の出力電圧が減少し、出力電圧Ｖ0 が減少す
る。つまり負帰還がかかり、比較増幅器２３の利得は著
しく大きいが、出力電圧Ｖ0 は入力ＰＷＭパルスのパル
ス幅に応じて、出力基準電圧Ｅr0より高いレベルで安定
する。[0008] The duty ratio of the PWM pulse S3 is 50%
, The output level of the smoothing filter 22 rises, and the output V 0 of the comparison amplifier 23 increases accordingly. The increase is inverted and amplified by the differential amplifier 26, and the feedback voltage V F ,
That is, the power supply voltage of the amplitude variable circuit 21 decreases, and accordingly, the amplitude of the pulse output from the amplitude variable circuit 21 decreases, the output voltage of the smoothing filter 22 decreases, and the output voltage V 0 decreases. That is, negative feedback is applied, and the gain of the comparison amplifier 23 is extremely large, but the output voltage V 0 is stabilized at a level higher than the output reference voltage Er 0 according to the pulse width of the input PWM pulse.
【０００９】入力ＰＷＭパルスＳ３のデューティ比が５
０％より下ると同様に動作してパルス幅に応じて、出力
基準電圧Ｅr0より低い出力電圧Ｖ0 が得られる。The duty ratio of the input PWM pulse S3 is 5
Depending on the pulse width operates similarly when down than 0%, the output voltage V 0 is lower than the output reference voltage E r0 obtained.
【００１０】[0010]
【発明が解決しようとする課題】従来の回路では、セン
サ８と復調器１０とが独立しており復調器の利得を大き
くした場合、何等かの原因でセンサ８の出力のノイズ及
びドリフトが大きくなると、これらは復調器１０の比較
増幅器２３で増幅され、出力Ｖ0 の安定性が悪くなると
云う問題があった。In the conventional circuit, when the sensor 8 and the demodulator 10 are independent and the gain of the demodulator is increased, the noise and the drift of the output of the sensor 8 increase for some reason. Then, these are amplified by the comparison amplifier 23 of the demodulator 10 and there is a problem that the stability of the output V 0 is deteriorated.
【００１１】[0011]
【課題を解決するための手段】（１） 請求項１の静電
容量式検出装置は、矩形波発生器と、その矩形波発生器
の出力を時定数回路を通して鋸歯状波に変換し、その鋸
歯状波をしきい値回路に入力して、矩形波発生器の出力
の位相を所定時間（τ３）だけ遅らせた矩形波を出力す
る位相変換回路と、矩形波発生器の出力の周波数を第１
フリップフロップ回路により１／２に分周して第１セン
サ駆動信号を発生すると共に位相変換回路の出力の周波
数を第２フリップフロップ回路により１／２に分周し、
第１センサ駆動信号の位相より前記所定時間（τ３）だ
け遅れた分周出力を第２センサ駆動信号として発生する
同期分周回路と、第１センサ駆動信号を第１直列入力抵
抗（Ｒ１）と第１並列センサ容量（Ｃ１）より成る第１
時定数回路を通して排他的論理和回路（ＥＸＯＲと言
う）の一方の入力端子に加え、第２センサ駆動信号を第
２直列入力抵抗（Ｒ２）と第２並列センサ容量（Ｃ２；
Ｃ１と差動的に変化する）より成る第２時定数回路を通
してＥＸＯＲの他方の入力端子に加え、そのＥＸＯＲ出
力よりＰＷＭ（パルス幅変調）信号を得る静電容量式Ｐ
ＷＭ出力センサと、そのＰＷＭ信号を直流に変換して外
部に出力する検波回路と、検波回路の出力を増幅して、
その増幅した信号を位相変換回路内のしきい値回路に帰
還して、そのしきい値を制御する帰還増幅器とを具備す
るものである。 （２） 請求項２の発明は、前記（１）において、矩形
波発生器の出力を時定数回路を通して鋸歯状波に変換
し、その鋸歯状波をしきい値回路に入力して、矩形波発
生器の出力の位相を所定時間（τ４）だけ遅らせた矩形
波を得、その矩形波を同期分周回路の第１フリップフロ
ップ回路に入力する第２の位相変換回路と、帰還増幅器
の出力の極性を反転して、その極性反転した信号を第２
の位相変換回路内のしきい値回路に帰還してそのしきい
値を制御する極性反転回路と、を追加したものである。 （３） 請求項３の発明は、前記（１）または（２）に
おいて、帰還増幅器または極性反転回路の出力が、位相
変換回路または第２の位相変換回路のしきい値回路の電
源入力端子に与えられているものである。 （４） 請求項４の発明は前記（１）または（２）にお
いて、位相変換回路または第２の位相変換回路のしきい
値回路が片方の入力端子を接地した排他的論理和回路、
または両方の入力端子を互いに接続したＡＮＤ回路また
はＯＲ回路より成るものである。 （５） 請求項５の発明は、前記（１），（２）のいず
れかにおいて、同期分周回路のフリップフロップ回路の
一方及び他方の出力端子が第２フリップ回路の一方及び
他方の入力端子にそれぞれ接続されているものである。 （６） 請求項６の発明は、前記（５）において、第
１、第２フリップフロップ回路がＪＫフリップフロップ
回路とされている。 （７） 請求項７の静電容量式検出装置は、矩形波発生
器と、その矩形波発生器の出力を第１直列入力抵抗（Ｒ
１）と第１並列センサ容量（Ｃ１，Ｃ１’）より成る第
１時定数回路を通して、ＡＮＤ回路またはＯＲ回路より
成るゲート回路の一方の入力端子に加え、矩形波発生器
の出力を第２直列入力抵抗（Ｒ２）と第２並列センサ容
量（Ｃ２，Ｃ２’）より成る第２時定数回路を通してゲ
ート回路の他方の入力端子に加え、そのゲート回路の出
力によりＰＷＭ信号を得る静電容量式ＰＷＭ出力センサ
と、ＰＷＭ出力センサの出力を入力して、その入力信号
の振幅を一定にして出力する振幅固定回路と、その振幅
固定回路の出力を直流に変換して外部に出力する検波回
路と、検波回路の出力を増幅して、その増幅した信号を
ＰＷＭ出力センサの前記ゲート回路の電源入力端子に帰
還して、そのゲート回路のしきい値を制御する帰還増幅
器とを具備するものである。 （８） 請求項８の静電容量式検出装置は、矩形波発生
器と、その矩形波発生器の出力の振幅を可変する振幅可
変回路と、その振幅可変回路の出力を第１直列入力抵抗
（Ｒ１）と第１並列センサ容量（Ｃ１，Ｃ１’）より成
る第１時定数回路を通して、ＡＮＤ回路またはＯＲ回路
より成るゲート回路の一方の入力端子に加え、振幅可変
回路の出力を第２直列入力抵抗（Ｒ２）と第２並列セン
サ容量（Ｃ２，Ｃ２’）より成る第２時定数回路を通し
てゲート回路の他方の入力端子に加え、そのゲート回路
の出力よりＰＷＭ信号を得る静電容量式ＰＷＭ出力セン
サと、そのＰＷＭ出力センサの出力を直流に変換して外
部に出力する検波回路と、その検波回路の出力を増幅し
て、その増幅した信号を振幅可変回路に与えて、その出
力の振幅を制御する帰還増幅器とを具備するものであ
る。 （９） 請求項９の発明は、前記（８）において、振幅
可変回路が両方の入力端子を互いに接続したＡＮＤ回路
またはＯＲ回路より成り、その電源入力端子に帰還増幅
器の出力が与えられているものである。According to a first aspect of the present invention, there is provided an electrostatic capacitance type detection device which converts a rectangular wave generator and an output of the rectangular wave generator into a sawtooth wave through a time constant circuit. A phase conversion circuit that inputs a sawtooth wave to a threshold circuit and outputs a rectangular wave obtained by delaying the phase of the output of the rectangular wave generator by a predetermined time (τ3); 1
A first sensor drive signal is generated by dividing the frequency by に よ り by a flip-flop circuit, and the frequency of the output of the phase conversion circuit is divided by に よ り by a second flip-flop circuit.
A synchronous frequency dividing circuit for generating a frequency-divided output delayed from the phase of the first sensor drive signal by the predetermined time (τ3) as a second sensor drive signal; a first sensor drive signal for a first series input resistor (R1); A first parallel sensor capacitance (C1)
In addition to one input terminal of an exclusive OR circuit (referred to as EXOR) through a time constant circuit, a second sensor drive signal is supplied to a second series input resistor (R2) and a second parallel sensor capacitance (C2;
C1) which is differentially changed from C1) to the other input terminal of the EXOR, and obtains a PWM (Pulse Width Modulation) signal from the EXOR output.
A WM output sensor, a detection circuit that converts the PWM signal into DC and outputs the DC signal to the outside, and amplifies the output of the detection circuit.
A feedback amplifier for feeding back the amplified signal to a threshold circuit in the phase conversion circuit and controlling the threshold. (2) The invention according to claim 2, wherein in (1), the output of the rectangular wave generator is converted into a sawtooth wave through a time constant circuit, and the sawtooth wave is input to a threshold circuit, A second phase conversion circuit that obtains a rectangular wave whose output phase of the generator is delayed by a predetermined time (τ4) and inputs the rectangular wave to a first flip-flop circuit of a synchronous frequency divider; The polarity is inverted and the inverted signal is
And a polarity inversion circuit for controlling the threshold value by feeding back to the threshold value circuit in the phase conversion circuit. (3) In the invention according to claim 3, in the above (1) or (2), the output of the feedback amplifier or the polarity inversion circuit is connected to the power supply input terminal of the threshold value circuit of the phase conversion circuit or the second phase conversion circuit. Is given. (4) The exclusive-OR circuit according to (1) or (2), wherein the threshold circuit of the phase conversion circuit or the second phase conversion circuit has one input terminal grounded.
Or an AND circuit or an OR circuit in which both input terminals are connected to each other. (5) The invention according to claim 5, wherein in any one of (1) and (2), one and the other output terminals of the flip-flop circuit of the synchronous frequency divider circuit are one and the other input terminal of the second flip circuit. Are connected to each other. (6) In the invention of claim 6, in the above (5), the first and second flip-flop circuits are JK flip-flop circuits. (7) The capacitance type detection device according to claim 7, wherein a rectangular wave generator and an output of the rectangular wave generator are connected to a first series input resistor (R
1) through a first time constant circuit comprising a first parallel sensor capacitor (C1, C1 '), to one input terminal of a gate circuit comprising an AND circuit or an OR circuit, and to output the output of the rectangular wave generator to a second series circuit. A capacitive PWM that obtains a PWM signal by an output of the gate circuit in addition to the other input terminal of the gate circuit through a second time constant circuit including an input resistance (R2) and a second parallel sensor capacitance (C2, C2 ′). An output sensor, a fixed-amplitude circuit that receives the output of the PWM output sensor and outputs the input signal with a constant amplitude, a detection circuit that converts the output of the fixed-amplitude circuit to DC and outputs the same to the outside, A feedback amplifier that amplifies the output of the detection circuit, feeds back the amplified signal to a power input terminal of the gate circuit of the PWM output sensor, and controls a threshold value of the gate circuit. A. (8) A capacitance type detection device according to claim 8, wherein a rectangular wave generator, an amplitude variable circuit for varying the amplitude of the output of the rectangular wave generator, and an output of the variable amplitude circuit are connected to a first serial input resistor. (R1) and a first parallel sensor capacitor (C1, C1 ') through a first time constant circuit, to one input terminal of a gate circuit formed of an AND circuit or an OR circuit, and to output the output of the variable amplitude circuit to a second series circuit. A capacitive PWM that obtains a PWM signal from the output of the gate circuit in addition to the other input terminal of the gate circuit through a second time constant circuit including an input resistor (R2) and a second parallel sensor capacitance (C2, C2 ′). An output sensor, a detection circuit for converting the output of the PWM output sensor into a direct current and outputting the output to the outside, amplifying the output of the detection circuit, giving the amplified signal to an amplitude variable circuit, Control the return Those comprising an amplifier. (9) In the ninth aspect of the present invention, in the above (8), the amplitude variable circuit comprises an AND circuit or an OR circuit having both input terminals connected to each other, and the output of the feedback amplifier is given to the power supply input terminal. Things.
【００１２】[0012]
【発明の実施の形態】（１） 実施例１ この発明の第１の実施例を図１、図２に図８と対応する
部分に同じ符号を付けて示す。この発明の静電容量式検
出装置は、矩形波発生器６、静電容量式ＰＷＭ出力セン
サ８、検波回路２０、帰還増幅器３３、位相変換回路４
１及び同期分周回路４２からなる。センサ８の一方の駆
動信号ＳＤの周波数及び位相を位相変換回路４１及び同
期分周回路４２によりあらかじめ遅れた位相で駆動する
もので、外力“０”の時のＰＷＭ出力パルス幅を時定数
τ１，τ２により設定する。センサ８は回路２０−３３
−４１−４２−８より成るフィードバックループ内に組
み込まれている。検波回路２０は、ＰＷＭ信号ＳＧを平
滑し、比較増幅器２３よりＶ0 を出力し、帰還増幅器３
３はＶ0 の極性を反転した信号を出力する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (1) Embodiment 1 A first embodiment of the present invention is shown in FIGS. 1 and 2 by attaching the same reference numerals to parts corresponding to those in FIG. The capacitance type detection device of the present invention includes a rectangular wave generator 6, a capacitance type PWM output sensor 8, a detection circuit 20, a feedback amplifier 33, and a phase conversion circuit 4.
1 and a synchronous frequency dividing circuit 42. The frequency and phase of one of the driving signals SD of the sensor 8 are driven with a phase delayed by a phase conversion circuit 41 and a synchronization frequency dividing circuit 42. When the external force is "0", the PWM output pulse width is set to a time constant τ1, Set by τ2. The sensor 8 is a circuit 20-33
-41-42-8. The detection circuit 20 smoothes the PWM signal SG, outputs V 0 from the comparison amplifier 23,
3 outputs a signal in which the polarity of V 0 is inverted.
【００１３】位相変換回路４１及び同期分周回路４２
は、帰還信号ＶF を、位相変換回路４１のしきい値回路
（ＥＸＯＲより成る）４３の電源入力にすることによ
り、アナログ帰還信号ＶF に応じてしきい値が変化し、
出力信号ＳＣの位相を早めることができる。以上の様に
センサ８の出力ＳＨに対し、センサ８の駆動信号ＳＥの
位相を制御することにより出力Ｖ0 の安定を図ることが
できる。即ち、ＰＷＭ出力センサ８がフィードバックル
ープに組み込まれていることで出力の安定が図られてい
る。The phase conversion circuit 41 and the synchronization frequency dividing circuit 42
Is the feedback signal V F, (consisting EXOR) threshold circuit of the phase conversion circuit 41 by the power input 43, the threshold is changed according to the analog feedback signal V F,
The phase of the output signal SC can be advanced. As described above, the output V 0 can be stabilized by controlling the phase of the drive signal SE of the sensor 8 with respect to the output SH of the sensor 8. In other words, the output is stabilized by incorporating the PWM output sensor 8 in the feedback loop.
【００１４】位相変換回路４１はＲ３，Ｃ３より成る時
定数回路を持ち、駆動パルスＳＡを入力とし、ＥＸＯＲ
より成るしきい値回路４３の電源電圧変化によるしきい
値Ｖ thの変化を利用し、出力ＳＣの位相変化を得るもの
で出力ＳＣは位相と共に出力デューティ（幅）も同時に
変化する為、この信号ＳＣを同期分周回路４２のＴ型フ
リップフロップ回路Ｆ／Ｆ２により分周することにより
デューティ比５０％の駆動パルスＳＥを出力する。また
入力駆動パルスＳＡと同期分周回路４２のＦ／Ｆ１（Ｔ
型Ｆ／Ｆ）で分周することにより、センサ８のデューテ
ィ比５０％の一方の駆動パルスＳＤを得る。駆動パルス
ＳＤとＳＥとは入力駆動パルスＳＡに同期しており、従
って互いに同期したパルスである。センサ出力ＳＨはＳ
Ａの立下りよりａ時間だけ遅れて立下る。この遅延時間
ａはセンサ８の時定数τ１（Ｒ１，Ｃ１）＝τ２（Ｒ
２，Ｃ２）により遅れる時間であり、ＳＨの幅ｂはセン
サの入力（例えば圧力、外力等）がゼロまたは標準値で
あるときの幅であり、位相変換回路４１のＲ３，Ｃ３の
時定数τ３によって定まる。When the phase conversion circuit 41 is composed of R3 and C3
It has a constant circuit, receives drive pulse SA as input,
Caused by power supply voltage change of the threshold circuit 43 composed of
Value V thTo obtain the phase change of the output SC using the change of
The output SC has the phase and the output duty (width) at the same time
Therefore, the signal SC is transmitted to the T-type
By dividing by the flip-flop circuit F / F2
A drive pulse SE having a duty ratio of 50% is output. Also
The input drive pulse SA and the F / F1 (T
By dividing the frequency by the type F / F, the duty
One drive pulse SD having a ratio of 50% is obtained. Drive pulse
SD and SE are synchronized with the input drive pulse SA, and
Are pulses synchronized with each other. The sensor output SH is S
It falls after a time delay from the fall of A. This delay time
a is the time constant τ1 (R1, C1) = τ2 (R
2, C2), and the SH width b is
Input (eg pressure, external force, etc.) is zero or standard value
It is a width at a certain time, and R3 and C3 of the phase conversion circuit 41
It is determined by the time constant τ3.
【００１５】なお、しきい値回路４３としてＥＸＯＲの
代わりに２つの入力端子を互いに接続したＡＮＤゲート
またはＯＲゲートを用いることもできる。図３に示す同
期分周回路は静電容量式ＰＷＭセンサ８へ駆動パルスＳ
Ｄ及びＳＥを供給するもので、ＳＥ信号はＳＤ信号に対
し位相変換回路４１による遅延時間を持つ相似信号でな
ければならない。フリップフロップ回路Ｆ／Ｆ１，Ｆ／
Ｆ２を各々独立に２回路動作させた場合、電源投入時あ
るいは片方がノイズによる誤作動をした場合等出力ＳＥ
の極性設定ができなくなる。本回路は常に同期極性分周
出力を得る為の回路で、Ｑ１とＪ２，Ｑ- 1 とＫ２を接
続することによりＦ／Ｆ１の出力極性に従属し作動す
る。図３に示す様にＳＤはＦ／Ｆ２の極性判別出力とな
り、ノイズ作動を少なくすると共に、ＳＥ出力幅に影響
を生ずる作動をしてもその影響をノイズ作動した１周期
パルスのみに押さえる事ができる。 （２） 実施例２ 第２の実施例を図４に示す。図４では図１の回路に、帰
還極性反転回路４５、位相変換回路４６を追加し、セン
サ８の２つの駆動信号ＳＤ，ＳＥの位相を帰還制御する
ことにより出力Ｖ0 の安定化を図っている。しきい値回
路４３，４７として２つの入力端子を互いに接続したＡ
ＮＤゲートまたはＯＲゲートを用いてもよい。 （３） 実施例３ 第３の実施例を図５、図６に示す。検出装置は、矩形波
発生器６とセンサ（ＡＮＤまたはＯＲ信号処理）８と振
幅固定回路５１、検波回路２０、帰還増幅器３３からな
り、センサ８はあらかじめセンサ外部に取付けたキャパ
シタＣ２’またはＣ１’により外力“０”または基準値
の時の出力Ｓ３のパルス幅を時定数τ１とτ２の差によ
り設定する。インバータ回路より成る振幅固定回路５１
は、センサ出力Ｓ３の振幅変動を除去し、一定振幅のＰ
ＷＭ信号Ｓ４を出力する。検波回路２０はこのＰＷＭ信
号Ｓ４を平滑（アナログ変換）し、増幅した信号Ｖ0 を
出力する。帰還増幅器３３は出力信号Ｖ0 の極性を反転
し、センサ８のＡＮＤまたはＯＲ回路７’の電源端子に
接続する。外力によりセンサ８の時定数τ１，τ２か差
動的８に変化され、パルス幅変調された出力信号Ｓ３に
対し、ＡＮＤ／ＯＲ回路７’のしきい値Ｖthを制御し、
出力の安定を図っている。It should be noted that an AND gate or OR gate having two input terminals connected to each other can be used as the threshold circuit 43 instead of EXOR. The synchronous frequency dividing circuit shown in FIG.
In order to supply D and SE, the SE signal must be a similar signal having a delay time by the phase conversion circuit 41 with respect to the SD signal. Flip-flop circuits F / F1, F /
Output SE when F2 is operated independently by two circuits, when power is turned on, or when one of them malfunctions due to noise.
Cannot be set. This circuit is a circuit for always obtaining a synchronous polarity frequency divided output, and operates depending on the output polarity of F / F1 by connecting Q1 and J2 and Q - 1 and K2. As shown in FIG. 3, SD becomes an output for discriminating the polarity of F / F2, thereby reducing the noise operation and suppressing the effect to only the one-period pulse that operates the noise even if the operation has an effect on the SE output width. it can. (2) Embodiment 2 FIG. 4 shows a second embodiment. In FIG. 4, a feedback polarity inversion circuit 45 and a phase conversion circuit 46 are added to the circuit of FIG. 1, and the output V 0 is stabilized by feedback controlling the phases of the two drive signals SD and SE of the sensor 8. I have. A circuit in which two input terminals are connected to each other as threshold circuits 43 and 47
An ND gate or an OR gate may be used. (3) Embodiment 3 FIGS. 5 and 6 show a third embodiment. The detection device comprises a rectangular wave generator 6, a sensor (AND or OR signal processing) 8, an amplitude fixing circuit 51, a detection circuit 20, and a feedback amplifier 33, and the sensor 8 is a capacitor C2 'or C1' previously mounted outside the sensor. , The pulse width of the output S3 at the time of the external force “0” or the reference value is set by the difference between the time constants τ1 and τ2. Amplitude fixing circuit 51 composed of an inverter circuit
Removes fluctuations in the amplitude of the sensor output S3, and sets P
The WM signal S4 is output. Detection circuit 20 is the PWM signal S4 and smooth (analog conversion), and outputs a signal V 0 obtained by amplifying. The feedback amplifier 33 inverts the polarity of the output signal V 0 and connects it to the power supply terminal of the AND or OR circuit 7 ′ of the sensor 8. The time constants τ1 and τ2 of the sensor 8 are changed to the differential 8 by the external force, and the threshold value V th of the AND / OR circuit 7 ′ is controlled with respect to the pulse width modulated output signal S3.
The output is stabilized.
【００１６】センサ８の出力段７がＡＮＤの場合はＣ
２’を付けてτ１＜τ２とし、ＯＲの場合はＣ１’を付
けてτ１＞τ２とする。いずれの場合も、外力によりＣ
１が減少し、Ｃ２が増加すると、センサ出力Ｓ３のＨ
（ハイ）レベルの期間が減少する。振幅固定回路（イン
バータ）５１の出力Ｓ４は逆にＨレベルの期間が増加す
る。 （４） 実施例４ 第４の実施例を図７に示す。矩形波発生器６とセンサ
（ＡＮＤまたはＯＲ信号処理）８と検波回路２０と、帰
還増幅器３３と、振幅可変回路２１とからなり、センサ
８は、あらかじめセンサ外部に取付けたキャパシタＣ
２’またはＣ１’により外力“０”または基準値の時の
出力Ｓ５のパルス幅を時定数τ１，τ２の差により設定
する。検波回路２０はこのセンサ８のＰＷＭ出力Ｓ５を
平滑（アナログ変換）し、増幅して信号Ｖ0 を出力す
る。帰還増幅器３３は出力信号Ｖ0 の極性を反転し、Ａ
ＮＤゲートまたはＯＲゲートまたはＥＸＯＲより成る振
幅可変回路の電源端子に接続する。出力Ｖ0 が増加する
と帰還信号ＶF が減少し、振幅可変回路２１の出力Ｓ２
の振幅が減少する。そのためゲート回路７の入力Ｓ３，
Ｓ４のレベルが減少し、その出力Ｓ５のＨレベルの期間
が減少する。よって出力Ｖ 0 は減少する。このように負
帰還制御が行われることにより出力Ｖ0 の安定化を図っ
ている。When the output stage 7 of the sensor 8 is AND, C
2 ′ to make τ1 <τ2, and in the case of OR, add C1 ′
Τ1> τ2. In either case, C
When 1 decreases and C2 increases, H of the sensor output S3 increases.
The period of the (high) level decreases. Fixed amplitude circuit
Conversely, the output S4 of the (verter) 51 has an increased H level period.
You. (4) Fourth Embodiment FIG. 7 shows a fourth embodiment. Square wave generator 6 and sensor
(AND or OR signal processing) 8, the detection circuit 20,
A feedback amplifier 33 and a variable amplitude circuit 21
8 is a capacitor C previously mounted outside the sensor.
2 'or C1' when the external force is "0" or the reference value
Set the pulse width of output S5 by the difference between time constants τ1 and τ2
I do. The detection circuit 20 detects the PWM output S5 of the sensor 8
After smoothing (analog conversion), amplifying the signal V0Output
You. The feedback amplifier 33 outputs the output signal V0The polarity of A
ND gate or OR gate or EXOR
Connect to power supply terminal of variable width circuit. Output V0Increases
And feedback signal VFDecreases, and the output S2 of the variable amplitude circuit 21
Decrease in amplitude. Therefore, the input S3 of the gate circuit 7
The period when the level of S4 decreases and the output S5 is at the H level
Decrease. Therefore, the output V 0Decreases. So negative
Output V is obtained by performing feedback control.0To stabilize
ing.
【００１７】前述の（３）項と同様にセンサ８がＯＲで
信号処理する場合、Ｃ２’の代わりにＣ１’を取り付け
る必要がある。When the sensor 8 performs signal processing by OR similarly to the above-mentioned item (3), it is necessary to attach C1 'instead of C2'.
【００１８】[0018]
【発明の効果】この発明では、検波回路２０の出力を帰
還増幅器３３を介して検波回路２０の入力側に負帰還す
るループの中に、ＰＷＭ出力センサ８を挿入するように
したので、センサ出力のノイズ及びドリフトが抑圧さ
れ、検波回路２０の出力はそのノイズ及びドリフトが低
減し、安定化される。According to the present invention, the PWM output sensor 8 is inserted into a loop for negatively feeding the output of the detection circuit 20 to the input side of the detection circuit 20 via the feedback amplifier 33. Is suppressed, and the noise and drift of the output of the detection circuit 20 are reduced and stabilized.
【図１】第１の実施例を示す回路図。FIG. 1 is a circuit diagram showing a first embodiment.
【図２】図１の動作波形図。FIG. 2 is an operation waveform diagram of FIG.
【図３】Ａは図１の同期分周回路の結線図、ＢはＡの機
能表、ＣはＡの動作波形図。3A is a connection diagram of the synchronous frequency dividing circuit of FIG. 1, B is a function table of A, and C is an operation waveform diagram of A. FIG.
【図４】第２の実施例を示す回路図。FIG. 4 is a circuit diagram showing a second embodiment.
【図５】第３の実施例を示す回路図。FIG. 5 is a circuit diagram showing a third embodiment.
【図６】図５の要部の動作波形図。FIG. 6 is an operation waveform diagram of a main part of FIG. 5;
【図７】第４の実施例を示す回路図。FIG. 7 is a circuit diagram showing a fourth embodiment.
【図８】従来の静電容量式検出装置の回路図。FIG. 8 is a circuit diagram of a conventional capacitance-type detection device.
【図９】図８の要部の動作波形図。9 is an operation waveform diagram of a main part of FIG. 8;
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｇ０１Ｒ 19/00 Ｇ０１Ｒ 19/00 Ｐ Ｇ０１Ｄ 3/04 Ｆ Ｆターム(参考） 2F055 AA01 AA03 BB11 CC14 EE25 GG31 GG44 2F075 AA05 AA06 AA10 EE04 2F077 AA16 AA21 HH13 TT09 TT21 TT35 TT82 2G035 AA06 AA08 AB00 AB06 AC16 AD12 AD14 AD20 AD23 AD25 AD27 AD29 AD51 AD55 AD56 AD60 AD61 AD62 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI theme coat ゛ (reference) G01R 19/00 G01R 19/00 P G01D 3/04 FF term (reference) 2F055 AA01 AA03 BB11 CC14 EE25 GG31 GG44 2F075 AA05 AA06 AA10 EE04 2F077 AA16 AA21 HH13 TT09 TT21 TT35 TT82 2G035 AA06 AA08 AB00 AB06 AC16 AD12 AD14 AD20 AD23 AD25 AD27 AD29 AD51 AD55 AD56 AD60 AD61 AD62
Claims (9)
力を時定数回路を通して鋸歯状波に変換し、その鋸歯状
波をしきい値回路に入力して、前記矩形波発生器の出力
の位相を所定時間（τ３）だけ遅らせた矩形波を出力す
る位相変換回路と、 前記矩形波発生器の出力の周波数を第１フリップフロッ
プ回路により１／２に分周して第１センサ駆動信号を発
生すると共に、前記位相変換回路の出力の周波数を第２
フリップフロップ回路により１／２に分周し、前記第１
センサ駆動信号の位相より前記所定時間（τ３）だけ遅
れた分周出力を第２センサ駆動信号として発生する同期
分周回路と、 前記第１センサ駆動信号を第１直列入力抵抗（Ｒ１）と
第１並列センサ容量（Ｃ１）より成る第１時定数回路を
通して排他的論理和回路（ＥＸＯＲと言う）の一方の入
力端子に加え、前記第２センサ駆動信号を第２直列入力
抵抗（Ｒ２）と第２並列センサ容量（Ｃ２；Ｃ１と差動
的に変化する）より成る第２時定数回路を通して前記Ｅ
ＸＯＲの他方の入力端子に加え、そのＥＸＯＲ出力より
ＰＷＭ（パルス幅変調）信号を得る静電容量式ＰＷＭ出
力センサと、 前記ＰＷＭ信号を直流に変換して外部に出力する検波回
路と、 前記検波回路の出力を増幅して、その増幅した信号を前
記位相変換回路内の前記しきい値回路に帰還して、その
しきい値を制御する帰還増幅器と、 を具備することを特徴とする静電容量式検出装置。1. A rectangular wave generator and an output of the rectangular wave generator are converted into a sawtooth wave through a time constant circuit, and the sawtooth wave is input to a threshold circuit, and A phase conversion circuit that outputs a rectangular wave whose output phase is delayed by a predetermined time (τ3); and a first flip-flop circuit that divides the frequency of the output of the rectangular wave generator by half to drive the first sensor A signal is generated and the frequency of the output of the phase conversion circuit is changed to a second
The frequency is divided by 1/2 by a flip-flop circuit,
A synchronous frequency divider circuit for generating a frequency-divided output delayed from the phase of the sensor drive signal by the predetermined time (τ3) as a second sensor drive signal, and a first series input resistor (R1) In addition to one input terminal of an exclusive OR circuit (referred to as EXOR) through a first time constant circuit comprising one parallel sensor capacitor (C1), the second sensor drive signal is supplied to a second serial input resistor (R2) and a second serial input resistor (R2). The above E is passed through a second time constant circuit comprising two parallel sensor capacitors (C2; which changes differentially with C1).
A capacitive PWM output sensor that obtains a PWM (pulse width modulation) signal from the EXOR output in addition to the other input terminal of the XOR; a detection circuit that converts the PWM signal into DC and outputs the DC to the outside; A feedback amplifier that amplifies the output of the circuit, feeds back the amplified signal to the threshold circuit in the phase conversion circuit, and controls the threshold. Capacitive detector.
出力を時定数回路を通して鋸歯状波に変換し、その鋸歯
状波をしきい値回路に入力して、前記矩形波発生器の出
力の位相を所定時間（τ４）だけ遅らせた矩形波を得、
その矩形波を前記同期分周回路の前記第１フリップフロ
ップ回路に入力する第２の位相変換回路と、 前記帰還増幅器の出力の極性を反転して、その極性反転
した信号を前記第２の位相変換回路内の前記しきい値回
路に帰還してそのしきい値を制御する極性反転回路と、 を追加したことを特徴とする静電容量式検出装置。2. The rectangular wave generator according to claim 1, wherein the output of said rectangular wave generator is converted into a sawtooth wave through a time constant circuit, and the sawtooth wave is input to a threshold circuit. Is obtained by delaying the phase by a predetermined time (τ4),
A second phase conversion circuit for inputting the rectangular wave to the first flip-flop circuit of the synchronous frequency dividing circuit; and inverting the polarity of the output of the feedback amplifier, and applying the inverted signal to the second phase. And a polarity inversion circuit for controlling the threshold value by feeding back to the threshold value circuit in the conversion circuit.
幅器または前記極性反転回路の出力が、前記位相変換回
路または前記第２の位相変換回路の前記しきい値回路の
電源入力端子に与えられていることを特徴とする静電容
量式検出装置。3. The power supply input terminal according to claim 1, wherein an output of said feedback amplifier or said polarity inversion circuit is supplied to a power supply input terminal of said threshold value circuit of said phase conversion circuit or said second phase conversion circuit. A capacitance type detection device.
換回路または前記第２の位相変換回路の前記しきい値回
路が、片方の入力端子を接地した排他的論理和回路、ま
たは両方の入力端子を互いに接続したＡＮＤ回路または
ＯＲ回路より成ることを特徴とする静電容量式検出装
置。4. The exclusive OR circuit according to claim 1, wherein the threshold circuit of the phase conversion circuit or the second phase conversion circuit has one input terminal grounded, or both input terminals. Characterized by an AND circuit or an OR circuit connected to each other.
同期分周回路の前記フリップフロップ回路の一方及び他
方の出力端子が前記第２フリップ回路の一方及び他方の
入力端子にそれぞれ接続されていることを特徴とする静
電容量式検出装置。5. The synchronous frequency dividing circuit according to claim 1, wherein one and the other output terminals of the flip-flop circuit of the synchronous frequency dividing circuit are connected to one and the other input terminal of the second flip circuit, respectively. A capacitance type detection device.
ップフロップ回路がＪＫフリップフロップ回路であるこ
とを特徴とする静電容量式検出装置。6. The electrostatic capacitance detection device according to claim 5, wherein the first and second flip-flop circuits are JK flip-flop circuits.
第１並列センサ容量（Ｃ１，Ｃ1 ’）より成る第１時定
数回路を通して、ＡＮＤ回路またはＯＲ回路より成るゲ
ート回路の一方の入力端子に加え、前記矩形波発生器の
出力を第２直列入力抵抗（Ｒ２）と第２並列センサ容量
（Ｃ２，Ｃ２’）より成る第２時定数回路を通して前記
ゲート回路の他方の入力端子に加え、そのゲート回路の
出力によりＰＷＭ信号を得る静電容量式ＰＷＭ出力セン
サと、 前記ＰＷＭ出力センサの出力を入力して、その入力信号
の振幅を一定にして出力する振幅固定回路と、 その振幅固定回路の出力を直流に変換して外部に出力す
る検波回路と、 その検波回路の出力を増幅して、その増幅した信号を前
記ＰＷＭ出力センサの前記ゲート回路の電源入力端子に
帰還して、そのゲート回路のしきい値を制御する帰還増
幅器と、 を具備することを特徴とする静電容量式検出装置。7. An AND circuit which outputs the output of the rectangular wave generator through a first time constant circuit comprising a first series input resistor (R1) and a first parallel sensor capacitor (C1, C1 '). Alternatively, in addition to one input terminal of a gate circuit composed of an OR circuit, the output of the rectangular wave generator is connected to a second time constant circuit composed of a second series input resistance (R2) and a second parallel sensor capacitance (C2, C2 ′). And a capacitance-type PWM output sensor that obtains a PWM signal from the output of the gate circuit in addition to the other input terminal of the gate circuit, and the output of the PWM output sensor is input to make the amplitude of the input signal constant. An amplitude fixing circuit that converts the output of the amplitude fixing circuit into a direct current and outputs the output to the outside; amplifies the output of the detection circuit and outputs the amplified signal to the gate of the PWM output sensor. Fed back to the power supply input terminal of the bets circuit, the electrostatic capacitance detection device, characterized by comprising a feedback amplifier for controlling the threshold value of the gate circuit.
と、 その振幅可変回路の出力を第１直列入力抵抗（Ｒ１）と
第１並列センサ容量（Ｃ１，Ｃ１’）より成る第１時定
数回路を通して、ＡＮＤ回路またはＯＲ回路より成るゲ
ート回路の一方の入力端子に加え、前記振幅可変回路の
出力を第２直列入力抵抗（Ｒ２）と第２並列センサ容量
（Ｃ２，Ｃ２’）より成る第２時定数回路を通して前記
ゲート回路の他方の入力端子に加え、そのゲート回路の
出力よりＰＷＭ信号を得る静電容量式ＰＷＭ出力センサ
と、 そのＰＷＭ出力センサの出力を直流に変換して外部に出
力する検波回路と、 前記検波回路の出力を増幅して、その増幅した信号を前
記振幅可変回路に与えて、その出力の振幅を制御する帰
還増幅器と、 を具備することを特徴とする静電容量式検出装置。8. A rectangular wave generator, an amplitude variable circuit for varying the amplitude of an output of the rectangular wave generator, and an output of the variable amplitude circuit, the first series input resistor (R1) and the first parallel sensor capacitance ( C1, C1 '), the output of the variable amplitude circuit is applied to one input terminal of a gate circuit composed of an AND circuit or an OR circuit and a second parallel input resistance (R2) through a first time constant circuit composed of a second serial input resistance (R2). A capacitive PWM output sensor that obtains a PWM signal from an output of the gate circuit in addition to the other input terminal of the gate circuit through a second time constant circuit including a sensor capacitor (C2, C2 ′); and the PWM output sensor. A detection circuit that converts the output of the detection circuit into a direct current and outputs the output to the outside; a feedback amplifier that amplifies the output of the detection circuit, supplies the amplified signal to the amplitude variable circuit, and controls the amplitude of the output, A capacitance type detection device comprising:
両方の入力端子を互いに接続したＡＮＤ回路またはＯＲ
回路より成り、その電源入力端子に前記帰還増幅器の出
力が与えられていることを特徴とする静電容量式検出装
置。9. An AND circuit or OR circuit according to claim 8, wherein said variable amplitude circuit has both input terminals connected to each other.
A capacitance type detection device comprising a circuit, and an output of the feedback amplifier is given to a power supply input terminal thereof.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20005998A JP3326521B2 (en) | 1998-07-15 | 1998-07-15 | Capacitive detection device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20005998A JP3326521B2 (en) | 1998-07-15 | 1998-07-15 | Capacitive detection device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000028394A true JP2000028394A (en) | 2000-01-28 |
| JP3326521B2 JP3326521B2 (en) | 2002-09-24 |
Family
ID=16418164
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20005998A Expired - Fee Related JP3326521B2 (en) | 1998-07-15 | 1998-07-15 | Capacitive detection device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3326521B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011107086A (en) * | 2009-11-20 | 2011-06-02 | Asahi Kasei Electronics Co Ltd | Capacitance detection circuit, pressure detector, acceleration detector and transducer for microphone |
| JP2012042216A (en) * | 2010-08-12 | 2012-03-01 | Nippon Telegr & Teleph Corp <Ntt> | Sensor |
| EP3862757A1 (en) * | 2020-02-07 | 2021-08-11 | Atlantic Inertial Systems Limited | Methods for closed loop operation of capacitive accelerometers and such capacitive accelerometers |
-
1998
- 1998-07-15 JP JP20005998A patent/JP3326521B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011107086A (en) * | 2009-11-20 | 2011-06-02 | Asahi Kasei Electronics Co Ltd | Capacitance detection circuit, pressure detector, acceleration detector and transducer for microphone |
| JP2012042216A (en) * | 2010-08-12 | 2012-03-01 | Nippon Telegr & Teleph Corp <Ntt> | Sensor |
| EP3862757A1 (en) * | 2020-02-07 | 2021-08-11 | Atlantic Inertial Systems Limited | Methods for closed loop operation of capacitive accelerometers and such capacitive accelerometers |
| US11662361B2 (en) | 2020-02-07 | 2023-05-30 | Atlantic Inertial Systems Limited | Methods for closed loop operation of capacitive accelerometers |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3326521B2 (en) | 2002-09-24 |
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