JP2000022155A - Thin film transistor circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress generation of hot carriers by connecting a plurality of sets of inverter circuit comprising a load MOS transistor and a drive MOS transistor in parallel thereby reducing the capacity of both MOS transistors. SOLUTION: The drain D of one thin film load MOS transistor Tr1 is connected with the source S of a thin film drive MOS transistor Tr2 to constitute a set of inverter circuit I. A plurality of sets of inverter circuit I are connected in parallel. An input signal is fed to each gate of the inverter circuits I and the connecting lines of the drain D of load MOS transistor Tr1 and the source S of drive MOS transistor Tr2 in each inverter circuit I are connected as the output lines of the entire circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor circuit comprising a thin film transistor to form an inverter circuit.

[0002]

2. Description of the Related Art Thin-film transistors are manufactured by using MOS on amorphous silicon or polysilicon formed on a glass substrate.
A transistor is a transistor that has been widely used in recent years for driving a liquid crystal display device.

[0003] Unlike a normal MOS transistor (formed on a silicon substrate), a thin film transistor has a structure without a terminal grounded to the substrate potential. FIG. 5 is a schematic diagram showing the structure of a normal MOS transistor.
This MOS transistor has a structure in which a drain D and a source S made of N ⁺ are formed on a P-type silicon substrate Sb, and a gate G is formed via a gate oxide film GOX.

FIG. 6 is a diagram showing an inverter circuit using a normal MOS transistor. In the inverter circuit, the load MOS transistor Tr1 and the drive MOS transistor Tr2 are connected in parallel, and output in a state where the power supply voltage is inverted based on a signal commonly input to both gates.

FIG. 7 is a schematic diagram showing the structure of a thin film transistor. In this thin film transistor, a drain D and a source S are formed in a polysilicon film T formed on a glass substrate GSb of quartz glass or the like.
In this structure, a gate G is formed on a region between the source S and the gate oxide film GOX via a gate oxide film GOX.

[0006]

However, when an inverter circuit or the like for flowing a high current, such as a drive circuit of a liquid crystal display device, is constituted by the above-mentioned thin film transistor, the substrate potential for releasing hot carriers generated by the drive current is reduced. Due to the lack of the hot carriers, the generated hot carriers are injected into the gate oxide film.

For this reason, there arises a problem that the threshold voltage of the thin film transistor is changed by the carriers injected into the gate oxide film by continuing the high current driving. This change in the threshold voltage reduces the circuit margin, and causes a decrease in operation stability.

[0008]

SUMMARY OF THE INVENTION The present invention is a thin film transistor circuit for solving such a problem. That is, the present invention relates to a 1
A plurality of sets of inverter circuits, each of which includes one load MOS transistor and one driving MOS transistor including a thin film transistor, are adjacently connected to each other.

In the present invention, since a plurality of sets of inverter circuits are connected in parallel to form a thin film transistor circuit, one load MOS transistor and one load transistor constituting one set of the inverter circuits are formed. The capacity of the driving MOS transistor can be reduced, and the generation of hot carriers can be suppressed.

Further, the thin film transistor circuit of the present invention comprises:
1 comprising a thin film transistor having a first channel width
A first inverter circuit in which one load MOS transistor and one driving MOS transistor formed of a thin film transistor having the first channel width are adjacent to each other, and a second channel width shorter than the first channel width A load MOS transistor formed of a thin film transistor having the following structure, and a second inverter circuit formed adjacent to one drive MOS transistor formed of the thin film transistor having the second channel width,
The first inverter circuit and the second inverter circuit are connected in parallel.

According to the present invention, the second inverter circuit including the load MOS transistor and the drive MOS transistor having the second channel width shorter than the first channel width is driven first, and is connected to the next stage. After that, a signal serving as a trigger of a circuit is transferred, and then a first inverter circuit including a load MOS transistor having a first channel width and a driving MOS transistor is driven. Thus, even if the threshold voltage of the load MOS transistor and the drive MOS transistor constituting the first inverter circuit fluctuates and an operation delay occurs, the second inverter circuit operates before the operation is delayed. Threshold voltage fluctuations in the inverter circuit can be absorbed by the second inverter circuit.

[0012]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a thin film transistor circuit according to the present invention. FIG.
FIG. 1 is a circuit diagram illustrating a first embodiment of a thin film transistor circuit of the present invention. This thin film transistor circuit is an inverter circuit whose output is inverted with respect to the input as a whole, and is mainly applied to a drive circuit of a liquid crystal display device which requires a high current.

That is, in the thin film transistor circuit according to the first embodiment, one load MOS transistor Tr1 composed of a thin film transistor (TFT) and a driving MOS transistor Tr2 also composed of a thin film transistor are adjacent to each other to form a set of inverter circuits I. In addition, a plurality of inverter circuits I are connected in parallel.

In the first embodiment, the drain D of the load MOS transistor Tr1 and the drive MOS transistor Tr
2 are connected to the source S, and an input signal is supplied to each gate G of each inverter circuit I. The connection line between the drain D of the load MOS transistor Tr1 and the source S of the drive MOS transistor Tr2 in each inverter circuit I is connected, and serves as an output line of the entire circuit.

That is, an input signal is applied to each gate G of each inverter circuit I, and an output based on this input is output from a connection line between the load MOS transistor Tr1 and the drive MOS transistor Tr2 to a next stage circuit (for example, a capacitor). Sent to Therefore, the capacity of the entire thin film transistor circuit is the sum of the capacity of each inverter circuit I.

In the thin-film transistor circuit of the first embodiment having such a configuration, for example, when a large-capacity inverter circuit is formed, a plurality of inverter circuits I are connected in parallel. That is, the capacity of one load MOS transistor Tr1 and one drive MOS transistor Tr2 can be reduced, and the generation of hot carriers can be suppressed by dispersing the flowing current.

FIG. 2 is a schematic plan view illustrating the wiring layout of the thin film transistor circuit according to the first embodiment. As described above, one load MOS transistor Tr1 and one drive MOS transistor Tr2 forming one set of inverter circuits are arranged so that the source S, the gate, and the drain D are arranged in a line. The inverter circuits are arranged in a direction orthogonal to the arrangement of the source S, the gate, and the drain D.

In particular, in the first embodiment, the load MOS transistor Tr1 and the drive MOS transistor Tr2 having a short channel width W are used.

A source electrode SP is connected to the source S of each load MOS transistor Tr1 so that the power supply voltage VDD
Is given. Further, each load MOS transistor Tr
1 and each drive MOS transistor Tr2, a common gate electrode GP is wired and used as an input line. The drain D of each load MOS transistor Tr1 and the source S of each drive MOS transistor Tr2 are connected by an output electrode OP and used as an output line.

With such a layout, each load MO
The sources S of the S transistor Tr1 are arranged in a line, and similarly, the gate and the drain D are also arranged in a line. Further, the sources S of the respective drive MOS transistors Tr2 are also arranged in a line, and similarly, the gates and the drains D are also arranged in a line.

That is, in the present embodiment, although the number of load MOS transistors and drive MOS transistors is increased as compared with the case where an inverter circuit having the same capacity is constituted by one load MOS transistor and drive MOS transistor having a large channel width. , The overall layout does not change.

In other words, the structure can be realized only by dividing the long source S, gate and drain D corresponding to a large channel width, and it is possible to manufacture the semiconductor device only by changing the mask without greatly changing the process.

Next, a second embodiment of the thin film transistor circuit of the present invention will be described. FIG. 3 is a circuit diagram illustrating a thin film transistor circuit according to the second embodiment. That is, this thin film transistor circuit comprises a first inverter circuit I1 comprising a load MOS transistor Tr1-1 comprising a thin film transistor capable of coping with a high current and a driving MOS transistor Tr2-1 comprising a thin film transistor.
And the load MOS transistor Tr1- having a channel width shorter than the channel width of the load MOS transistor Tr1-1 and the drive MOS transistor Tr2-1.
2 (thin film transistor) and the driving MOS transistor Tr2-2 (thin film transistor) constitute a second inverter circuit I2, and the first inverter circuit I1 and the second inverter circuit I2 are connected in parallel. I have.

The second inverter circuit I2 constituted by the thin-film transistor having a short channel width is connected in parallel to the first inverter circuit I1 for actually driving, so that the second inverter circuit I2 is first connected. , And a signal that triggers a circuit (for example, a capacitor) connected to the next stage can be transferred.

FIG. 4 is a diagram showing a change in the drain-source current Ids with respect to the drain-source voltage Vds using the gate voltage Vgs as a parameter. As shown in this figure,
Even with a small gate voltage Vgs, a drain-source current Ids equivalent to the high gate voltage Vgs can be obtained up to the change point.

That is, even when the second inverter circuit I2 driven by a small gate voltage is driven first as in this embodiment, it is possible to supply a sufficient current to the next-stage circuit (for example, a capacitor). it can.

Therefore, even if the threshold voltage of the first inverter circuit I1 that can cope with a high current is shifted and a transmission delay occurs, the potential of the second inverter circuit I2 driven first and the potential for the next circuit are reduced. Can be given.

Further, when the second inverter circuit I2 cannot respond, a high current can be supplied by the first inverter circuit I1 which actually performs the driving. That is, the shift of the threshold voltage of the first inverter circuit I1 that can handle a high current can be absorbed by the second inverter circuit I2 including a thin film transistor with a short channel width, and stable signal supply can be performed.

[0029]

As described above, the thin film transistor circuit according to the present invention has the following effects. In other words, by paralleling a plurality of sets of inverter circuits, 1
The capacity of one thin film MOS transistor can be reduced, the generation of hot carriers can be suppressed, and the variation in threshold can be reduced. As a result, a decrease in circuit margin can be suppressed, and a stable operation can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a first embodiment.

FIG. 2 is a schematic plan view illustrating a layout.

FIG. 3 is a circuit diagram illustrating a second embodiment.

FIG. 4 is a diagram illustrating characteristics.

FIG. 5 is a schematic cross-sectional view illustrating a MOS transistor.

FIG. 6 is a circuit diagram illustrating an inverter circuit.

FIG. 7 is a schematic cross-sectional view illustrating a thin-film MOS transistor.

[Explanation of symbols]

Tr1 ... Load MOS transistor, Tr2 ... Drive MOS
Transistor, I: inverter circuit, GP: gate electrode, SP: source electrode, OP: output electrode

Claims (3)

[Claims] 1. One load M comprising a thin film transistor
2. A thin film transistor circuit comprising: a plurality of sets of inverter circuits each including an OS transistor and one driving MOS transistor formed of a thin film transistor adjacent to each other; 2. The load MOS transistor and the drive MOS transistor are arranged such that their source, gate, and drain are arranged in a line, and the plurality of sets of inverter circuits are arranged in a row of the source, the gate, and the drain. 2. The thin film transistor circuit according to claim 1, wherein the thin film transistor circuit is arranged in a direction orthogonal to the thin film transistor. 3. A first load MOS transistor comprising a thin film transistor having a first channel width and a driving MOS transistor comprising a thin film transistor having a first channel width are adjacent to each other.
Inverter circuit, one load MOS transistor including a thin film transistor having a second channel width shorter than the first channel width, and one driving MOS transistor including the thin film transistor having the second channel width are adjacent to each other And a second inverter circuit configured as described above, wherein the first inverter circuit and the second inverter circuit are connected in parallel.