JP2000021926A5 - - Google Patents
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- JP2000021926A5 JP2000021926A5 JP1998190809A JP19080998A JP2000021926A5 JP 2000021926 A5 JP2000021926 A5 JP 2000021926A5 JP 1998190809 A JP1998190809 A JP 1998190809A JP 19080998 A JP19080998 A JP 19080998A JP 2000021926 A5 JP2000021926 A5 JP 2000021926A5
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- 239000004065 semiconductor Substances 0.000 claims description 176
- 230000003321 amplification Effects 0.000 claims description 43
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 43
- 239000000758 substrate Substances 0.000 claims description 36
- 230000005669 field effect Effects 0.000 claims description 7
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Description
前記高周波電力増幅器は、一主面に増幅手段が形成された半導体チップを配線基板の一主面側に搭載し、半導体チップの一主面に形成された電極と配線基板の一主面に形成された電極とを導電性のワイヤで電気的に接続している。増幅手段は、例えば複数の電界効果トランジスタの夫々を電気的に並列に接続した構成になっており、増幅手段のゲート端子(入力部)は半導体チップの一主面に形成されたチップ側入力用電極と電気的に接続され、増幅手段のドレイン端子(出力部)は半導体チップの一主面に形成されたチップ側出力用電極と電気的に接続されている。チップ側入力用電極は半導体チップの一辺側に配置され、チップ側出力用電極は半導体チップの一辺と対向する他の辺側に配置されている。増幅手段のソース端子は半導体チップの一主面と対向する他の面(裏面)に形成された裏面電極と電気的に接続され、この裏面電極は基準電位に電位固定される。チップ側入力用電極は、半導体チップの一辺と向かい合うようにして配線基板の一主面に形成された基板側入力用電極と入力用ワイヤを介して電気的に接続され、チップ側出力用電極は、半導体チップの他の辺と向かい合うにようにして配線基板の一主面に形成された基板側出力用電極と出力用ワイヤを介して電気的に接続されている。The high frequency power amplifier, a semiconductor chip amplifying means formed on one main surface to the mounting tower on one main surface side of the wiring substrate, on one main surface of the wiring substrate electrode formed on one main surface of the semiconductor chip The formed electrodes are electrically connected by conductive wires. The amplification means has, for example, a configuration in which a plurality of field effect transistors are electrically connected in parallel, and the gate terminal (input section) of the amplification means is for chip side input formed on one main surface of the semiconductor chip. It is electrically connected to the electrode, and the drain terminal (output unit) of the amplification means is electrically connected to the chip-side output electrode formed on one main surface of the semiconductor chip. The chip-side input electrode is arranged on one side of the semiconductor chip, and the chip-side output electrode is arranged on the other side facing one side of the semiconductor chip. The source terminal of the amplification means is electrically connected to a back surface electrode formed on another surface (back surface) facing one main surface of the semiconductor chip, and the back surface electrode is fixed at a reference potential. The chip-side input electrode is electrically connected to the substrate-side input electrode formed on one main surface of the wiring substrate so as to face one side of the semiconductor chip via an input wire, and the chip-side output electrode is , It is electrically connected to the output electrode on the substrate side formed on one main surface of the wiring substrate so as to face the other side of the semiconductor chip via the output wire.
平面が方形状で形成された半導体チップと、一主面側に前記半導体チップが搭載された配線基板と、前記半導体チップの一主面の第１領域に形成され、前記半導体チップの一辺側に配置された第１電極と、前記半導体チップの一主面の第１領域に形成され、入力部が前記第１電極と電気的に接続された第１増幅手段と、前記半導体チップの一主面の第２領域に形成され、前記半導体チップの一辺側に配置された第２電極と、前記半導体チップの一主面の第２領域に形成され、出力部が前記第２電極と電気的に接続された第２増幅手段と、前記半導体チップの一主面の第１領域と第２領域との間の第３領域に形成された第３電極と、前記半導体チップの一辺と向かい合うようにして前記配線基板の一主面に形成され、第１ワイヤを介して前記第１電極と電気的に接続された第４電極と、前記半導体チップの一辺と向かい合うようにして前記配線基板の一主面に形成され、第２ワイヤを介して前記第２電極と電気的に接続された第５電極と、前記半導体チップの一辺と向かい合うようにして前記配線基板の一主面に形成され、基準電位に電位固定される第３ワイヤを介して前記第３電極と電気的に接続された第６電極とを有する半導体装置であって、前記第６電極は、前記第５電極よりも前記半導体チップの一辺から遠く離れた位置に配置されている。前記第４電極は、前記半導体チップの一辺からの距離が前記第５電極とほぼ同一となる位置、又は前記第６電極よりも前記半導体チップの一辺から遠く離れた位置に配置されている。A semiconductor chip plane is formed in a rectangular shape, a wiring substrate on which the semiconductor chip is mounting tower on one main surface side, formed in a first region of one main surface of said semiconductor chip, one side of the semiconductor chip A first amplification means formed in a first region of one main surface of the semiconductor chip, the input portion of which is electrically connected to the first electrode, and a main unit of the semiconductor chip. A second electrode formed in the second region of the surface and arranged on one side of the semiconductor chip, and an output unit formed in the second region of one main surface of the semiconductor chip electrically with the second electrode. The connected second amplification means, the third electrode formed in the third region between the first region and the second region of one main surface of the semiconductor chip, and the third electrode formed so as to face one side of the semiconductor chip. A fourth electrode formed on one main surface of the wiring board and electrically connected to the first electrode via a first wire, and one main surface of the wiring board so as to face one side of the semiconductor chip. The fifth electrode, which is formed in the above and electrically connected to the second electrode via the second wire, and the fifth electrode, which is formed on one main surface of the wiring substrate so as to face one side of the semiconductor chip, are formed at a reference potential. A semiconductor device having a sixth electrode electrically connected to the third electrode via a third wire whose potential is fixed, the sixth electrode is one side of the semiconductor chip rather than the fifth electrode. It is located far away from. The fourth electrode is arranged at a position where the distance from one side of the semiconductor chip is substantially the same as that of the fifth electrode, or at a position farther from one side of the semiconductor chip than the sixth electrode.
増幅手段ＰＷ１、ＰＷ２の夫々は、図３に示す半導体チップ５に形成され、増幅手段ＰＷ３は、図示していないが、半導体チップ５と異なる他の半導体チップに形成されている。半導体チップ５は配線基板１の一主面に形成された凹部１Ａ内に搭載され、他の半導体チップは配線基板１の一主面に形成された他の凹部内に搭載されている。即ち、増幅手段が形成された半導体チップは配線基板１の一主面側に搭載されている。半導体チップ５、他の半導体チップの夫々は、平面が方形状（本実施形態においては長方形状）で形成されている。なお、増幅手段ＰＷ３が形成された他の半導体チップについては以降の説明を省略する。Each of the amplification means PW1 and PW2 is formed on the semiconductor chip 5 shown in FIG. 3, and the amplification means PW3 is formed on another semiconductor chip different from the semiconductor chip 5, although not shown. The semiconductor chip 5 is mounting tower in the recess 1A formed on one main surface of the wiring substrate 1, another semiconductor chip is mounting tower in another recess formed on one main surface of the wiring board 1. That is, the semiconductor chip amplifying means is formed is the mounting tower on one main surface side of the wiring board 1. Each of the semiconductor chip 5 and the other semiconductor chips has a rectangular plane (rectangular shape in this embodiment). The following description will be omitted for other semiconductor chips on which the amplification means PW3 is formed.
半導体チップ５が搭載された凹部１Ａの底面には、図４に示すように、導電プレート１Ｂが形成されている。導電プレート１Ｂは、その直下に形成されたスルーホール配線３を介して、配線基板１の一主面と対向する他の主面(裏面)に形成された基準電位用外部端子４と電気的に接続されている。この基準電位用外部端子４は例えば０［Ｖ］電位に電位固定される。なお、前述の入力用外部端子Ｐin、出力用外部端子Ｐout、電源電位用外部端子ＶＤＤ、外部端子ＶＧの夫々も配線基板１の裏面に形成されている。Semiconductor chip 5 on the bottom surface of the tower mount has been recesses 1A, as shown in FIG. 4, the conductive plate 1B is formed. The conductive plate 1B is electrically connected to the reference potential external terminal 4 formed on the other main surface (back surface) facing one main surface of the wiring board 1 via the through-hole wiring 3 formed immediately below the conductive plate 1B. It is connected. The reference potential external terminal 4 is fixed at a potential of, for example, 0 [V]. The input external terminal Pin of the foregoing, the output external terminal Pout, the power supply potential external terminal V DD, are formed on the back surface each well of the wiring substrate 1 of the external terminal V G.
Claims (28)
第１面と前記第１面に対向する第２面とを有し、前記第１面側に前記半導体チップが搭載された基板と、
前記半導体チップの第１面の第１領域に形成され、前記半導体チップの一辺側に配置された第１電極と、
前記第１領域に形成され、入力部が前記第１電極と電気的に接続された第１増幅手段と、
前記半導体チップの前記第１面の前記第１領域とは異なる第２領域に形成され、前記半導体チップの前記一辺側に配置された第２電極と、
前記第２領域に形成され、出力部が前記第２電極と電気的に接続された第２増幅手段と、
前記半導体チップの前記第１面の前記第１領域と前記第２領域との間の第３領域に形成された第３電極と、
前記半導体チップの前記一辺と向かい合うようにして前記基板の前記第１面に形成され、第１ワイヤを介して前記第１電極と電気的に接続された第４電極と、
前記半導体チップの前記一辺と向かい合うようにして前記基板の前記第１面に形成され、第２ワイヤを介して前記第２電極と電気的に接続された第５電極と、
前記半導体チップの前記一辺と向かい合うようにして前記基板の前記第１面に形成され、基準電位に電位固定される第３ワイヤを介して前記第３電極と電気的に接続された第６電極とを有し、
前記第６電極と前記半導体チップの前記一辺との間の距離は、前記第５電極と前記半導体チップの前記一辺との間の距離よりも大きいことを特徴とする半導体装置。A semiconductor chip whose plane is formed in a quadrilateral shape,
A second surface and has the said first surface side semiconductor chip tower mounting radicals plate opposite to the first surface and the first surface,
A first electrode formed in the first region of the first surface of the semiconductor chip and arranged on one side of the semiconductor chip, and
Formed prior Symbol first region, a first amplifying means for the input portion is electrically connected to the first electrode,
And wherein the semiconductor chip the first regions of the first surface of the formed in the different second regions, a second electrode disposed on the one edge side of the semiconductor chip,
Before SL are formed in the second region, the second amplifying means output unit is connected to the second electrode,
A third electrode formed in the third region between the semiconductor chip the first region and the second region of the first surface of,
And said semiconductor chip so as to face the one side are formed on the first surface of the front Kimoto plate, a fourth electrode electrically connected to the first electrode through the first wire,
And said semiconductor chip so as to face the one side are formed on the first surface of the front Kimoto plate, a fifth electrode electrically connected to the second electrode through a second wire,
6 wherein said semiconductor chip is formed on the first surface of Kimoto plate before as facing the one side, are electrically connected to the third electrode via the third wire being fixed potential to the reference potential With electrodes,
A semiconductor device characterized in that the distance between the sixth electrode and the one side of the semiconductor chip is larger than the distance between the fifth electrode and the one side of the semiconductor chip.
前記第４電極は、前記半導体チップの前記一辺からの距離が前記第５電極とほぼ同一となる位置に配置されていることを特徴とする半導体装置。 In the semiconductor device according to claim 1,
The fourth electrode, the semiconductor chip of the substantially identical to become position semiconductors devices characterized in that arranged on the location distance and the fifth electrode from one side.
前記第４電極と前記半導体チップの前記一辺との間の距離は、前記第６電極と前記半導体チップの前記一辺との間の距離よりも大きいことを特徴とする半導体装置。A semiconductor device characterized in that the distance between the fourth electrode and the one side of the semiconductor chip is larger than the distance between the sixth electrode and the one side of the semiconductor chip.
前記第２増幅手段の入力部は、前記第１増幅手段の出力部と電気的に接続されていることを特徴とする半導体装置。 In the semiconductor device according to any one of claims 1 to 3.
The input of the second amplifying means, characterized in that it is an output unit electrically connected to said first amplifying means semiconductors devices.
前記第４電極に入力された信号は、前記第１及び前記第２増幅手段を介して増幅され、前記第５電極から出力されることを特徴とする半導体装置。A semiconductor device characterized in that a signal input to the fourth electrode is amplified via the first and second amplification means and output from the fifth electrode.
第１面と前記第１面に対向する第２面とを有し、前記第１面側に前記半導体チップが搭載された基板と、
前記半導体チップの第１面の第１領域に形成され、前記半導体チップの一辺側に配置された第１電極と、
前記第１領域に形成され、入力部が前記第１電極と電気的に接続された第１増幅手段と、
前記半導体チップの前記第１面の前記第１領域とは異なる第２領域に形成され、前記半
導体チップの前記一辺側に配置された第２電極と、 前記第２領域に形成され、出力部が前記第２電極と電気的に接続された第２増幅手段と
、
前記半導体チップの前記一辺と向かい合うようにして前記基板の前記第１面に形成され、第１ワイヤを介して前記第１電極と電気的に接続された第３電極と、
前記半導体チップの前記一辺と向かい合うようにして前記基板の前記第１面に形成され、第２ワイヤを介して前記第２電極と電気的に接続された第４電極と、
前記第１領域に形成され、前記半導体チップの前記一辺と対向する他の辺側に配置され、前記第１増幅手段の出力部と電気的に接続された第５電極と、
前記第２領域に形成され、前記半導体チップの前記他の辺側に配置され、前記第２増幅手段の入力部と電気的に接続された第６電極と、
前記半導体チップの前記他の辺と向かい合うようにして前記基板の前記第１面に形成され、第３ワイヤを介して前記第５電極と電気的に接続された第７電極と、
前記半導体チップの前記他の辺と向かい合うようにして前記基板の前記第１面に形成され、第４ワイヤを介して前記第６電極と電気的に接続され、更に前記第７電極と電気的に接続された第８電極と、
前記半導体チップの前記一辺と向かい合うようにして前記基板の前記第１面に形成され、前記半導体チップの前記第１面の前記第１領域と前記第２領域との間の第３領域上を延在し、基準電位に電位固定される第５ワイヤの一端側が接続された第９電極と、
前記半導体チップの前記他の辺と向かい合うようにして前記基板の前記第１面に形成され、前記第５ワイヤの他端側が接続された第１０電極とを有し、
前記第９電極と前記半導体チップの前記一辺との間の距離は、前記第４電極と前記半導体チップの前記一辺との間の距離よりも大きく、
前記第１０電極と前記半導体チップの前記他の辺との間の距離は、前記第７電極と前記半導体チップの前記他の辺との間の距離よりも大きいことを特徴とする半導体装置。A semiconductor chip whose plane is formed in a quadrilateral shape,
A second surface and has the said first surface side semiconductor chip tower mounting radicals plate opposite to the first surface and the first surface,
A first electrode formed in the first region of the first surface of the semiconductor chip and arranged on one side of the semiconductor chip, and
Formed prior Symbol first region, a first amplifying means for the input portion is electrically connected to the first electrode,
Wherein formed on the semiconductor chip the first surface and the second region different from the first region of the second electrode that is disposed on the one side of the semiconductor chip, it is formed before Symbol second region, the output unit With the second amplification means electrically connected to the second electrode,
And said semiconductor chip so as to face the one side are formed on the first surface of the front Kimoto plate, third electrode electrically connected to the first electrode through the first wire,
And said semiconductor chip so as to face the one side are formed on the first surface of the front Kimoto plate, a fourth electrode electrically connected to the second electrode through a second wire,
Formed prior Symbol first region, and the semiconductor chip wherein are located in other side to one side facing the fifth electrode output unit electrically connected to said first amplifying means,
Formed prior Symbol second region, and wherein disposed on the other side of the semiconductor chip, a sixth electrode which is input portion electrically connected to said second amplifying means,
Said formed on the first surface of the front Kimoto plate as opposed to the other side of the semiconductor chip, a seventh electrode that is electrically connected to the fifth electrode through the third wire,
Wherein formed on the first surface of the front Kimoto plate as opposed to the other side of the semiconductor chip, it is electrically connected to the sixth electrode through the fourth wire, further the seventh electrode and the electrical 8th electrode connected to the
Said semiconductor chip the formed on the first surface of Kimoto plate prior to the face the one side of the third region on between the semiconductor chip the first surface of the first region and the second region of the And the 9th electrode to which one end side of the 5th wire, which extends and is fixed at the reference potential, is connected.
Wherein formed on the first surface of the front Kimoto plate as opposed to the other side of the semiconductor chip, and a tenth electrode other end of the fifth wire is connected,
The distance between the ninth electrode and the one side of the semiconductor chip is larger than the distance between the fourth electrode and the one side of the semiconductor chip .
A semiconductor device characterized in that the distance between the tenth electrode and the other side of the semiconductor chip is larger than the distance between the seventh electrode and the other side of the semiconductor chip.
前記第３電極は、前記半導体チップの前記一辺からの距離が前記第４電極とほぼ同一となる位置に配置され、
前記第７電極及び前記第８電極は、前記半導体チップの前記他の辺からの距離がほぼ同一となる位置に配置されていることを特徴とする半導体装置。 In the semiconductor device according to claim 6,
The third electrode, the distance from the one side of the semiconductor chip is arranged on substantially the same as a position and the fourth electrode,
The seventh electrode and the eighth electrode, the semiconductor chip of the other semi-conductor devices you characterized in that distance is arranged substantially the same as a position of the edge.
前記第３電極と前記半導体チップの前記一辺との間の距離は、前記第９電極と前記半導体チップの前記一辺との間の距離よりも大きいことを特徴とする半導体装置。A semiconductor device characterized in that the distance between the third electrode and the one side of the semiconductor chip is larger than the distance between the ninth electrode and the one side of the semiconductor chip.
第１面と前記第１面に対向する第２面とを有し、前記第１面側に前記半導体チップが搭載された基板と、
前記半導体チップの第１面の第１領域に形成された第１電極と、
前記第１領域に形成され、入力部が前記第１電極と電気的に接続された第１増幅手段と、
前記半導体チップの前記第１面の前記第１領域とは異なる第２領域に形成された第２電極と、
前記第２領域に形成され、出力部が前記第２電極と電気的に接続された第２増幅手段と、
前記基板の前記第１面に形成され、第１ワイヤを介して前記第１電極と電気的に接続された第３電極と、
前記基板の前記第１面に形成され、第２ワイヤを介して前記第２電極と電気的に接続された第４電極とを具備して成り、
前記第１増幅手段の出力部と前記第２増幅手段の入力部とは電気的に接続され、
前記第４電極は前記半導体チップの一辺と向かい合う位置に配置され、
前記第３電極は前記半導体チップの前記一辺に対して交わる他の辺と向かい合う位置に配置されていることを特徴とする半導体装置。A semiconductor chip whose plane is formed in a quadrilateral shape,
A second surface and has the said first surface side semiconductor chip tower mounting radicals plate opposite to the first surface and the first surface,
A first electrode formed on the first region of the first surface of the semiconductor chip,
Formed prior Symbol first region, a first amplifying means for the input portion is electrically connected to the first electrode,
A second electrode formed on a second area different from the first region of the first surface of the semiconductor chip,
Before SL are formed in the second region, the second amplifying means output unit is connected to the second electrode,
Before being formed on the first surface of Kimoto plate, third electrode electrically connected to the first electrode through the first wire,
Before being formed on the first surface of Kimoto plate, made by and a fourth electrode electrically connected to the second electrode through a second wire,
The output unit of the first amplification means and the input unit of the second amplification means are electrically connected to each other.
The fourth electrode is arranged at a position facing one side of the semiconductor chip.
The third electrode is a semiconductor device characterized by being arranged at a position facing the other side intersecting with respect to said one side of said semiconductor chip.
第１面と前記第１面に対向する第２面とを有し、前記第１面側に前記半導体チップが搭載された基板と、A substrate having a first surface and a second surface facing the first surface and having the semiconductor chip mounted on the first surface side.
前記半導体チップの第１面に形成された第１電極と、The first electrode formed on the first surface of the semiconductor chip and
前記半導体チップの前記第１面に形成され、入力部が前記第１電極と電気的に接続された第１増幅手段と、A first amplification means formed on the first surface of the semiconductor chip and having an input portion electrically connected to the first electrode.
前記半導体チップの前記第１面に形成された第２電極と、A second electrode formed on the first surface of the semiconductor chip and
前記半導体チップの前記第１面に形成され、出力部が前記第２電極と電気的に接続された第２増幅手段と、A second amplification means formed on the first surface of the semiconductor chip and having an output unit electrically connected to the second electrode.
前記基板の前記第１面に形成され、第１ワイヤを介して前記第１電極と電気的に接続された第３電極と、A third electrode formed on the first surface of the substrate and electrically connected to the first electrode via a first wire,
前記基板の前記第１面に形成され、第２ワイヤを介して前記第２電極と電気的に接続された第４電極とを具備して成り、A fourth electrode formed on the first surface of the substrate and electrically connected to the second electrode via a second wire is provided.
前記第１増幅手段の出力部と前記第２増幅手段の入力部とは電気的に接続され、The output unit of the first amplification means and the input unit of the second amplification means are electrically connected to each other.
前記第１ワイヤは、前記第１ワイヤと前記半導体チップの一辺とが互いに交差するように、前記第１電極から前記第３電極まで延在し、The first wire extends from the first electrode to the third electrode so that the first wire and one side of the semiconductor chip intersect with each other.
前記第２ワイヤは、前記第２のワイヤと前記半導体チップの前記一辺に対して交わる他の辺とが互いに交差するように、前記第２電極から前記第４電極まで延在することを特徴とする半導体装置。The second wire is characterized in that it extends from the second electrode to the fourth electrode so that the second wire and the other side intersecting with the one side of the semiconductor chip intersect with each other. Semiconductor device.
第１面と前記第１面に対向する第２面とを有し、前記第１面側に前記半導体チップが搭載された基板と、A substrate having a first surface and a second surface facing the first surface and having the semiconductor chip mounted on the first surface side.
前記半導体チップの第１面に形成された第１電極と、The first electrode formed on the first surface of the semiconductor chip and
前記半導体チップの前記第１面に形成され、入力部が前記第１電極と電気的に接続された第１増幅手段と、A first amplification means formed on the first surface of the semiconductor chip and having an input portion electrically connected to the first electrode.
前記半導体チップの前記第１面に形成された第２電極と、A second electrode formed on the first surface of the semiconductor chip and
前記半導体チップの前記第１面に形成され、出力部が前記第２電極と電気的に接続された第２増幅手段と、A second amplification means formed on the first surface of the semiconductor chip and having an output unit electrically connected to the second electrode.
前記基板の前記第１面に形成され、第１ワイヤを介して前記第１電極と電気的に接続された第３電極と、A third electrode formed on the first surface of the substrate and electrically connected to the first electrode via a first wire,
前記基板の前記第１面に形成され、複数の第２ワイヤを介して前記第２電極と電気的に接続された第４電極とを具備して成り、A fourth electrode formed on the first surface of the substrate and electrically connected to the second electrode via a plurality of second wires is provided.
前記第１増幅手段の出力部と前記第２増幅手段の入力部とは電気的に接続され、The output unit of the first amplification means and the input unit of the second amplification means are electrically connected to each other.
前記第１ワイヤは、前記第１ワイヤと前記半導体チップの一辺とが互いに交差するように、前記第１電極から前記第３電極まで延在し、The first wire extends from the first electrode to the third electrode so that the first wire and one side of the semiconductor chip intersect with each other.
前記複数の第２ワイヤの夫々は、前記複数の第２のワイヤの夫々と前記半導体チップの前記一辺に対して交わる他の辺とが互いに交差するように、前記第２電極から前記第４電極まで延在することを特徴とする半導体装置。Each of the plurality of second wires is from the second electrode to the fourth electrode so that each of the plurality of second wires and another side intersecting with the one side of the semiconductor chip intersect with each other. A semiconductor device characterized by extending to.
前記第１増幅手段の前記入力部に入力された信号を電圧増幅し、前記第２増幅手段の前記出力部から、電圧増幅された前記信号を出力することを特徴とする半導体装置。A semiconductor device characterized in that a signal input to the input unit of the first amplification means is voltage-amplified, and the voltage-amplified signal is output from the output unit of the second amplification means.
前記第１及び前記第２増幅手段の各々は、ゲート、ソース、及びドレインを有する電界効果トランジスタを含んで成り、Each of the first and second amplification means comprises a field effect transistor having a gate, a source, and a drain.
前記第１増幅手段の前記入力部は、前記第１増幅手段の前記電界効果トランジスタの前記ゲートであり、The input unit of the first amplification means is the gate of the field effect transistor of the first amplification means.
前記第１増幅手段の前記出力部は、前記第１増幅手段の前記電界効果トランジスタの前記ドレインであり、The output unit of the first amplification means is the drain of the field effect transistor of the first amplification means.
前記第２増幅手段の前記入力部は、前記第２増幅手段の前記電界効果トランジスタの前記ゲートであり、The input unit of the second amplification means is the gate of the field effect transistor of the second amplification means.
前記第２増幅手段の前記出力部は、前記第２増幅手段の前記電界効果トランジスタの前記ドレインであることを特徴とする半導体装置。A semiconductor device characterized in that the output unit of the second amplification means is the drain of the field effect transistor of the second amplification means.
第１面と前記第１面に対向する第２面とを有し、前記第１面側に前記半導体チップが搭載された基板と、A substrate having a first surface and a second surface facing the first surface and having the semiconductor chip mounted on the first surface side.
前記半導体チップの第１面の第１領域に形成された第１及び第２電極と、The first and second electrodes formed in the first region of the first surface of the semiconductor chip,
前記第１領域に形成され、入力部が前記第１電極と電気的に接続され、出力部が前記第２電極と電気的に接続された第１増幅手段と、A first amplification means formed in the first region, the input unit is electrically connected to the first electrode, and the output unit is electrically connected to the second electrode.
前記半導体チップの前記第１面の第２領域に形成された第３及び第４電極と、The third and fourth electrodes formed in the second region of the first surface of the semiconductor chip,
前記第２領域に形成され、入力部が前記第３電極と電気的に接続され、出力部が前記第４電極と電気的に接続された第２増幅手段と、A second amplification means formed in the second region, the input unit is electrically connected to the third electrode, and the output unit is electrically connected to the fourth electrode.
前記第１電極と前記基板の前記第１面とを接続する第１ワイヤと、A first wire connecting the first electrode and the first surface of the substrate,
前記第２電極と前記基板の前記第１面とを接続する第２ワイヤと、A second wire connecting the second electrode and the first surface of the substrate,
前記第３電極と前記基板の前記第１面とを接続する第３ワイヤと、A third wire connecting the third electrode and the first surface of the substrate,
前記第４電極と前記基板の前記第１面とを接続する第４ワイヤとを具備して成り、A fourth wire connecting the fourth electrode and the first surface of the substrate is provided.
前記第２ワイヤの長さは前記第１ワイヤの長さよりも短く、前記第２ワイヤの直列インピーダンスの大きさは前記第１ワイヤの直列インピーダンスの大きさよりも小さくなっており、The length of the second wire is shorter than the length of the first wire, and the magnitude of the series impedance of the second wire is smaller than the magnitude of the series impedance of the first wire.
前記第４ワイヤの長さは前記第３ワイヤの長さよりも短く、前記第４ワイヤの直列インピーダンスの大きさは前記第３ワイヤの直列インピーダンスの大きさよりも小さくなっていることを特徴とする半導体装置。A semiconductor characterized in that the length of the fourth wire is shorter than the length of the third wire, and the magnitude of the series impedance of the fourth wire is smaller than the magnitude of the series impedance of the third wire. apparatus.
前記第１乃至第４ワイヤの長さは、夫々前記第１乃至第４電極の位置に依存して決定されることを特徴とする半導体装置。A semiconductor device, wherein the length of the first to fourth wires is determined depending on the positions of the first to fourth electrodes, respectively.
前記第２電極は前記半導体チップの一辺に近接して配置され、The second electrode is arranged close to one side of the semiconductor chip.
前記第４電極は前記半導体チップの前記一辺に対向する辺に近接して配置されることを特徴とする半導体装置。A semiconductor device characterized in that the fourth electrode is arranged close to a side of the semiconductor chip facing the one side.
入力端子が第５ワイヤを介して前記基板に電気的に接続され、出力端子が第６ワイヤを介して前記基板に電気的に接続される第３増幅手段を更に具備して成り、It further comprises a third amplification means in which the input terminal is electrically connected to the substrate via the fifth wire and the output terminal is electrically connected to the substrate via the sixth wire.
前記第６ワイヤの長さは前記第５ワイヤの長さより短く、前記第６ワイヤの直列インピーダンスの大きさは前記第５ワイヤの直列インピーダンスの大きさより小さくなっていることを特徴とする半導体装置。A semiconductor device characterized in that the length of the sixth wire is shorter than the length of the fifth wire, and the magnitude of the series impedance of the sixth wire is smaller than the magnitude of the series impedance of the fifth wire.
前記第３増幅手段は、前記第１及び前記第２領域とは異なる、前記半導体チップの前記第１面の第３領域に形成されていることを特徴とする半導体装置。 In the semiconductor device according to claim 17 ,
The third amplification means is a semiconductor device characterized in that it is formed in a third region of the first surface of the semiconductor chip, which is different from the first and second regions.
第１面と前記第１面に対向する第２面とを有し、前記第１面側に前記半導体チップが搭載された基板と、A substrate having a first surface and a second surface facing the first surface and having the semiconductor chip mounted on the first surface side.
前記半導体チップの第１面の第１領域に形成された第１及び第２電極と、The first and second electrodes formed in the first region of the first surface of the semiconductor chip,
前記第１領域に形成され、入力部が前記第１電極と電気的に接続され、出力部が前記第２電極と電気的に接続された第１増幅手段と、A first amplification means formed in the first region, the input unit is electrically connected to the first electrode, and the output unit is electrically connected to the second electrode.
前記半導体チップの前記第１面の前記第１領域とは異なる第２領域に形成された第３及び第４電極と、The third and fourth electrodes formed in a second region different from the first region of the first surface of the semiconductor chip,
前記第２領域に形成され、入力部が前記第３電極と電気的に接続され、出力部が前記第４電極と電気的に接続された第２増幅手段と、A second amplification means formed in the second region, the input unit is electrically connected to the third electrode, and the output unit is electrically connected to the fourth electrode.
前記第１電極と前記基板の前記第１面とを接続する第１ワイヤと、A first wire connecting the first electrode and the first surface of the substrate,
前記第２電極と前記基板の前記第１面とを接続する第２ワイヤと、A second wire connecting the second electrode and the first surface of the substrate,
前記第３電極と前記基板の前記第１面とを接続する第３ワイヤと、A third wire connecting the third electrode and the first surface of the substrate,
前記第４電極と前記基板の前記第１面とを接続する第４ワイヤとを具備して成り、A fourth wire connecting the fourth electrode and the first surface of the substrate is provided.
前記第２電極と前記半導体チップの一辺との間の距離は、前記第１電極と前記半導体チップの前記一辺との間の距離よりも大きく、The distance between the second electrode and one side of the semiconductor chip is larger than the distance between the first electrode and the one side of the semiconductor chip.
前記第３電極と前記半導体チップの前記一辺との間の距離は、前記第４電極と前記半導体チップの前記一辺との間の距離よりも大きく、The distance between the third electrode and the one side of the semiconductor chip is larger than the distance between the fourth electrode and the one side of the semiconductor chip.
前記第１ワイヤの前記第１電極におけるボンディング部と前記半導体チップの前記一辺との間の距離は、前記第２ワイヤの前記第２電極におけるボンディング部と前記半導体チップの前記一辺に対向する辺との間の距離よりも大きく、The distance between the bonding portion of the first wire at the first electrode and the one side of the semiconductor chip is the distance between the bonding portion of the second electrode of the second wire and the side of the semiconductor chip facing the one side. Greater than the distance between
前記第３ワイヤの前記第３電極におけるボンディング部と前記半導体チップの前記一辺に対向する辺との間の距離は、前記第４ワイヤの前記第４電極におけるボンディング部と前記半導体チップの前記一辺との間の距離よりも大きいことを特徴とする半導体装置。The distance between the bonding portion of the third wire at the third electrode and the side of the semiconductor chip facing the one side is the distance between the bonding portion of the fourth electrode of the fourth wire and the one side of the semiconductor chip. A semiconductor device characterized by being greater than the distance between.
第５及び第６電極と、With the 5th and 6th electrodes,
入力端子が前記第５電極に電気的に接続され、出力端子が前記第６電極に電気的に接続される第３増幅手段と、A third amplification means in which the input terminal is electrically connected to the fifth electrode and the output terminal is electrically connected to the sixth electrode.
前記第５電極と前記基板とを電気的に接続する第５ワイヤと、A fifth wire that electrically connects the fifth electrode and the substrate,
前記第６電極と前記基板とを電気的に接続する第６ワイヤとを更に具備して成り、A sixth wire for electrically connecting the sixth electrode and the substrate is further provided.
前記第５ワイヤの前記第５電極におけるボンディング部と前記第５ワイヤの前記基板におけるボンディング部との間の距離は、前記第６ワイヤの前記第６電極におけるボンディング部と前記第６ワイヤの前記基板におけるボンディング部との間の距離よりも大きいことを特徴とする半導体装置。The distance between the bonding portion of the fifth wire at the fifth electrode and the bonding portion of the fifth wire at the substrate is the distance between the bonding portion of the sixth wire at the sixth electrode and the substrate of the sixth wire. A semiconductor device characterized in that it is larger than the distance between the bonding portion and the bonding portion in the above.
前記第５電極と、前記第６電極と、前記第３増幅手段とは、前記第１及び前記第２領域とは異なる、前記半導体チップの前記第１面の第３領域に形成されていることを特徴とする半導体装置。The fifth electrode, the sixth electrode, and the third amplification means are formed in a third region of the first surface of the semiconductor chip, which is different from the first and second regions. A semiconductor device characterized by.
前記半導体チップの前記第１面の前記第１領域と前記第２領域との間に形成された第４領域と、A fourth region formed between the first region and the second region of the first surface of the semiconductor chip, and
前記第４領域上に形成された導体とを更に具備して成り、It is further provided with a conductor formed on the fourth region.
前記導体は基準電位に電位固定され、その底面が前記半導体チップの前記第１面の前記第１乃至第４電極の表面よりも高い位置にあることを特徴とする半導体装置。A semiconductor device characterized in that the conductor is fixed at a reference potential and its bottom surface is located at a position higher than the surface of the first to fourth electrodes on the first surface of the semiconductor chip.
前記半導体チップの前記第１面の前記第２領域と前記第３領域との間に形成された第５A fifth formed between the second region and the third region of the first surface of the semiconductor chip.
領域と、Area and 前記第５領域上に形成された導体とを更に具備して成り、It is further provided with a conductor formed on the fifth region.
前記導体は基準電位に電位固定され、その底面が前記半導体チップの前記第１面の前記第１乃至第４電極の表面よりも高い位置にあることを特徴とする半導体装置。A semiconductor device characterized in that the conductor is fixed at a reference potential and its bottom surface is located at a position higher than the surface of the first to fourth electrodes on the first surface of the semiconductor chip.
前記半導体チップの前記第１面の前記第１領域と第２領域との間に形成された第４領域と、
前記第４領域上に形成された第１の導体と、
前記半導体チップの前記第１の前記第２領域と第３領域との間に形成された第５領域と、
前記第５領域上に形成された第２の導体とを更に具備して成り、
前記第２領域は前記第１領域と前記第３領域との間に位置し、
前記第１及び第２の導体の夫々は基準電位に電位固定され、それらの底面が前記半導体チップの前記第１面の前記第１乃至前記第４電極の表面よりも高い位置にあることを特徴とする半導体装置。 In the semiconductor device according to claim 18 or 21
A fourth region formed between the first region and the second region on the first surface of the semiconductor chip, and
With the first conductor formed on the fourth region,
A fifth region formed between the first second region and the third region of the semiconductor chip, and
It is further provided with a second conductor formed on the fifth region .
The second region is located between the first region and the third region.
Each of the first and second conductors is fixed at a reference potential, and the bottom surface thereof is located at a position higher than the surface of the first to fourth electrodes on the first surface of the semiconductor chip. Semiconductor device.
第１面と前記第１面に対向する第２面とを有し、前記第１面側に前記半導体チップが搭載された基板と、A substrate having a first surface and a second surface facing the first surface and having the semiconductor chip mounted on the first surface side.
前記半導体チップの第１面の第１領域に形成された第１及び第２電極と、The first and second electrodes formed in the first region of the first surface of the semiconductor chip,
前記第１領域に形成され、入力部が前記第１電極と電気的に接続され、出力部が前記第２電極と電気的に接続された第１増幅手段と、A first amplification means formed in the first region, the input unit is electrically connected to the first electrode, and the output unit is electrically connected to the second electrode.
前記半導体チップの前記第１面の第１領域とは異なる第２領域に形成された第３及び第４電極と、The third and fourth electrodes formed in a second region different from the first region of the first surface of the semiconductor chip,
前記第２領域に形成され、入力部が前記第３電極と電気的に接続され、出力部が前記第４電極と電気的に接続された第２増幅手段と、A second amplification means formed in the second region, the input unit is electrically connected to the third electrode, and the output unit is electrically connected to the fourth electrode.
前記第１電極と前記基板の前記第１面とを接続する第１ワイヤと、A first wire connecting the first electrode and the first surface of the substrate,
前記第２電極と前記基板の前記第１面とを接続する第２ワイヤと、A second wire connecting the second electrode and the first surface of the substrate,
前記第３電極と前記基板の前記第１面とを接続する第３ワイヤと、A third wire connecting the third electrode and the first surface of the substrate,
前記第４電極と前記基板の前記第１面とを接続する第４ワイヤと、A fourth wire connecting the fourth electrode and the first surface of the substrate,
前記第１領域に形成され、接地された第５電極と、 With the fifth electrode formed in the first region and grounded,
前記第２領域に形成され、接地された第６電極と、 With the sixth electrode formed in the second region and grounded,
を具備して成り、Made up of
前記第２電極と前記半導体チップの一辺との間の距離は、前記第１電極と前記一辺との間の距離よりも大きく、The distance between the second electrode and one side of the semiconductor chip is larger than the distance between the first electrode and one side.
前記第３電極と前記一辺との間の距離は、前記第４電極と前記一辺との間の距離よりも大きく、The distance between the third electrode and the one side is larger than the distance between the fourth electrode and the one side.
前記第５電極と前記一辺との間の距離は、前記第１電極と前記一辺との間の距離よりも小さく、The distance between the fifth electrode and the one side is smaller than the distance between the first electrode and the one side.
前記第６電極と前記半導体チップの前記一辺に対向する辺との間の距離は、前記第３電極と前記対向する辺との間の距離よりも小さいことを特徴とする半導体装置。A semiconductor device characterized in that the distance between the sixth electrode and the side of the semiconductor chip facing the one side is smaller than the distance between the third electrode and the facing side.
前記第１領域に形成され、接地された第７電極を更に有し、It further has a seventh electrode formed in the first region and grounded.
前記第７電極と前記一辺との間の距離は、前記第１電極と前記一辺との間の距離よりも小さく、The distance between the 7th electrode and the one side is smaller than the distance between the first electrode and the one side.
前記第５電極と前記第７電極との間の領域を通るように前記第１ワイヤが設けられていることを特徴とする半導体装置。A semiconductor device characterized in that the first wire is provided so as to pass through a region between the fifth electrode and the seventh electrode.
前記第５、第６、及び第７電極のうちの少なくとも１つは、プローブ検査用の電極を兼ねていることを特徴とする半導体装置。A semiconductor device characterized in that at least one of the fifth, sixth, and seventh electrodes also serves as an electrode for probe inspection.
前記第１及び第２増幅手段の各々は、ゲート、ソース、ドレインを有する電界効果トランジスタを含んで成り、Each of the first and second amplification means includes a field effect transistor having a gate, a source, and a drain.
前記第５、第６、第７電極のうちの少なくとも１つは、前記ソースと電気的に接続されていることを特徴とする半導体装置。A semiconductor device characterized in that at least one of the fifth, sixth, and seventh electrodes is electrically connected to the source.
Priority Applications (13)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19080998A JP3946874B2 (en) | 1998-07-06 | 1998-07-06 | Semiconductor device |
| TW088110698A TW473882B (en) | 1998-07-06 | 1999-06-25 | Semiconductor device |
| EP06027122A EP1770777A3 (en) | 1998-07-06 | 1999-07-01 | Semiconductor device with a shielding bond wire |
| EP99112588A EP0971411B1 (en) | 1998-07-06 | 1999-07-01 | Semiconductor device |
| DE69935182T DE69935182T2 (en) | 1998-07-06 | 1999-07-01 | A semiconductor device |
| US09/345,505 US6330165B1 (en) | 1998-07-06 | 1999-07-01 | Semiconductor device |
| US09/970,668 US6489680B2 (en) | 1998-07-06 | 2001-10-05 | Semiconductor device |
| US10/291,840 US6943441B2 (en) | 1998-07-06 | 2002-11-12 | Semiconductor device |
| US11/194,701 US7068521B2 (en) | 1998-07-06 | 2005-08-02 | Semiconductor device |
| US11/451,579 US20070001300A1 (en) | 1998-07-06 | 2006-06-13 | Semiconductor device |
| US11/905,421 US7525813B2 (en) | 1998-07-06 | 2007-10-01 | Semiconductor device |
| US12/394,421 US7817437B2 (en) | 1998-07-06 | 2009-02-27 | Semiconductor device |
| US12/787,154 US8295057B2 (en) | 1998-07-06 | 2010-05-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19080998A JP3946874B2 (en) | 1998-07-06 | 1998-07-06 | Semiconductor device |
Related Child Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006339318A Division JP2007074001A (en) | 2006-12-18 | 2006-12-18 | Semiconductor device |
| JP2006339316A Division JP2007074000A (en) | 2006-12-18 | 2006-12-18 | Semiconductor device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2000021926A JP2000021926A (en) | 2000-01-21 |
| JP2000021926A5 true JP2000021926A5 (en) | 2005-10-27 |
| JP3946874B2 JP3946874B2 (en) | 2007-07-18 |
Family
ID=16264117
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19080998A Expired - Lifetime JP3946874B2 (en) | 1998-07-06 | 1998-07-06 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3946874B2 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW594888B (en) | 2001-09-05 | 2004-06-21 | Hitachi Ltd | Semiconductor device and manufacturing method thereof and wireless communication device |
| EP1941546A2 (en) * | 2005-10-19 | 2008-07-09 | Nxp B.V. | Device comprising an element with electrodes coupled to connections |
| KR100950511B1 (en) | 2009-09-22 | 2010-03-30 | 테세라 리써치 엘엘씨 | Microelectronic assembly with impedance controlled wirebond and conductive reference element |
| KR100935854B1 (en) * | 2009-09-22 | 2010-01-08 | 테세라 리써치 엘엘씨 | Microelectronic assembly with impedance controlled wirebond and reference wirebond |
| US9136197B2 (en) | 2010-09-16 | 2015-09-15 | Tessera, Inc. | Impedence controlled packages with metal sheet or 2-layer RDL |
| US8853708B2 (en) | 2010-09-16 | 2014-10-07 | Tessera, Inc. | Stacked multi-die packages with impedance control |
| US8786083B2 (en) | 2010-09-16 | 2014-07-22 | Tessera, Inc. | Impedance controlled packages with metal sheet or 2-layer RDL |
| US8581377B2 (en) | 2010-09-16 | 2013-11-12 | Tessera, Inc. | TSOP with impedance control |
-
1998
- 1998-07-06 JP JP19080998A patent/JP3946874B2/en not_active Expired - Lifetime
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