JP2000021814A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To compensate for an insulated part generated when the titanium silicide film of a C54 phase is manufactured only by means of adding a simple process in MOSFET of silicide structure, using titanium silicide of the C54 phase which is a stable phase. SOLUTION: When titanium silicide films 106-108 of C54 phases are formed in MOSFET in a silicide process, a part of the titanium silicide film 108 is interrupted through aggregation, and a polysilicon forming a gate electrode 104 is exposed. When a titanium film is formed on the entire face of a wafer and heat-treatment is executed, the titanium silicide film 108 of the C54 phase does not react with the titanium film, but polysilicon exposed in the insulated part reacts with the titanium film and titanium silicide of a C49 phase is obtained. Thereafter, a C49 phase titanium silicide film 109 for compensating insulating can be obtained by removing the titanium film.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having a salicide structure and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, MOS (Metal Oxide Semiconduct)
or) FET (Field Effect Transistor)
In general, a gate electrode is formed of polycrystalline silicon, and a source region and a drain region are formed by ion-implanting a high-concentration impurity into a single-crystal silicon surface of a substrate. However, such MOSFETs
Since the resistance of the gate electrode, the source, and the drain is large, the signal transmission delay is increased, and it has not been possible to sufficiently meet the demand for high-speed operation of the device.

On the other hand, in recent years, a number of techniques (salicide techniques) for reducing the resistance by silicidizing the surfaces of the gate electrode, the source region, and the drain region formed as described above have been proposed. MO with salicide structure
As a silicide used for an SFET, titanium silicide is particularly promising. Titanium silicide is
This is because it has advantages such as a very low specific resistance of 13 μΩcm, a low-cost material, and high thermal stability. In fact, in recent years, gate lengths of 0.25
In a semiconductor element for high-speed application at the μm level, it is common to use a salicide structure MOSFET using titanium silicide.

Documents relating to the salicide technique using titanium silicide include the following, for example.

(Literature I) "Measures against fine wire effect of salicide structure" Kenichi Goto, Semiconductor World 1995.12 p1
56-160 (Reference II) 'A Thermally Stable Ti-W Salicide for D
eep-Submicron Logic with Embedded DRAM'K.Fujii e
t.al., IEDM1996, p.451-454

[0006]

A method of manufacturing a MOSFET having a salicide structure using titanium silicide will be described below with reference to FIG.

First, a field oxide film 1001 is formed on a silicon wafer 1000 in accordance with a normal MOSFET manufacturing process.
2. A MOSFET structure including a drain region 1003, a gate oxide film 1004, a gate electrode 1005, and sidewalls 1006 is formed. Then, for example, silicon or arsenic is ion-implanted to form the source region 10.
02, drain region 1003 and gate electrode 1005
Surface regions 1002a, 1003a, and 1005a are made amorphous. This amorphization is a process for facilitating the phase transition of titanium silicide from the C49 phase to the C54 phase in a later step, and is called a preamorphization process. After that, a titanium film 1007 is formed over the entire surface of the wafer 1000 by sputtering or the like (see FIG. 12A).

Next, rapid heating (RTA; Rapid Thermal)
Anneal) method, for example, in a nitrogen gas atmosphere,
The wafer 1000 is subjected to a heat treatment at about 700 ° C. or less. Accordingly, a reaction occurs in a region where the titanium film 1007 and silicon are in contact with each other, and C49-phase titanium silicide films 1002b, 1003b, and 1005b, which are metastable phases, are formed (see FIG. 12B). At this time, the surface of the titanium film 1007 is nitrided,
Is also formed.

Subsequently, after removing the titanium film 1007 and the titanium nitride film 1008 by wet etching or the like, the wafer 1000 is subjected to a heat treatment at about 800 ° C. in a nitrogen gas atmosphere, for example, by a rapid heating method or the like. . Thereby, the films 1002b, 1003b, 1005
phase transition of titanium silicide b to form a stable phase C
The 54-phase titanium silicide films 1002c, 1003c,
1005c can be obtained (see FIG. 12C).

However, as disclosed in the above-mentioned Document I, in the MOSFET described with reference to FIG. 12, aggregation occurs when titanium silicide undergoes a phase transition from the C49 phase to the C54 phase, and the There is a disadvantage that the titanium silicide pattern on the electrode is easily broken.

FIG. 10 conceptually shows a state of aggregation generated in titanium silicide of C54 phase.
(A) shows the case where the gate length is 0.1 μm, and (B) shows the case where the gate length is 0.2 μm.

As shown in FIG.
When aggregation occurs in the four-phase titanium silicide film 1005c, a break 1101 is likely to occur.

FIG. 11 shows the MOSFET described with reference to FIG.
Is a graph showing the relationship between the sheet resistance of the gate electrode (resistance when a signal is propagated in the direction indicated by the arrow S in FIG. 10) and the element size, with the vertical axis representing the sheet resistance and the horizontal axis representing the gate length. is there.

As can be seen from the figure, the gate length is 0.2 μm.
When it is less than m, the sheet resistance of the gate electrode increases rapidly. This is because when the gate length is 0.2 μm or less, disconnection of the gate electrode is likely to occur.

When a break occurs in the gate electrode, the effect of employing the salicide structure is lost, and the resistance of the gate electrode, the source region, and the drain region becomes equal to the resistance value when titanium silicide is not formed. Here, the resistance value of the gate electrode and the like when titanium silicide is not formed differs depending on the impurity concentration, but is usually 400 μΩ.
cm. For this reason, when a break occurs in the gate electrode, the resistance of the gate electrode increases at this break portion (that is, increases from 13 μΩcm to about 400 μΩcm), so that the delay in signal transmission also increases. Is remarkable. Such an increase in malfunctions causes a significant decrease in the reliability and yield of the semiconductor device.

For the reasons described above, conventionally, a salicide structure using titanium silicide has a gate width of 0.1 mm.
It was thought that MOSFETs of 2 μm or less could not be used.

[0017]

(1) A semiconductor device according to a first aspect of the present invention includes a conductive pattern formed by performing a phase transition from a metastable phase silicide to a stable phase silicide; And a buried portion formed by burying a metastable phase silicide in a discontinuous portion of the conductive pattern generated in the above.

According to such an apparatus, it is possible to compensate for the disconnection of the conductive pattern.

(2) In the method of manufacturing a semiconductor device according to the second invention, a first step of forming a pattern composed of metastable phase silicide and a phase transition of metastable phase silicide to stable phase silicide are provided. And a third step of forming a buried portion by burying a metastable phase silicide at a break in the conductive pattern generated at the time of phase transition.

According to such a method, since the silicide can be buried in the cut portion without using a mask, the cut of the conductive pattern can be compensated only by a simple process.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the size, shape, and arrangement of each component are only schematically shown to an extent that the present invention can be understood, and numerical conditions described below are merely examples. Please understand that.

First Embodiment A first embodiment of the present invention will be described by taking as an example a case where a salicide structure of a MOSFET is formed using titanium silicide.

FIG. 1 is a perspective view schematically showing the structure of a semiconductor device according to this embodiment.

As shown in FIG. 1, the silicon wafer 10
The source region 101 and the drain region 102 are formed on the surface of the zero by introducing impurities by ion implantation or the like. On the wafer 100, a gate electrode 10 of polycrystalline silicon is interposed via a gate oxide film 103.
4 and a side wall 105 are formed. Further, on the surfaces of the source region 101, the drain region 102 and the gate electrode 104, titanium silicide films 106, 107 and 108 of C54 phase, which is a stable phase, are formed.

The C49 phase titanium silicide film 109, which is a metastable phase, is buried in the discontinuity generated in the C54 phase titanium silicide film 108 on the gate electrode 104. This break occurs in the step of forming the C54 phase titanium silicide film 108, as described later.

FIG. 2 is a process sectional view for explaining a method of manufacturing a semiconductor device according to this embodiment.

First, in accordance with a normal MOSFET manufacturing process, a silicon wafer 100 is provided with a source region 101, a drain region 102, a gate oxide film 103, a gate electrode 104 and a sidewall 105.
An OSFET structure is formed. Then, for example, by ion-implanting silicon or arsenic, the source region 101,
The surface region of the drain region 102 and the gate electrode 104 is subjected to the same pre-amorphization treatment as in the related art (see FIG. 10).

A titanium film 201 is formed on the entire surface of the wafer 100 by using a technique such as sputtering.

Next, the wafer 100 is subjected to a heat treatment at about 700 ° C. or less, for example, in a nitrogen gas atmosphere using an RTA method or the like. As a result, a reaction occurs in a region where the titanium film 201 and silicon are in contact with each other, and the metastable phase C4
Nine-phase titanium silicide films 202, 203, and 204 are formed (see FIG. 2A). At this time, the surface of the titanium film 201 is nitrided, and a titanium nitride 205 is also formed.

The titanium film 201 and the titanium nitride film 205 are removed by wet etching or the like.

The wafer 100 is subjected to a heat treatment at about 800 ° C., for example, in a nitrogen gas atmosphere using a rapid heating method or the like. As a result, the titanium silicide of the films 202, 203 and 204 undergoes a phase transition to form the titanium silicide films 106, 107 and 108 of the C54 phase which is a stable phase (the film 108 is not shown). Here, at the time of this phase transition, the silicide film 10 formed on the gate electrode 104 is formed.
8 aggregates. Then, one or a plurality of discontinuous portions 108a are generated in the silicide film 108 due to the aggregation (see FIG. 2B). As shown in FIG. 2B, the polysilicon forming the gate electrode 104 is exposed at the disconnection point 108a.

Subsequently, a titanium film 206 is formed again on the entire surface of the wafer 100 by using a technique such as sputtering (see FIG. 2C).

Then, the wafer 100 is subjected to a heat treatment at about 700 ° C. or less, for example, in a nitrogen gas atmosphere using an RTA method or the like. As a result, the region where the polysilicon and the titanium film 206 are in contact with each other, that is,
The reaction does not take place in other regions because stable C54 phase titanium silicide is present in other regions. Accordingly, the titanium silicide film 109 of the C49 phase, which is a metastable phase, is formed only at the cut-off portion 108a even though the mask is not used. At this time, titanium nitride 208 is formed on the surface of the titanium film 208 (see FIG. 2D).

Finally, the MOSFET as shown in FIG. 1 is completed by removing the titanium film 206 and the titanium nitride film 207 by wet etching or the like.

In the MOSFET shown in FIG. 1, a signal is propagated in the direction indicated by S in the figure (or the opposite direction). Here, if the C49-phase titanium silicide film 109 is not formed at the cut-off point 108a (see FIG. 2B) (that is, in the case of the prior art), a signal is supplied to the polysilicon (as described above) near the cut-off point 108a. The gate electrode 10 having a normal specific resistance of about 400 μΩcm)
4 will be propagated. On the other hand, 10
When the titanium silicide film 109 is formed on 8a,
The specific resistance of this portion is the specific resistance of the C49 phase titanium silicide, which is about 40 μΩcm.

As described above, according to this embodiment, the MOSFET having a very short gate length (ie, a MOSFET which is disconnected when a C54 phase titanium silicide is formed).
OSFET) can also adopt a salicide structure using titanium silicide. Therefore, according to this embodiment, the reliability and yield of a highly integrated semiconductor device can be improved.

Further, in the method of manufacturing the MOSFET shown in FIG. 2, as described above, after the titanium silicide film 109 is formed on the entire surface of the wafer 100, the entire wafer 100 is heated only, so that Then, a C49-phase titanium silicide film 109 can be formed (the above process). That is, according to this embodiment, a mask is not required when forming the titanium silicide film 109 for embedding in the cutoff portion 108a.

Therefore, according to this embodiment, the process for compensating for the cutoff point is simplified.

In this embodiment, the present invention is applied to M
Although the case where the present invention is applied to the gate of the OSFET has been described as an example, it goes without saying that the present invention can be applied to other elements and wiring patterns in a semiconductor integrated circuit as long as a salicide process can be used.

The present invention can be applied to a salicide process using a silicide other than titanium silicide.
Of course.

Second Embodiment A second embodiment of the present invention will be described by taking as an example a case where a salicide structure of a MOSFET is formed using titanium silicide.

FIG. 3 is a perspective view schematically showing the structure of the semiconductor device according to this embodiment. In FIG.
The components denoted by the same reference numerals as those in FIG. 1 indicate the same components as those in FIG.

The MOSFET according to this embodiment is:
A titanium silicide film 301 to which an impurity such as tungsten is added is used as a film for embedding a discontinuous portion of the C54 phase titanium silicide film 108. The point of using a C49 phase which is a metastable phase as the titanium silicide film 301 is the same as in the case of the above-described first embodiment.

FIG. 4 is a process sectional view for illustrating the method for manufacturing the semiconductor device according to the present embodiment.

First, similarly to the first embodiment, a source region 101 and a drain region 10 are formed on a silicon wafer 100 in accordance with a normal MOSFET manufacturing process.
2. After forming a MOSFET structure including a gate oxide film 103, a gate electrode 104 and a sidewall 105, a pre-amorphization process is performed on the source region 101, the drain region 102, and the surface region of the gate electrode 104.

In the same manner as in the first embodiment, a titanium film is formed on the entire surface of
By performing the following heat treatment, a C49 phase titanium silicide film is formed, and then the titanium film and the titanium nitride film are removed. Then, by subjecting the wafer 100 to heat treatment under the same conditions as those in the first embodiment, the C49 phase titanium silicide undergoes a phase transition, and the C54 phase titanium silicide films 106 and 10 which are stable phases are formed.
7, 108 are formed. During this phase transition, the silicide film 108 formed over the gate electrode 104 is aggregated, so that one or a plurality of discontinuous portions 108a are generated in the silicide film 108 (see FIG. 4A).

Subsequently, a titanium film 401 is formed on the entire surface of the wafer 100 by using a sputtering method.
(B)). In this embodiment, a titanium film to which tungsten is added is used on the entire surface of the wafer 100 by using titanium to which only a few atomic concentrations of tungsten are added as a target used in this sputtering.
01 is formed.

Then, by subjecting the wafer 100 to heat treatment under the same conditions as in the first embodiment, a C49-phase titanium silicide film 301 to which only a few atomic concentrations of tungsten are added is formed at the cut-off portion 108a. (FIG. 4
(C)). In this embodiment, as in the first embodiment described above, the disconnection portion 108a can be formed without using a mask.
Only the titanium silicide film 301 can be formed. Note that a titanium nitride film 402 is also formed by this heat treatment.

Finally, by removing the titanium film 401 and the titanium nitride film 402 by wet etching or the like, the MOSFET as shown in FIG. 3 is completed.

As described above, the MO according to this embodiment is
In the SFET, tungsten is added to the C49-phase titanium silicide film 301 formed to bury the cut-off portion 108a. Thus, the titanium silicide film 301, which is a metastable phase (ie, C49 phase) film
To increase the thermal stability of the stable phase (ie, C54
Phase). As described in the above-mentioned reference II, when a few atomic concentration of tungsten is added to titanium silicide of C49 phase,
Even at a high temperature up to about 40 ° C., no phase transition to the C54 phase occurs. Therefore, by adding tungsten,
It is possible to prevent the titanium silicide film 301 from undergoing a phase transition to the C54 phase and aggregating due to aggregation again. That is, according to this embodiment, the MOS
The reliability and yield of the FET can be further improved as compared with the case of the first embodiment.

By forming the titanium silicide film 301, the resistance during signal propagation is reduced,
Reliability and yield can be improved,
Further, since the metastable phase silicide is formed at the break point of the stable phase silicide, a mask is not required and the process can be simplified, as in the case of the above-described first embodiment.

Further, the present invention can be applied not only to the gate of the MOSFET but also to a salicide process using a silicide other than titanium silicide.
This is the same as in the first embodiment.

In this embodiment, tungsten is used as an impurity of the metastable phase silicide film buried in the discontinuous portion. However, any other material that can increase the thermal stability of the metastable phase silicide film can be used. May be added.

Third Embodiment A third embodiment of the present invention will be described by taking as an example a case where a salicide structure of a MOSFET is formed using titanium silicide.

The structure of the MOSFET according to this embodiment is the same as that of the second embodiment (see FIG. 3). That is, a titanium silicide film 301 to which an impurity such as tungsten is added is used as a film for filling the discontinuous portion of the C54 phase titanium silicide film 108.

FIG. 5 is a process sectional view for illustrating the method for manufacturing the semiconductor device according to this embodiment.

First, similarly to the second embodiment, a source region 101 and a drain region 10 are formed on a silicon wafer 100 in accordance with a normal MOSFET manufacturing process.
2. After forming a MOSFET structure including a gate oxide film 103, a gate electrode 104 and a sidewall 105, a pre-amorphization process is performed on the source region 101, the drain region 102, and the surface region of the gate electrode 104.

In the same manner as in the first embodiment, a titanium film is formed on the entire surface of
By performing the following heat treatment, a C49 phase titanium silicide film is formed, and then the titanium film and the titanium nitride film are removed. Then, by subjecting the wafer 100 to heat treatment under the same conditions as those in the first embodiment, the C49 phase titanium silicide undergoes a phase transition, and the C54 phase titanium silicide films 106 and 10 which are stable phases are formed.
7, 108 are formed. At the time of this phase transition, the silicide film 108 formed over the gate electrode 104 aggregates, so that one or a plurality of discontinuous portions 108a are generated in the silicide film 108 (see FIG. 5A).

Subsequently, using a sputtering method or the like,
A titanium film 501 (see FIG. 5B) is formed over the entire surface of the wafer 100. In this embodiment, unlike the above-described second embodiment, tungsten (that is, one to which no impurity is added) is used as a target used in this sputtering.

Next, an impurity such as tungsten is ion-implanted on the entire surface of the titanium film 501. Thus, a titanium film 502 to which tungsten is added can be formed over the entire surface of the wafer 100 (see FIG. 5C).

Then, by subjecting the wafer 100 to heat treatment under the same conditions as in the above-described embodiments, a C49-phase titanium silicide film 301 to which only a few atomic concentrations of tungsten are added is formed at the cut-off portion 108a. (See FIG. 5D). In this embodiment, as in the above-described first embodiment, the cut-off portion 108 can be formed without using a mask.
The titanium silicide film 301 can be formed only on a. Note that this heat treatment allows the titanium nitride film 503 to be formed.
Is also formed.

Finally, the MOSFET as shown in FIG. 3 is completed by removing the titanium film 502 and the titanium nitride film 503 by wet etching or the like.

As described above, the MOSFET as shown in FIG. 3 can also be manufactured by ion-implanting impurities after the formation of the titanium film 501 (the above process).

Since the titanium film is formed first when forming the filling film, the titanium target used in the first titanium film forming step (the above step) can be used as it is. In addition, the manufacturing cost can be reduced.

By forming the titanium silicide film 301 and implanting an impurity such as tungsten into the titanium silicide film 301, the MOSFE is formed.
The third advantage is that the reliability of T and the yield can be improved, and the formation of metastable phase silicide at the break point of the stable phase silicide eliminates the need for a mask and simplifies the process. This is the same as in the embodiments and the like.

In addition, the present invention can be applied not only to the gate of the MOSFET, but also to the salicide process using silicide other than titanium silicide, and to the point that impurities other than tungsten can be used. Is the same as

Fourth Embodiment A fourth embodiment of the present invention will be described by taking as an example a case where a salicide structure of a MOSFET is formed using titanium silicide.

FIG. 6 shows a MOSF according to this embodiment.
FIG. 3 is an exploded perspective view schematically showing a structure of the ET. 6, the components denoted by the same reference numerals as those in FIG. 1 indicate the same components as those in FIG.

In the MOSFET according to this embodiment, the thickness t of the C54 phase titanium silicide
_C54 and a C49-phase titanium silicide film 601 for embedding a discontinuity in the C54-phase titanium silicide film 108
The relationship with the thickness t _C49 is _defined as t _C49 ≧ 3t _C54 (1).

FIG. 7 is a process sectional view for illustrating the method of manufacturing the semiconductor device according to the present embodiment.

First, similarly to the first embodiment, a source region 101 and a drain region 10 are formed on a silicon wafer 100 in accordance with a normal MOSFET manufacturing process.
2. After forming a MOSFET structure including a gate oxide film 103, a gate electrode 104 and a sidewall 105, a pre-amorphization process is performed on the source region 101, the drain region 102, and the surface region of the gate electrode 104.

As in the first embodiment, a titanium film is formed on the entire surface of the wafer 100,
By performing the following heat treatment, a C49 phase titanium silicide film is formed, and then the titanium film and the titanium nitride film are removed. Then, by subjecting the wafer 100 to heat treatment under the same conditions as those in the first embodiment, the C49 phase titanium silicide undergoes a phase transition, and the C54 phase titanium silicide films 106 and 10 which are stable phases are formed.
7, 108 are formed. At the time of the phase transition, the silicide film 108 formed over the gate electrode 104 is aggregated, so that one or a plurality of discontinuous portions 108a are generated in the silicide film 108 (see FIG. 7A).

Subsequently, a titanium film 701 is formed on the entire surface of the wafer 100 by using a sputtering method.
(B)).

Then, by subjecting the wafer 100 to heat treatment under the same conditions as in the first embodiment, a C49-phase titanium silicide film 601 is formed at the cut-off portion 108a (see FIG. 7C). At this time, by appropriately setting the conditions of the heat treatment (for example, the heating time), the titanium silicide film 601 having a film thickness satisfying the above-described formula (1) can be formed. Note that a titanium nitride film 702 is also formed by this heat treatment.

Finally, the MOSFET shown in FIG. 6 is completed by removing the titanium film 701 and the titanium nitride film 702 by wet etching or the like.

In this embodiment, the thickness t _C49 of the C49 phase titanium silicide film 601 is set to be three times or more the thickness t _C54 of the C54 phase titanium silicide film 108. As described above, the specific resistance of the C49 phase titanium silicide is 40 μΩc.
m, and the specific resistance of the C54 phase titanium silicide is about 13 μΩcm. Therefore, t _C49 ≧ 3
By setting t _C54 , the resistance of the C49 phase titanium silicide film 601 in the propagation direction of the signal S (see FIG. 1) can be equal to or higher than that of the C54 phase titanium silicide film 108. That is, according to this embodiment, the reduction in resistance due to the embedding of the C49 phase titanium silicide film 601 can be reduced to almost zero. Therefore, the signal propagation speed of the gate electrode can be further increased, and the reliability and yield of the MOSFET can be further improved.

Here, when the C49-phase titanium silicide film 601 is formed thick as in this embodiment, it is desirable that this titanium silicide film 601 does not reach the gate oxide film 103. That is, when the MOSFET is formed so as to satisfy the above-described expression (1), it is desirable that the following expression (2) is also satisfied in addition to the expression (1). Note that, in equation (2), t
_G is the thickness of the polysilicon gate electrode 104.

T _C49 ≧ t _C54 + t _G (2) When the titanium silicide film 601 reaches the gate oxide film 103 (that is, when the above equation (2) is not satisfied), the flatness of the gate electrode 104 is reduced. The band potential may fluctuate and the threshold voltage of the MOSFET may change. In addition, when the titanium silicide film 601 is formed, the gate oxide film 103 may be damaged, and the MOS transistor may not operate normally. On the other hand, when the above equation (2) is satisfied, there is no possibility that such an inconvenience occurs.

In this embodiment, the impurity such as tungsten is not added to the C49 phase titanium silicide film 601. However, in the second embodiment or the third embodiment,
The impurity may be added using the same method as that of the embodiment.

By forming the titanium silicide film 301 and injecting impurities such as tungsten into the titanium silicide film 301, the reliability and yield of the MOSFET can be improved. Since a metastable phase silicide is formed in the first embodiment, a mask is not required and the process can be simplified, as in the above-described embodiments.

In addition, the present invention can be applied not only to MOSFET gates, but also to salicide processes using silicides other than titanium silicide, and to the point that impurities other than tungsten can be used. Is the same as

Fifth Embodiment A fifth embodiment of the present invention will be described with reference to an example in which a salicide structure of a MOSFET is formed using titanium silicide.

FIG. 8 shows a MOSF according to this embodiment.
FIG. 3 is an exploded perspective view schematically showing a structure of the ET. 8, the components denoted by the same reference numerals as those in FIG. 1 indicate the same components as those in FIG.

[0084] Even MOSFET according to this embodiment, as in the fourth embodiment described above, the relationship between the thickness t _C49 thickness t _C54 and C49 phase titanium silicide film 801 of the C54 phase titanium silicide film 108 The above expression (1) is satisfied.

On the other hand, the titanium silicide film 80 of the C49 phase
1 is the upper surface 10 of the C54 phase titanium silicide film 108
The fourth embodiment is different from the fourth embodiment in that it is formed to protrude from 8a. By employing such a structure, the possibility that the C49-phase titanium silicide film 801 reaches the gate oxide film 103 in the manufacturing stage is reduced.

FIG. 9 is a process sectional view for illustrating the method for manufacturing the semiconductor device according to the present embodiment.

First, as in the above-described embodiments, the source region 101 and the drain region 10 are formed on the silicon wafer 100 in accordance with a normal MOSFET manufacturing process.
2. After forming a MOSFET structure including a gate oxide film 103, a gate electrode 104 and a sidewall 105, a pre-amorphization process is performed on the source region 101, the drain region 102, and the surface region of the gate electrode 104.

As in the first embodiment, a titanium film is formed on the entire surface of wafer 100. And 700
By performing a heat treatment at a temperature of not more than about ° C., titanium silicide films 902, 903, and 904 of the C49 phase are formed, and then the titanium film and the titanium nitride film are removed.

Subsequently, in this embodiment, for example, C
By a VD (Chemical Vaper Deposition) method or the like, a thin (for example, 2-3 nm) insulating film 90 is formed on the entire surface of the wafer 100.
1 is formed of, for example, silicon nitride (FIG. 9)
(A)).

By subjecting the wafer 100 to a heat treatment at, for example, about 800 ° C. in a nitrogen gas atmosphere, the C49 phase titanium silicide undergoes a phase transition, and the stable phase C5
Four-phase titanium silicide films 106, 107 and 108 are formed (film 108 is not shown). In this embodiment,
When the silicide film 108 aggregates during this phase transition to generate one or a plurality of cut portions 108a, the thin silicon nitride film 901 is also cut, and the polysilicon of the gate electrode 104 is exposed (FIG. 9B). reference).

Next, in this embodiment, the polysilicon film 905 is formed only in the region where the polysilicon is exposed, that is, only in the cutoff portion 108a, by the selective growth method using the silicon nitride film 901. Here, for the reason described later, the thickness of the polysilicon film 905 is set to be equal to the thickness of the titanium silicide film 801 formed in a later step.
It is desirable that the thickness be equal to or more than two-thirds of the film thickness (see FIG. 8).

[0092] The wafer 10 is
Then, a titanium film 903 is formed over the entire surface of the substrate 0 (see FIG. 7C).

The wafer 100 is subjected to a heat treatment at about 700 ° C. or less, for example, in a nitrogen gas atmosphere by using the RTA method or the like. As a result, the selectively grown polysilicon film 905 reacts with the titanium film 906 to form a C49 phase titanium silicide film 801 which is a metastable phase (see FIG. 7D). At this time, by appropriately setting the conditions of the heat treatment (for example, the heating time), the titanium silicide film 801 having a film thickness satisfying the above-described formula (1) can be formed. In this embodiment, as in each of the above-described embodiments, the disconnection portion 108a can be formed without using a mask.
Only the titanium silicide film 801 can be formed.

Finally, the MOSFET as shown in FIG. 8 is completed by removing the titanium film 906 and the titanium nitride film (not shown) by wet etching or the like.

As described above, the MOS according to this embodiment
In the FET, the C49 phase titanium silicide film 801 is
It is formed so as to project from the upper surface 108a of the titanium silicide film 108 of the C54 phase. This reduces the possibility that the C49-phase titanium silicide film 801 reaches the gate oxide film 103 in the manufacturing stage.
The yield and reliability of the OSFET can be improved.

In this embodiment, as described above, it is desirable that the thickness of the polysilicon film 905 is not less than two thirds of the thickness of the titanium silicide film 801 to be formed thereafter. Since the ratio of titanium to silicon when titanium silicide is formed is 1: 2, the thickness of the titanium silicide film 801 is 1.5 times the thickness of the polysilicon film 905. Therefore, the polysilicon film 905
By setting the thickness of the film to two thirds or more of the thickness of the titanium silicide film 801, the possibility that the titanium silicide film 801 reaches the gate oxide film 103 can be further reduced.

In the manufacturing method according to this embodiment, a polysilicon film 905 is formed by selective growth using a thin silicon nitride film 901, and a C49-phase titanium silicide film 801 is formed from the polysilicon film 905. did. Thus, the titanium silicide film 801 can be formed only by adding a simple process.

The thickness t _C49 of the C49 phase titanium silicide film 801 is changed to the thickness t of the C54 phase titanium silicide film 108.
_The point that the propagation speed of the signal can be increased because it is three times or more of _C54 is the same as in the above-described fourth embodiment.

In this embodiment, the impurity such as tungsten is not added to the C49-phase titanium silicide film 801. However, the impurity is added by applying the second embodiment or the third embodiment described above. It may be that.

By forming the titanium silicide film 801 and injecting impurities such as tungsten into the titanium silicide film 801, the reliability and the yield of the MOSFET can be improved. Since a metastable phase silicide is formed in the first embodiment, a mask is not required and the process can be simplified, as in the above-described embodiments.

The present invention can be applied not only to MOSFET gates, but also to salicide processes using silicides other than titanium silicide, and to the point that impurities other than tungsten can be used, as in the above embodiments. It is.

[0102]

As described above in detail, according to the present invention, a metastable phase silicide is formed at a break point in a conductive pattern generated when a metastable phase silicide is transformed into a stable phase silicide. Since the embedding is performed, it is possible to compensate for the disconnection of the conductive pattern only by adding a simple process.

[Brief description of the drawings]

FIG. 1 is a perspective view schematically showing a structure of a semiconductor device according to a first embodiment.

FIG. 2 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment.

FIG. 3 is a perspective view schematically showing a structure of a semiconductor device according to a second embodiment and a third embodiment.

FIG. 4 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the second embodiment.

FIG. 5 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the third embodiment.

FIG. 6 is an exploded perspective view schematically showing a structure of a semiconductor device according to a fourth embodiment.

FIG. 7 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the fourth embodiment.

FIG. 8 is an exploded perspective view schematically showing a structure of a semiconductor device according to a fifth embodiment.

FIG. 9 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the fifth embodiment.

FIG. 10 is a sectional process view illustrating a conventional method for manufacturing a semiconductor device.

FIG. 11 is a conceptual diagram for explaining a defect of a conventional semiconductor device.

FIG. 12 is a graph for explaining a defect of a conventional semiconductor device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 silicon wafer 101 source region 102 drain region 103 gate oxide film 104 gate electrode 105 sidewalls 106, 107, 108 titanium silicide film 108 C54 phase titanium silicide film 109 C49 phase titanium silicide film

Claims (20)

[Claims] 1. A conductive pattern formed by performing a phase transition from a metastable phase silicide to a stable phase silicide; and a metastable phase formed at a break point of the conductive pattern generated during the phase transition. And a buried portion formed by burying the silicide. 2. The semiconductor device according to claim 1, wherein the silicide is titanium silicide, the metastable phase is a C49 phase, and the stable phase is a C54 phase. 3. The semiconductor device according to claim 1, wherein the conductive pattern is an electrode pattern formed on a polycrystalline silicon gate electrode of a MOS field effect transistor by a salicide process. 4. The semiconductor device according to claim 1, wherein the buried portion is formed of metastable phase titanium silicide to which an impurity for suppressing phase transition is added. . 5. The semiconductor device according to claim 4, wherein said impurity is tungsten. 6. The semiconductor device according to claim 2, wherein the thickness of the buried portion is three times or more the thickness of the conductive pattern. 7. The semiconductor device according to claim 3, wherein a thickness of said buried portion is smaller than a thickness of said polycrystalline silicon gate electrode. 8. The semiconductor device according to claim 6, wherein said buried portion is formed so as to protrude from a surface of said conductive pattern. 9. A first step of forming a pattern composed of a metastable phase silicide, a second step of forming a conductive pattern by performing a phase transition of the metastable phase silicide to a stable phase silicide, By embedding a metastable phase silicide at the break point of the conductive pattern generated during the phase transition,
A method of manufacturing a semiconductor device, comprising: a third step of forming an embedded portion. 10. The method according to claim 9, wherein the silicide is titanium silicide, the metastable phase is a C49 phase, and the stable phase is a C54 phase. 11. The first step comprises: amorphizing a surface of a source region and a drain region of a MOS field effect transistor and a surface of a polycrystalline silicon gate electrode; depositing titanium on a surface of the field effect transistor; The method according to claim 9, wherein the method is a step of forming titanium silicide by the method. 12. The method according to claim 9, wherein said third step is a step of forming said buried portion by metastable phase titanium silicide to which impurities for suppressing phase transition are added. A method for manufacturing a semiconductor device according to any one of the above. 13. The method according to claim 12, wherein the third step is a step of depositing titanium by sputtering using the titanium to which the impurity is added as a target, and then converting the titanium into a silicide by a heat treatment. 13. The method for manufacturing a semiconductor device according to item 5. 14. The manufacturing of a semiconductor device according to claim 12, wherein in the third step, after depositing titanium, introducing the impurity into the titanium, the titanium is silicided by a heat treatment. Method. 15. The method of manufacturing a semiconductor device according to claim 12, wherein said impurity is tungsten. 16. The structure according to claim 10, wherein the thickness of the buried portion is at least three times the thickness of the conductive pattern.
13. The method for manufacturing a semiconductor device according to item 5. 17. The method according to claim 11, wherein the thickness of the buried portion is smaller than the thickness of the polycrystalline silicon gate electrode. 18. The method according to claim 16, wherein the buried portion is formed so as to protrude from a surface of the conductive pattern. 19. The buried portion is formed by depositing polysilicon protruding from the surface of the conductive pattern at the discontinuous portion, further depositing titanium, and then performing a heat treatment. A method for manufacturing a semiconductor device according to claim 16. 20. The method according to claim 19, wherein the deposition of the polysilicon is performed by selective growth using a silicon nitride film formed on a surface of the conductive pattern.