JP2000021175A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory for accelerating an accessing speed by inactivating a sense amplifier of a memory block not accessed and a reference voltage generator to reduce dissipation power, and activating the sense amplifiers and the reference voltage generators of all the blocks at the time of switching the blocks. SOLUTION: The semiconductor memory comprises memory blocks 101, 102 having general purpose address areas 101A, 102A, specific address areas 101B, 102B and memory block selecting terminals CS1, CS2 of terminals for selecting the memory block, and an address bus for supplying addresses to the blocks 101, 102. At the time of transiting addresses from an address bus to specific addresses, the areas 101B, 102B are accessed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device, in which a specific address area is set in each of a plurality of memory blocks constituting the semiconductor memory device, and the address transitions between memory blocks. The present invention relates to a semiconductor memory device in which an address transitions via an area.

[0002]

2. Description of the Related Art In recent years, the storage capacity of a semiconductor memory mounted on a microcomputer has been increasing year by year. If the storage capacity of the semiconductor memory is simply increased by a high-speed microcomputer equipped with the semiconductor memory, the load capacity of the word line and the data line increases, and the speed of reading and writing data decreases. For this reason, a method of dividing the semiconductor memory into blocks, reducing the load capacity of the word line and the data line, and measuring the high speed operation of the semiconductor memory has become general.

A first conventional example of a semiconductor memory device is shown in FIG.
As shown in FIG. 7, memory blocks 701 and 702, an address bus for supplying addresses to these memory blocks 701 and 702, and output signals S11 to S14 and S14 from sense amplifiers constituting the memory blocks 701 and 702.
Output buffer Bu driving S21 to S24 to the data bus
The inverter 1 receives f11 to Buf14, Buf21 to Buf24, and the most significant address bit ADn.

Next, the operation of the conventional semiconductor memory device shown in FIG. 7 will be described.

In FIG. 7, when the most significant bit ADn of the address is "0", the control gates of the output buffers Buf11 to Buf14 become "1", so that the output buffers Buf11 to Buf14 are activated and the output signal S11 from the sense amplifier is output. To S14 are driven to the data bus.

On the other hand, output buffers Buf21 to Buf2
4 is "0", the outputs of the output buffers Buf21 to Buf24 become high impedance, and the output signals S21 to S24 from the sense amplifier are output.
Is not output to the data bus.

On the other hand, when the address most significant bit ADn is "1", data from the memory block 702 is output to the data bus, and data in the memory block 701 is blocked by the output buffers Buf11 to Buf14.

As described above, the most significant bit of the address determines which of the memory blocks 701 and 702 outputs data to the data bus.

Next, a second conventional example of a semiconductor memory device will be described with reference to FIG.

The semiconductor memory device shown in FIG. 8 is different from the semiconductor memory device shown in FIG. 7 in that reference voltage generating circuits and sense amplifiers constituting memory blocks 701 and 702 are different from each other.
By the read signal READ and the precharge signal FC,
Activation / inactivation can be controlled.

As shown in FIG. 9, the memory blocks 801 and 802 include a memory cell array section 92 in which memory cells are arranged in an array, a word line W1 to Wn and data lines DL1 to DL4 by decoding addresses of an address bus AD. , And read data output from the memory cell array unit 92 via the data lines DL1 to DL4 to output signals S11 to S1.
4, sense amplifiers 94 to amplify as S21 to S24
97 and the sense amplifiers 94 to 97
and a reference voltage generating circuit 93 for supplying ref.

In FIG. 9, when a read signal READ becomes active, a reference voltage generating circuit 93 is activated, and a reference voltage Vref is supplied to sense amplifiers 94 to 9.
7 The sense amplifiers 94 to 97 receive the activated precharge signal FC and the activated read signal RE.
When the AD and the reference voltage Vref are applied, they are activated, amplify the signal output from the memory cell array unit 92 via the data lines DL1 to DL4, and output the signal S1.
Output to the data bus as 1 to S14 and S21 to S24.

When the read signal READ is inactive, the reference voltage generating circuit 93 and the sense amplifier 94
To 97 become inactive and current consumption is reduced.

[0014]

In the first prior art example of the semiconductor memory device described above, in order to increase the access speed, even when the divided memory blocks 701 and 702 are not accessed, the memory blocks 701 and 702 are not used.
However, there is a problem that the sense amplifier and the reference voltage generating circuit constituting the above operate and consume power that is not originally required.

In a second conventional example of a semiconductor memory device, a read signal READ and an address most significant bit ADn are used.
Is used to simply switch the memory blocks 801 and 802, and controls the activation and deactivation of the reference voltage generation circuit and the sense amplifier. It takes time until a predetermined reference voltage Vref is generated.
There is a disadvantage that the access speed is reduced when switching between memory blocks.

An object of the present invention is to provide a semiconductor memory device which reduces power consumption by inactivating a sense amplifier and a reference voltage generating circuit of a memory block which is not accessed.

Another object of the present invention is that the access speed is reduced due to the rise time required for the sense amplifier and the reference voltage generating circuit to be activated from the inactive state when the memory block is switched. And to provide a semiconductor memory device capable of high-speed access.

[0018]

Therefore, a semiconductor memory device according to the present invention comprises a memory cell array section in which memory cells are arranged in a matrix, and storage data stored in the memory cells input through a data line. A memory block group including a plurality of memory blocks provided with a general-purpose address area and a specific address area, the memory block group including a sense amplifier that amplifies Select any one memory block to configure,
Memory block selecting means for outputting a memory block selecting signal, wherein when accessing a general-purpose address area of the memory block selected by the memory block selecting signal, a memory block other than the selected memory block is accessed. The sense amplifiers and the reference voltage generating circuits are all inactive, and when accessing a specific address area of the memory block selected by the memory block selection signal, the senses configuring all the memory blocks are not accessed. The amplifier and the reference voltage generation circuit are activated, and access a specific address area of the selected memory block before an address of the selected memory block transits to an address of another memory block. .

[0019]

Next, a first embodiment of the semiconductor memory device of the present invention will be described with reference to the drawings.

FIG. 1 shows a first example of a semiconductor memory device according to the present invention.
1 is a block diagram illustrating an embodiment of the present invention, in which memory blocks 101 and 102 and these memory blocks 101 and 1 are used.
02, and an output buffer Buf11-Buf for driving output signals S11-S14, S21-S24 from the sense amplifiers constituting the memory blocks 101, 102 to a data bus.
14, Buf21 to Buf24, and the inverter 1 which receives the address most significant bit AD17 as input.

In the semiconductor memory device shown in FIGS. 7 and 8, the address most significant bit ADn controls only the activation and deactivation of the output buffers Buf11 to Buf14 and Buf21 to Buf24. In the semiconductor memory device shown in FIG.
Is connected to the memory block selection terminals CS1 and CS2, which are the terminals for selection of the memory blocks 101 and 102, by the inverter 1
Input via or without.

The memory blocks 101 and 102 are
Each of them has a storage capacity of 128 Kbits, and the memory block 101 stores addresses 000000H (00 | 0000 | 0
000 | 0000 | 0000) to 17FFFH, and an address 18000H (0
1 | 1000 | 0000 | 0000 | 0000) ~ 1F
FFFH (01 | 1111 | 1111 | 1111 | 11
11) up to 11).

Similarly, the memory block 102 has an address of 20000H (10 | 0000 | 0000 | 0000).
General address area 1 from | 0000) to 37FFFFH
02A and address 38000H (11 | 1000 | 0
000 | 0000 | 0000) to 3FFFFH (11 |
1111 | 1111 | 1111 | 1111).

As shown in FIG. 2, the memory blocks 101 and 102 include a memory cell array section 22 in which memory cells are arranged in an array and an address bus (AD17-AD).
0) to decode any word line W1 to Wn
And a decoder circuit 21 for selecting the data lines DL1 to DL4
And data lines DL1 to DL
4 is output to the output signal S11.
To S14, S21 to S24, and a reference voltage generating circuit 23 for supplying a reference voltage Vref to the sense amplifiers 31 to 34
A specific address detection circuit 24 that detects a specific address of an address bus (AD17-AD0) and outputs a specific address detection signal SAD; and an OR that receives the output of the specific address detection circuit 24 and the memory block selection signal CS1 or CS2. The gate 25, the output of the OR gate 25 and the read signal READ are input, and the reference voltage generation circuit 2
3 and the sense amplifiers 31 to 34 include a NAND gate 26 for outputting a read enable signal RD.

As in the case of the conventional semiconductor memory device shown in FIG.
34.

Next, the reference voltage generating circuit 23 will be described with reference to FIG.

The reference voltage generating circuit 23 has an inverter INV which receives a read enable signal RD for controlling activation and deactivation of the reference voltage generating circuit 23 as an input.
1 and P which also receives the read enable signal RD.
A channel transistor PT6 and an N-channel transistor NT6, a P-channel transistor PT8 for controlling on / off of P-channel transistors PT9 and PT10 forming a current mirror circuit, and an N-channel transistor NT10 for determining a reference voltage Vref together with the P-channel transistor PT10. And a P-channel transistor PT11 that pulls up the output terminal for outputting the reference voltage Vref to the power supply voltage.

Next, the operation of the reference voltage generating circuit shown in FIG. 3 will be described.

When the read enable signal RD is "1", the P-channel transistor PT6 is turned off.
No current flows through the channel transistor PT7 and the N-channel transistors NT6 and NT7. Further, the P-channel transistor PT8 is turned on, and the gate voltages of the P-channel transistors PT9 and PT10 are pulled up to the power supply voltage.
Are both turned off.

Therefore, the N-channel transistors NT8, NT8,
Since no current flows through NT9 and NT10, the reference voltage generating circuit 23 according to the present invention is characterized in that no current flows when the read enable signal RD is "1", that is, when the reference voltage generating circuit 23 is inactive. There is.

Since the gate of the P-channel transistor PT11 becomes "0", the output terminal is pulled up to the power supply voltage.

Next, the read enable signal RD becomes "0".
In this case, the P-channel transistor PT6 is turned on, a current flows from the power supply to GND via the P-channel transistors PT6, PT7, and the N-channel transistor NT7, and a gate bias voltage is generated in the N-channel transistor NT8.

Further, since the P-channel transistor PT8 is turned off and the N-channel transistor NT8 supplies a bias current, the P-channel transistor PT9 is turned on, and the P-channel transistor PT10 forming a current mirror circuit with this is turned on. Further, the N-channel transistor NT10 is turned on, and a reference voltage Vref determined at the output terminal is determined by the mutual conductance ratio of the P-channel transistor PT10 and the N-channel transistor NT10 and the threshold voltage of the N-channel transistor NT9.

Next, regarding the sense amplifiers 31 to 34,
This will be described with reference to FIG.

The sense amplifier shown in FIG. 4 receives a precharge signal FC which is a precharge period when it is "1" and a sampling period when it is "0" and a read enable signal RD which controls the activation and deactivation of the sense amplifier. A NOR gate NOR1, a P-channel transistor PT3 that inputs the output of the NOR gate NOR1 to the gate and controls on / off of P-channel transistors PT4 and PT5 forming a current mirror circuit, and a P-gate to which an enable signal is applied to the gate. The channel transistor PT1 and the N-channel transistor NT1, and the data lines DL1 to DL1
An N-channel transistor NT3 to which a read signal S from the memory cell array unit 22 is input via the DL4, an N-channel transistor NT4 having a gate to which a reference voltage Vref is applied, and an N-channel transistor NT
Inverter INV3 whose drain is connected to the input terminal
And an inverter INV2 for inverting the output of the inverter INV3 and outputting the output signal So of the sense amplifier.

Next, the operation of the sense amplifier shown in FIG. 4 will be described.

When the read enable signal RD is "1", the P-channel transistor PT1 is turned off.
No current flows through channel transistor PT2 and N-channel transistors NT1 and NT2. Further, the P-channel transistor PT3 is turned on, and the gate voltages of the P-channel transistors PT4 and PT5 are pulled up to the power supply voltage, so that both the P-channel transistors PT4 and PT5 are turned off. Therefore, the N-channel transistors NT3 and NT3
No current flows through NT4 and NT5.

When the read enable signal RD is "1"
At this time, since the reference voltage Vref is equal to the power supply voltage as described above, the N-channel transistor NT4 turns on, and the drain voltage of the N-channel transistor NT4 becomes "0". Therefore, the output signal So becomes “0”.

As described above, the sense amplifier according to the present invention is characterized in that no current flows when the read enable signal RD is "1", that is, when the sense amplifier is inactive.

Next, the read enable signal RD becomes "0".
The operation when the precharge signal FC is "1", that is, during the precharge period, will be described. At this time, P
Since the channel transistor PT3 is turned on, the P-channel transistors PT4 and PT5 and the N-channel transistor NT3 are turned off, so that the read signal is not amplified.

Next, the read enable signal RD becomes "0".
The operation when the precharge signal FC is "0", that is, during the sampling period, will be described.

At this time, the P-channel transistor PT1
Is turned on and P-channel transistors PT1, PT
2. A current flows to GND via the N-channel transistor NT2, and a gate bias voltage is generated for the N-channel transistor NT3.

The read signal applied to the source of the N-channel transistor NT3 is
The current is converted by T3 and the P-channel transistor P
After being amplified by the mirror ratio of T4 and PT5, a current is output to the node A of each drain terminal of the P-channel transistor PT5 and the N-channel transistor NT4.

On the other hand, since the N-channel transistor NT4 tries to flow a current determined by the reference voltage Vref to GND, the voltage level of the node A is finally determined by the read signal S and the reference voltage Vref, and is determined by the inverters INV3 and INV2. It is amplified and output as an output signal So.

Next, the operation of the semiconductor memory device of the present invention will be described with reference to the timing charts shown in FIGS.

It should be noted that the specific address detection circuit 24 has 2A
A case will be described in which the ND gate is used and the address to be input to the specific address detection circuit 24 is AD16 and AD15 which are one and two lower bits from the address most significant bit AD17. The read enable signal output from the NAND gate 26 forming the memory block 101 is RD1, and the read enable signal output from the NAND gate 26 forming the memory block 102 is RD2.

First, the operation when the read signal READ is "0", that is, the operation during the non-reading period will be described. At this time, as can be seen from FIG. 2, the read enable signals RD1 and RD2 are set to the memory block selection terminals CS.
1, it is always "1" regardless of the state of CS2 and the specific address detection signal SAD.

Therefore, when the read signal READ is in the non-reading period, the reference voltage generating circuit 23 and the sense amplifiers 31 to 34 are all inactive and no current flows, so that the power consumption of the semiconductor memory device according to the present invention is extremely low. It will be a low value.

Next, the operation when the read signal READ is "1", that is, the operation during the read period will be described.

In the state of FIG. 5, since the most significant bit AD17 of the address is "0", as can be seen from FIG.
They are "1" and "0". In addition, address bits AD1
6 and AD15 are both “0”, the specific address detection signal SAD is “0”, and the memory block selection terminals CS1, C
S2 is “1” and “0”, respectively, and the read signal REA
Since D is “1”, the read enable signal RD1,
RD2 is "0" and "1", respectively.

Therefore, the reference voltage generating circuit 23 and the sense amplifiers 31 to 31 constituting the memory block 101
Operation state 1 representing the operation state of 34 is an active state,
The operation state 2 representing the operation states of the reference voltage generation circuit 23 and the sense amplifiers 31 to 34 constituting the memory block 102 is in an inactive state.

In FIG. 1, the output buffers Buf11 to Buf11-B
Since the control gate of uf14 becomes "1", the output buffers Buf11 to Buf14 are activated and drive the output signals S11 to S14 from the sense amplifiers 31 to 34 to the data bus.

On the other hand, output buffers Buf21-Buf2
4 is "0", the outputs of the output buffers Buf21 to Buf24 become high impedance, and the output signals S21 to S24 from the sense amplifier are output.
Is not output to the data bus.

As can be seen from the above description, the memory block 101 to be read is activated, but the non-read memory block 102 is deactivated, so that the power consumption of the memory block 102 is extremely small. Therefore, there is an excellent effect that the power consumption of the semiconductor memory device according to the present invention is extremely small as a whole.

Next, in the state, the address bits A
Since D16 and AD15 are "0" and "1", respectively, the specific address detection signal SAD becomes "0" similarly to the state, and the memory block selection terminals CS1 and CS2 and the read enable signals RD1 and RD2 do not change from the state. Therefore, the operation state 1 keeps the active state, and the operation state 2 keeps the inactive state.

Next, in the state, the address bits A
Since D16 and AD15 are "1" and "0", respectively, the specific address detection signal SAD is "0" similarly to the state.
Since the read enable signals RD1 and RD2 do not change from the state, the operation state 1 keeps the active state and the operation state 2 keeps the inactive state.

Next, in the state, the address bits A
Since D16 and AD15 are both "1", the specific address detection signal SAD becomes "1" and the specific address detection signal SAD
AD is activated.

At this time, the memory block selection terminal CS
1, read enable signal RD regardless of the state of CS2
1 and RD2 both become "0". Therefore, both the operation states 1 and 2 are activated.

Further, similarly to the state 1 to 5, the output buffer B
uf11 to Buf14 are activated, and the sense amplifiers 31 to Buf14 are activated.
34, the output signals S11 to S14 are driven to a data bus, the outputs of the output buffers Buf21 to Buf24 become high impedance, and the output signals S11 to S14 from the sense amplifier are output.
21 to S24 are not output to the data bus.

Next, in the state, since the address most significant bit AD17 changes from "0" to "1", the memory block selection terminals CS1 and CS2 change to "0" and "1", respectively. Also, address bits AD16,
Since AD15 is both "0" as in the state, the specific address detection signal SAD is "0", the memory block selection terminals CS1 and CS2 are "0" and "1", respectively, and the read signal READ is "1". Therefore, the read enable signals RD1 and RD2 become "1" and "0", respectively.

Therefore, the reference voltage generating circuit 23 and the sense amplifiers 31 to 31 constituting the memory block 101
The operation state 1 representing the operation state of 34 is inactive, and the operation state 2 representing the operation states of the reference voltage generation circuit 23 and the sense amplifiers 31 to 34 constituting the memory block 102 is active, which is opposite to the state. State.

The output buffers Buf21-Buf2
4 becomes “1”, the output buffers Buf21 to Buf24 are activated and the sense amplifier 3
The output signals S21 to S24 from 1 to 34 are driven to the data bus.

On the other hand, output buffers Buf11-Buf1
4, the output of the output buffers Buf11 to Buf14 becomes high impedance, and the output signals S1 from the sense amplifiers 31 to 34 become high.
1 to S14 are not output to the data bus.

Next, in the state, the address bits A
Since D16 and AD15 are "0" and "1", respectively, the specific address detection signal SAD becomes "0" similarly to the state, and the memory block selection terminals CS1 and CS2 and the read enable signals RD1 and RD2 do not change from the state. Therefore, the operation state 1 keeps the inactive state, and the operation state 2 keeps the active state.

Similarly, in the state, the state and the state are continued.

Next, in the state, the address bits A
Since D16 and AD15 are both "1", the specific address detection signal SAD becomes "1" and the specific address detection signal SAD
AD is activated again.

At this time, the memory block selection terminal CS
1, regardless of the state of CS2, the read enable signal
D1 and RD2 are both "0". Therefore, both the operation states 1 and 2 are activated again.

Also, as in the case of the state (1), the output buffer B
uf21 to Buf24 are activated, and the sense amplifiers 31 to Buf24 are activated.
34, the output signals S21 to S24 are driven to the data bus, the outputs of the output buffers Buf11 to Buf14 become high impedance, and the output signal S from the sense amplifier is output.
11 to S14 are not output to the data bus.

As can be understood from the above description of the states and the states, the memory blocks 101 to 10
When reading is switched to 2, the memory block 101 is deactivated after both the memory blocks 101 and 102 are once activated.

Similarly, as can be understood from the above description of the states and the states, when reading is switched from the memory block 102 to the memory block 101, the memory blocks 101 and 102 are once activated, 102 is deactivated.

That is, when switching the reading from the memory block 101 to the memory block 102, the address transitions from the general-purpose address area 101A of the memory block 101 to the specific address area 101B, and further, the address changes to the general-purpose address area 102 of the memory block 102. It can be seen that there is a transition.

Conversely, the same operation is performed when reading is switched from the memory block 102 to the memory block 101.

As described above, when the address of the memory block 102 changes from the memory block 101, by activating both the memory blocks 101 and 102 once, the reference voltage generation circuit 23 and the sense Since the amplifiers 31 to 34 are in the active state, the addresses can be transitioned from the memory block 101 to the memory block 102 without providing a wait time, so that high-speed access is possible.

As in the present invention, when transitioning the address from the memory block 101 to the memory block 102,
When the transition from the general-purpose address area 101A of the memory block 101 directly to the general-purpose address area 102A of the memory block 102 is performed without activating the reference voltage generation circuit 23 and the sense amplifiers 31 to 34 of the memory block 102 in advance, the reference voltage generation is performed. The circuit 23 and the sense amplifiers 31 to 34 do not operate normally and malfunction, or the reference voltage generation circuit 23 and the sense amplifiers 31 to 31
Since a wait time is provided until 34 rises, high-speed access cannot be performed.

The present invention has solved such a problem.
It is characterized by low power consumption.

The specific address areas 101B, 102B
The storage capacity of B is determined by the activation time of the reference voltage generation circuit 23 and the sense amplifiers 31 to 34, the processing time executed in the specific address areas 101B and 102B, and the like.

That is, the reference voltage generating circuit 23
The processes in the specific address areas 101B and 102B are performed until the sense amplifiers 31 to 34 are activated, and after the reference voltage generation circuit 23 and the sense amplifiers 31 to 34 are activated, the address is changed to the specific address areas 101B and 102B.
The state transitions from B to the general-purpose address areas 101A and 102A.

In the above description, the specific address detection circuit 24 is constituted by an AND gate, and the address input to the specific address detection circuit 24 is AD1 which is one bit lower and two bits lower than the address most significant bit AD17.
6, the case where AD15 is used has been described, but the address signal input to the specific address detection circuit 24 is as follows.
Not limited to two bits, any address bits may be used.

The circuit configuration is not limited to the AND gate, and may be any circuit configuration as long as the circuit detects an address input to the specific address detection circuit 24.

Further, in the above description, only the case where data written in the memory cell is read has been described. However, the case where the sense amplifier is changed to the write circuit and the read signal READ is changed to the write signal WRITE or the like for writing is performed. May be applied as well.

Next, a second embodiment of the present invention will be described with reference to FIG.

The semiconductor memory device according to the second embodiment of the present invention comprises: memory blocks 601 to 604; an address bus (AD17 to AD0) having an 18-bit width for supplying addresses to these memory blocks 601 to 604;
Output signals S11 to S1m, S21 to S2m, S3 from the sense amplifiers constituting the memory blocks 601 to 604
Output buffers Buf1 to Bufm for driving data buses 1 to S3m and S41 to S4m to the data bus, and address bits AD17 and AD16 smaller by 1 bit and 2 bits than the most significant bit AD17 of the address. Select terminals CS1-C
A decoder circuit 605 for outputting a memory block selection signal to S4 is provided.

The memory blocks 601 to 604 are
Similar to the semiconductor memory device shown in FIG. 1, general-purpose address areas 601A to 604A and specific address areas 601B to
604B.

The operation of the semiconductor memory device shown in FIG. 6 is basically the same as that of the semiconductor memory device shown in FIG. 1, for example, general-purpose address area 601A of memory block 601.
Is accessed, another memory block 602 is accessed.
６０604 are all inactive, and wasteful power consumption is reduced.

When switching from the memory block 601 to the memory block 603, the memory block 601
General address area 601A to specific address area 60
Transition to 1B. At this time, the memory blocks 601 to 6
04 all transition to the active state,
The reference voltage generation circuit and the sense amplifier constituting 604 are activated.

Thereafter, the address is stored in the memory block 603.
General-purpose address area 603A or specific address area 60
Transition to 3B.

As described above, when switching the reading from a plurality of memory blocks, once the general-purpose address area 6
01A to 604A to specific address area 601B to 60
By transitioning to 4B and then to an address of another memory block, the access speed can be increased and the power consumption can be reduced.

In the above description, the case where the number of memory blocks is four has been described, but it is easy to expand the number of memory blocks.

[0089]

As described above, in the semiconductor memory device according to the present invention, when reading from a memory block is performed by switching the memory block, all the memory blocks are activated once to configure each memory block. Since the reference voltage generation circuit and the sense amplifier to be activated are activated, addresses between memory blocks can be transitioned without providing a wait time, and high-speed access is possible.

When the general-purpose address area of a memory block is being accessed, all other memory blocks are inactive, and no current flows through the reference voltage generating circuit and the sense amplifier constituting these memory blocks. Thus, power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a semiconductor memory device of the present invention.

FIG. 2 is a circuit diagram showing one embodiment of the memory blocks 101 and 102 of FIG.

FIG. 3 is a circuit diagram showing one embodiment of a reference voltage generation circuit 23 of FIG. 2;

FIG. 4 is a circuit diagram showing one embodiment of the sense amplifiers 31 to 34 of FIG. 2;

FIG. 5 is a timing chart for explaining the operation of the semiconductor memory device of the present invention shown in FIG. 1;

FIG. 6 is a block diagram showing a second embodiment of the semiconductor memory device of the present invention.

FIG. 7 is a block diagram illustrating an example of a conventional semiconductor memory device.

FIG. 8 is a block diagram showing another example of a conventional semiconductor memory device.

FIG. 9 is a circuit diagram showing memory blocks 801 and 802 of FIG.

[Explanation of symbols]

1, INV1 to INV3 Inverter 21, 91, 605 Decoder circuit 22, 92 Memory cell array unit 23, 93 Reference voltage generation circuit 24 Specific address detection circuit 25 OR gate 26 NAND gate 31 to 34, 94 to 97 Sense amplifier 101, 102, 601 to 604, 701, 702, 8
01, 802 Memory block 101A, 102A, 601A-604A General-purpose address area 101B, 102B, 601B-604B Specific address area Buf11-Buf14, Buf21-Buf24, B
uf1 to Bufm output buffer CS1, CS2 Memory block selection signal NOR1 NOR gate NT1 to NT10 N-channel transistor PT1 to PT11 P-channel transistor

Claims (7)

[Claims] 1. A memory cell array section in which memory cells are arranged in a matrix, a sense amplifier for amplifying data stored in the memory cells input via a data line, and a reference voltage applied to the sense amplifier. A memory block group including a plurality of memory blocks provided with a general-purpose address area and a specific address area, including a reference voltage generation circuit to be supplied; and an arbitrary memory block configuring the memory block group; Memory block selecting means for outputting a selection signal, wherein when a general-purpose address area of the memory block selected by the memory block selection signal is being accessed, a memory block other than the selected memory block is configured. The sense amplifier and the reference voltage generation circuit When a specific address area of the memory block selected by the memory block selection signal is being accessed, the sense amplifiers and reference voltage generation circuits configuring all the memory blocks are activated, A semiconductor memory device, wherein a specific address area of the selected memory block is accessed before an address of the selected memory block transits to an address of another memory block. 2. A memory cell array section in which memory cells are arranged in a matrix, a write circuit for writing input data to the memory cells via data lines, and a reference voltage generator for supplying a reference voltage to the write circuit. A memory block group including a plurality of memory blocks each including a general-purpose address area and a specific address area; and an arbitrary memory block included in the memory block group is selected, and a memory block selection signal is output. A memory block selecting unit, wherein when accessing a general-purpose address area of the memory block selected by the memory block selection signal, the write circuit and a write circuit configuring a memory block other than the selected memory block; The reference voltage generation circuits are all inactive, and the memory block When accessing a specific address area of the memory block selected by the block selection signal, the write circuit and the reference voltage generation circuit configuring all the memory blocks are activated, and the selected memory block is activated. A specific address area of the selected memory block is accessed before the address of the selected memory block transitions to an address of another memory block. 3. A specific address detection circuit for outputting a specific address detection signal which is activated when a predetermined address of the address is inputted, wherein all the memory blocks are activated when the specific address detection signal is activated. 3. The method according to claim 1, wherein said sense amplifier or write circuit and a reference voltage generating circuit are activated.
The semiconductor memory device according to claim 1. 4. The semiconductor memory device according to claim 1, wherein said memory block selecting means comprises a decoder circuit which receives an arbitrary bit of said address as an input. 5. The semiconductor memory device according to claim 4, wherein said decoder circuit is an AND gate. 6. An OR gate for inputting said specific address detection signal and said memory block selection signal, and said OR gate
A NAND gate to which an output of the gate and a read signal that is activated at the time of reading are input, wherein the output of the NAND gate controls activation or inactivation of the sense amplifier and the reference voltage generation circuit. The semiconductor memory device according to claim 1. 7. An OR gate for inputting the specific address detection signal and the memory block selection signal, and the OR gate
A NAND gate to which an output of the gate and a write signal to be activated at the time of writing are input, wherein the output of the NAND gate controls activation or inactivation of the writing circuit and the reference voltage generating circuit. The semiconductor memory device according to claim 2.