JP2000012844A - High breakdown voltage semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a high-breakdown voltage semiconductor device, which can avoid increase in a junction leakage, due to a damaged region generated on a semiconductor substrate at the formation of an LDD low-concentration impurity diffusion structure in the case where an offset region is provided. SOLUTION: A method of manufacturing a high-breakdown voltage semiconductor device consists of a process, wherein after gate electrodes 14A and 14B are formed on a semiconductor substrate 10, low-concentration impurity regions 15A and 15B are formed in the region of the substrate 10 by an ion implantation method, then a process for forming an insulating film 16 on the entire surface, a process for providing masks on the film 16, a process for etching the film 16 using the masks, moreover, a process for forming insulating film regions 16A and 16B from the top surfaces of the electrodes 14A and 14B for extending to the part on at least one side of the parts of each of the regions 15A and 15b: Then, a process for forming high-concentration impurity regions 19A and 19B in the region of the substrate 10 using the masks by an ion implantation method.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a high breakdown voltage semiconductor device and a method of manufacturing the same.

[0002]

2. Description of the Related Art A high breakdown voltage semiconductor device in which a voltage applied to a source / drain region is higher than a power supply voltage _Vcc (for example, 3 volts) has, for example, a floating gate electrode and a control gate electrode, and is electrically rewritten. Is used in various fields, such as a booster circuit in a memory cell capable of operating. An outline of a method for manufacturing such a conventional high breakdown voltage semiconductor device (high breakdown voltage transistor) will be described below with reference to FIGS. 10 and 11 which are schematic partial cross-sectional views of a silicon semiconductor substrate and the like. Incidentally, _the power supply voltage V _cc is applied to the source region of the high breakdown voltage transistor, a high voltage V _pp is assumed to be applied to the drain region.

[Step-10] First, after forming an element isolation region 11 having a LOCOS structure in a silicon semiconductor substrate 10, a gate insulating film 13 is formed on the surface of the silicon semiconductor substrate 10 based on a thermal oxidation method. Thereafter, an n-type well 12A is provided on the silicon semiconductor substrate 10 to form a p-channel transistor, and a p-type well 12B is further provided on the silicon semiconductor substrate 10 to form an n-channel transistor. Next, a polysilicon layer containing impurities and a tungsten silicide layer are sequentially deposited on the entire surface by a CVD method, and then, the tungsten silicide layer and the polysilicon layer are patterned to form gate electrodes 14A and 14B. be able to. The height of the gate electrodes 14A and 14B is 0.2 μm.
m. In the figure, the gate electrodes 14A, 14B
Is represented by one layer.

[Step-20] Next, in order to form an LDD structure, ions are implanted into the exposed silicon semiconductor substrate 10 to form a low-concentration impurity region (p ⁻ region) 15A for a p-channel transistor. And a low-concentration impurity region (n ⁻ region) 15B for an n-channel transistor.

[Step-30] Thereafter, an insulating film 11 is formed on the entire surface.
6 is deposited by the CVD method, and then the insulating film 11 is deposited.
By etching back 6 based on the RIE method,
Gate sidewalls 18A and 18B are formed on the side walls of the gate electrodes 14A and 14B (see FIG. 10A).

[Step-40] Next, in order to form a p-channel transistor, a resist 30A for ion implantation is provided based on a lithography technique, and boron is ion-implanted into the exposed silicon semiconductor substrate 10 to thereby increase the height. A concentration impurity region (p ⁺ region) 19A (source region 19A ₁ , drain region 19A ₂ ) is formed (see FIG. 10B). Thereafter, in order to remove the resist 30A and form an n-channel transistor, a resist 30B for ion implantation is provided based on a lithography technique, and phosphorus or arsenic is ion-implanted into the exposed silicon semiconductor substrate 10 to achieve a high concentration. Impurity region (n ⁺ region)
After forming the source region 19B (the source region 19B ₁ and the drain region 19B ₂ ) (see FIG. 11A), the resist 30B is removed (see FIG. 11B). Source area 19
A ₁ and 19B ₁ have a power supply voltage V _cc of, for example, about 3 volts.
Is applied. On the other hand, a high voltage V _pp of, for example, about 25 volts is applied to the drain regions 19A ₂ and 19B ₂ .

In the high breakdown voltage transistor, in order to suppress the occurrence of the parasitic bipolar action, and to suppress the occurrence of the pn junction breakdown when the high voltage _Vpp is applied to the drain regions 19A ₂ and 19B _2. Then, from the side walls of the gate electrodes 14A and 14B, the drain region 19A
_2, the 19B ₂ the distance to the end, about 1 [mu] m. The gate electrode 14A, the low concentration impurity region 15A located between the side walls and the drain region 19A _2, 19B ₂ ends of 14B, a part of 15B, for convenience, referred to as the offset region 20A, and 20B. The width L _s of the gate side wall is about 0.2μm.

[Step-50] Thereafter, an interlayer insulating layer is formed on the entire surface, and the source / drain regions 19A ₁ , 19A ₂ , 1
An opening is provided as necessary in the interlayer insulating layer above 9B ₁ and 19B ₂ , and a contact plug is formed by filling the opening with tungsten by, for example, a blanket tungsten CVD method. After forming a metal wiring material layer on the substrate, a wiring is formed by patterning the metal wiring material layer. Thus, a high breakdown voltage transistor can be manufactured.

[0009]

SUMMARY OF THE INVENTION [Step-30]
In forming the gate sidewalls 18A and 18B on the side walls of the gate electrodes 14A and 14B by etching back the insulating film 116 based on the RIE method,
Etching ions are reflected by the inclined portions of the insulating film 116 near the side walls of the gate electrodes 14A and 14B (see FIG. 12A), and finally, the low concentration impurity regions 15A and 15A near the side walls of the gate electrodes 14A and 14B. A portion 15B (a part of the offset regions 20A and 20B) is scooped, and a damaged region is generated (see FIG. 12B). As shown in an enlarged schematic partial cross-sectional view of FIG. 13, when such a damaged region is formed in a part of the offset regions 20A and 20B, a high voltage V _{pp is} applied to the drain regions 19A ₂ and 19B _2.
When the voltage is applied, the depletion layer expands and reaches the damaged region, resulting in a problem that junction leakage increases. On the other hand, as shown in FIG. 13, the source regions 19A ₁ and 19B ₁
Although a damaged region is also generated in the high-concentration impurity regions 19A and 19B constituting the source region 19A, only the power supply voltage _Vcc is applied to the source regions 19A ₁ and 19B ₁ at most.
Even if a high voltage V _pp is applied to A ₁ and 19B ₁ , the depletion layer does not reach the damaged regions because the damaged region is located in the high-concentration impurity regions 19A and 19B, and the junction leakage increases. There is no problem.

[0010] Therefore, an object of the present invention is to avoid the occurrence of a phenomenon that, when an offset region is provided, junction leakage increases due to a damaged region generated in a semiconductor substrate when an LDD structure is formed. An object of the present invention is to provide a high breakdown voltage semiconductor device and a method for manufacturing the same.

[0011]

According to a first aspect of the present invention, there is provided a method of manufacturing a high breakdown voltage semiconductor device, comprising the steps of: (a) forming a gate electrode on a semiconductor substrate; (B) forming low-concentration impurity regions by ion implantation in regions of the semiconductor substrate on both sides of the gate electrode;
(C) forming a mask on the insulating film, covering the entire surface of the insulating film, extending from the top surface of the gate electrode to at least one of the low-concentration impurity regions; (D) etching the insulating film using the mask as an etching mask, thereby forming a region of the insulating film extending from the top surface of the gate electrode to at least one of the low-concentration impurity regions; And (e) using the mask as an ion implantation mask to form a high-concentration impurity region in the exposed region of the semiconductor substrate by an ion implantation method.

In the method of manufacturing a high-breakdown-voltage semiconductor device according to the first aspect of the present invention, an end of the insulating film extending from the top surface of the gate electrode to a part of the low-concentration impurity region on the low-concentration impurity region. The distance L from the portion to the side wall of the gate electrode (which substantially corresponds to the width of the offset region) is 0.4 μm.
m or more, preferably 0.8 μm or more, more preferably 1 μm or more.
It is desirable that the thickness be not less than μm from the viewpoint of surely forming the offset region. Alternatively, the distance from the end of the low concentration impurity region in the region of the insulating film extending from the top surface of the gate electrode to a part of the low concentration impurity region to the side wall of the gate electrode is L, and the height of the gate electrode is H. Where L ≧ 2H, preferably L ≧ 4H, and more preferably L
≧ 5H is desirable.

The second object of the present invention for achieving the above object is as follows.
The method for manufacturing a high-breakdown-voltage semiconductor device according to the first aspect includes the steps of (a) forming a gate electrode on a semiconductor substrate, and (b) ion-implanting a low-concentration impurity region in a region of the semiconductor substrate on both sides of the gate electrode. (C) forming an insulating film over the entire surface, and then forming a mask covering the insulating film region extending from the top surface of the gate electrode to at least one of the low-concentration impurity regions. (D) etching the insulating film using the mask as an etching mask, whereby the insulating film extending from the top surface of the gate electrode to at least one of the low-concentration impurity regions; Forming a film region; and (e) removing the mask and then using the region of the insulating film as a mask for ion implantation, forming a high-concentration impurity region in the exposed region of the semiconductor substrate by ion implantation. Work to form , The distance from the end of the low concentration impurity region of the insulating film extending from the top surface of the gate electrode to a part of the low concentration impurity region to the side wall of the gate electrode is L, and the height of the gate electrode is Where H is
The distance L satisfies 0.4 μm or more, preferably 0.8 μm or more, more preferably 1 μm or more, or L ≧ 2H, preferably L ≧ 4H, more preferably L
≧ 5H is satisfied.

In the method of manufacturing a high-breakdown-voltage semiconductor device according to the first or second aspect of the present invention, a portion of the low-concentration impurity region from the top surface of the gate electrode depends on the specification of the high-breakdown-voltage semiconductor device to be manufactured. A region of the insulating film extending to both sides of the gate electrode may be formed on both sides of the gate electrode, or a region of the insulating film extending from the top surface of the gate electrode to a part of the low concentration impurity region may be formed on one side of the gate electrode. A gate sidewall may be formed on the side wall of the gate electrode where the region of the insulating film is not formed. In the latter case, the distance from the end on the low concentration impurity region to the side wall of the gate electrode in the region of the insulating film extending from the top surface of the gate electrode to a part of the low concentration impurity region is L, and the width of the gate sidewall is the when the L _s, L ≧ 2L _s, preferably L ≧ 4L _s, more preferably it is desirable that the L ≧ 5L _s.

According to the present invention, there is provided a high-breakdown-voltage semiconductor device according to the present invention, in which (A) a gate electrode formed on a semiconductor substrate, and (B) a gate electrode formed in a region of the semiconductor substrate on both sides of the gate electrode. (C) a low-concentration impurity region formed in a region of the semiconductor substrate on both sides of the gate electrode and between the gate electrode and the high-concentration impurity region;
(D) a semiconductor device having an insulating film region extending from the top surface of the gate electrode to at least one part of the low-concentration impurity region, wherein: Assuming that the distance from the end of the extended insulating film on the low-concentration impurity region to the side wall of the gate electrode is L, and the height of the gate electrode is H, the distance L is 0.1.
It is desirable to satisfy 4 μm or more, preferably 0.8 μm or more, more preferably 1 μm or more, or to satisfy L ≧ 2H, preferably L ≧ 4H, more preferably L ≧ 5H.

In the high breakdown voltage semiconductor device of the present invention, regions of the insulating film extending from the top surface of the gate electrode to a part of the low concentration impurity region are formed on both sides of the gate electrode, depending on the specifications of the high breakdown voltage semiconductor device. Alternatively, an insulating film region extending from the top surface of the gate electrode to a part of the low-concentration impurity region is formed on one side of the gate electrode, and the insulating film region is formed on a side wall of the gate electrode where the insulating film region is not formed. May have a gate sidewall. In the latter case, the distance from the end of the low concentration impurity region in the region of the insulating film extending from the top surface of the gate electrode to a part of the low concentration impurity region to the side wall of the gate electrode is L, and the gate sidewall is formed. Is the width of L _s , L ≧ 2L _s , preferably L ≧ 4
L _s , more preferably L ≧ 5L _s is desirable.
Note that the gate sidewall is etched back at the same time as forming the region of the insulating film extending from the top surface of the gate electrode to at least one of the low-concentration impurity regions by etching the insulating film. Can be formed by

As the semiconductor substrate, a silicon semiconductor substrate can be exemplified. The gate electrode is, for example,
It can be composed of a polysilicon layer containing impurities, a laminated structure (polycide structure) of a polysilicon layer containing impurities and a silicide layer such as tungsten silicide, or a high melting point metal material layer such as tungsten. A structure in which an insulating layer is formed thereon may be employed. Note that in a gate electrode having a structure in which an insulating layer is formed over these material layers, the height H of the gate electrode includes the thickness of the insulating layer. The insulating film is SiO ₂ , BP
SG, PSG, BSG, AsSG, PbSG, SbS
G, NSG, SOG, LTO (Low Temperature Oxid
e, low-temperature CVD-SiO ₂ ), SiN, SiON, and other known materials.

The high breakdown voltage semiconductor device according to the present invention means a semiconductor device in which the voltage applied to the source / drain regions is higher than the power supply voltage _Vcc .

In the present invention, a mask covering an insulating film region extending from the top surface of the gate electrode to at least one of the low-concentration impurity regions is provided on the insulating film, and the mask is used as an etching mask. Since the insulating film is etched in this manner, generation of a damaged region due to etching of the low-concentration impurity region can be avoided.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings based on embodiments of the present invention (hereinafter, abbreviated as embodiments).

Embodiment 1 Embodiment 1 relates to a method of manufacturing a high breakdown voltage semiconductor device according to the first aspect of the present invention and a high breakdown voltage semiconductor device of the present invention. In the first embodiment, a region of the insulating film extending from the top surface of the gate electrode to a part of the low-concentration impurity region is formed on one side of the gate electrode, and the side wall of the gate electrode where such a region of the insulating film is not formed is formed. A gate sidewall is formed. The insulating film is made of PSG, but is not limited to such a material. Hereinafter, Embodiment 1 will be described with reference to FIGS. 1 to 6 which are schematic partial cross-sectional views of a semiconductor substrate and the like.

[Step-100] First, a gate electrode is formed on a semiconductor substrate. Specifically, an element isolation region 11 having a LOCOS structure is formed in a p-type silicon semiconductor substrate 10.
After forming the gate insulating film 13 (thickness: about 0.5 μm), a gate insulating film 13 having a thickness of about 40 nm is formed on the surface of the silicon semiconductor substrate 10 based on a thermal oxidation method. Note that the element isolation region may have a trench structure or a combination of a LOCOS structure and a trench structure. Then, the silicon semiconductor substrate 1 is formed to form a p-channel transistor.
An n-type well 12A is provided at 0 based on the ion implantation method, and a p-type well 12B is provided at the silicon semiconductor substrate 10 based on the ion implantation method to form an n-channel transistor. Table 1 below shows examples of ion implantation conditions. Next, a polysilicon layer having a thickness of about 0.1 μm containing impurities and a tungsten silicide layer having a thickness of about 0.1 μm are sequentially deposited on the entire surface by a CVD method.
The tungsten silicide layer and the polysilicon layer are patterned. Thereby, the gate electrodes 14A, 14B
Can be formed (see FIG. 1A). The height H of the gate electrodes 14A and 14B is about 0.2 μm. In the figure, the gate electrodes 14A and 14B are represented by one layer.

[0023]

Table 1 Formation of n-type well 12A Ion species: phosphorus or arsenic Dose: 5 × 10 ¹¹ / cm ² Formation of p-type well 12B Ion species: boron Dose: 5 × 10 ¹¹ / cm ²

[Step-110] Next, the gate electrode 14
Low-concentration impurity regions 15A and 15B are formed by ion implantation in regions of the silicon semiconductor substrate 10 on both sides of A and 14B. That is, in order to form an LDD structure, impurity ions are implanted into the exposed silicon semiconductor substrate 10 and p
Low-concentration impurity region (p
⁽ Region) 15A and a low-concentration impurity region (n ^- region) 15B for an n-channel transistor are formed (see FIG. 1B). Table 2 below shows examples of ion implantation conditions.

[0025]

[Table 2] Formation of low-concentration impurity region (p ^- region) 15A Ion species: phosphorus or arsenic Dose: 5 × 10 ¹² / cm ² Formation of low-concentration impurity region (n ^- region) 15B Ion species: boron dose : 5 × 10 ¹² / cm ²

[Step-120] After that, after the insulating film 16 is formed on the entire surface, a mask 17A covering a region of the insulating film 16 extending from the top surface of the gate electrode 14A to a part of one of the low-concentration impurity regions 15A. Is provided on the insulating film 16. Specifically, an insulating film 1 made of PSG and having a thickness of about 0.2 μm
6 is formed on the entire surface (see FIG. 2A). Next, a mask 17A made of a resist material is formed over the entire surface, and a lithography technique is used to form a portion of one of the low-concentration impurity regions 15A from the top surface of the gate electrode 14A to form a p-channel transistor. Insulating film 1 extending
A mask 17A covering the region 6 is provided on the insulating film 16 (see FIG. 2B). The mask 17A has n
The region where the channel transistor is to be formed is also covered.

[Step-130] Next, the insulating film 16 is etched by RIE using the mask 17A as an etching mask. Thereby, the gate electrode 1
A region 16A of the insulating film 16 extending from the top surface of 4A to a part of one of the low-concentration impurity regions 15A can be formed (see FIG. 3A). In the first embodiment, the insulating film region 16A is formed on one side of the gate electrode 14A. On the side wall of the gate electrode where the insulating film region 16A is not formed, the gate sidewall 18A is simultaneously formed by etching back the insulating film 16.

[Step-140] Thereafter, using the mask 17A as an ion implantation mask, a high concentration impurity region is formed in the exposed region of the silicon semiconductor substrate 10 by an ion implantation method. In order to form a p-channel transistor, a dose of 5
Boron is ion-implanted under the condition of × 10 ¹⁵ / cm ² . Thus, a high-concentration impurity region (p ⁺ region) 19A (source region 19A ₁ , drain region 19A ₂ ) can be formed (see FIG. 3B).

[Step-150] Next, a mask 17B made of a resist material is formed on the entire surface, and in order to form an n-channel transistor, one of the lower surfaces of the gate electrode 14B is formed from the top surface of the gate electrode 14B by lithography. A mask 17B covering the region of the insulating film 16 extending to a part of the concentration impurity region 15B is provided on the insulating film 16 (see FIG. 4A). The mask 17B also covers a region where a p-channel transistor is to be formed. Thereafter, the insulating film 16 is etched based on the RIE method using the mask 17B as an etching mask. Thus, the region 16B of the insulating film 16 extending from the top surface of the gate electrode 14B to a part of the one low-concentration impurity region 15B
(See FIG. 4B). In the first embodiment, the insulating film region 16B is formed on one side of the gate electrode 14B. The gate sidewall 1 is formed by etching back the insulating film 16 on the side wall of the gate electrode where the insulating film region 16B is not formed.
8B are formed simultaneously.

[Step-160] Then, using the mask 17B as an ion implantation mask, a high concentration impurity region is formed in the exposed region of the silicon semiconductor substrate 10 by an ion implantation method. Specifically, in order to form an n-channel transistor, the exposed silicon semiconductor substrate 10
Then, phosphorus or arsenic is ion-implanted under the condition of a dose amount of 5 × 10 ¹⁵ / cm ² . Thereby, the high concentration impurity region (n
⁺ Region) 19B (source region 19B ₁ , drain region 19)
B ₂ ) can be formed (see FIG. 5).

Thereafter, the semiconductor device having the structure shown in FIG. 6A can be manufactured by removing the mask 17B.

[Step-170] Then, for example, a PSG layer having a thickness of 0.1 μm and a Si layer having a thickness of 0.1 μm are formed on the entire surface.
After forming an interlayer insulating layer composed of three layers of an N layer and a BPSG layer having a thickness of 0.6 μm, and performing a flattening process on the interlayer insulating layer, the source / drain regions 19A ₁ , 19A ₂ ,
An opening is provided in the interlayer insulating layer above 19B ₁ and 19B ₂ as necessary, for example, by blanket tungsten CVD.
A contact plug is formed by filling the inside of the opening with tungsten by a method, a metal wiring material layer is formed on the interlayer insulating layer, and then the metal wiring material layer is patterned to form a wiring. Finally, a PSG layer having a thickness of about 0.5 μm is deposited on the entire surface as an overcoat layer.

In the first embodiment, as shown in an enlarged schematic partial cross-sectional view of FIG. 6B, an insulating material extending from the top surface of gate electrode 14B to a part of low-concentration impurity region 15B. Low concentration impurity region 15 in film region 16B
The distance L from the end on B to the side wall of the gate electrode 14B was 1 μm. In addition, the width L _s of the gate side wall 18B is about 0.2μm. Height H of gate electrode 14B
Is about 0.2 μm. Therefore, to satisfy L ≧ 2H, moreover, it meets the L ≧ 2L _s. The gate electrode 14
The distance L from the end on the low concentration impurity region 15A to the side wall of the gate electrode 14A in the insulating film region 16A extending from the top surface of A to a part of the low concentration impurity region 15A is also 1 μm.
m. In addition, the width L _s of the gate side wall 18A
Is about 0.2 μm. The height H of the gate electrode 14A is about 0.2 μm. Therefore, to satisfy L ≧ 2H, moreover, it meets the L ≧ 2L _s.

In the first embodiment, a mask for forming an insulating film region extending from the top surface of the gate electrode to at least one of the low-concentration impurity regions, and a high-concentration region in the exposed region of the semiconductor substrate. The mask for forming the impurity region by the ion implantation method is the same mask.
Therefore, even if a damaged region in which a junction leak can occur is generated, such a damaged region is located in the high-concentration impurity region, so that the occurrence of a junction leak can be reliably suppressed. That is, the source region 19A _1, 19B ₁ in the high voltage transistor of the first embodiment, for example 3 volts of _the power supply voltage V _cc is applied. On the other hand, a high voltage V _pp of, for example, about 25 volts is applied to the drain regions 19A ₂ and 19B ₂ . In the high breakdown voltage transistor, in order to suppress the occurrence of the parasitic bipolar action, the high voltage V _{pp is} applied to the drain regions 19A ₂ and 19B _2.
In order to suppress the occurrence of pn junction breakdown when is applied, offset regions 20A and 20B are provided in low concentration impurity regions 15A and 15B. By the way, Embodiment 1
In [Step-130] or [Step-15]
0], when the insulating film 16 is etched based on the RIE method, the top surface of the insulating film 16 to be etched is flat. Therefore, as in the prior art, the gate electrode 14
Etching ions are reflected by the inclined portions of the insulating film 116 near the side walls of the gate electrodes 14A and 14B (see FIG. 12A), and finally the low concentration impurity regions 15A and 15B near the side walls of the gate electrodes 14A and 14B. Part (offset area 20)
A and a part of 20B) are dug, and the problem that a damaged area is generated (see FIG. 12B) can be reliably avoided. Therefore, the drain regions 19A ₂ and 19B ₂
When a high voltage V _pp is applied to the substrate, even if the depletion layer extends, the problem that the junction region does not increase without reaching the damage region can be reliably avoided. Moreover, even if the silicon semiconductor substrate 10 is gouged, even if the damaged area generated, such damaged regions are high-concentration impurity regions 19A, so located within 19B, the drain region 19A _2, 19B ₂ a high voltage V _pp When the voltage is applied, the problem that the depletion layer does not reach such a damaged region and the junction leak increases can be reliably avoided. still,
In the method of manufacturing a high-breakdown-voltage semiconductor device according to the first embodiment, the number of etching (etch-back) increases by one time as compared with the conventional method of manufacturing a high-breakdown-voltage semiconductor device, but the number of resist patterns does not change.

Embodiment 2 Embodiment 2 relates to a method of manufacturing a high breakdown voltage semiconductor device according to the second aspect of the present invention and a high breakdown voltage semiconductor device of the present invention. Also in the second embodiment, a region of the insulating film extending from the top surface of the gate electrode to a part of the low-concentration impurity region is formed on one side of the gate electrode, and the side wall of the gate electrode where the region of the insulating film is not formed A gate sidewall is formed. The insulating film is made of PSG, but is not limited to such a material. Embodiment 2 will be described below with reference to FIGS. 7 and 8 which are schematic partial cross-sectional views of a semiconductor substrate and the like.

[Step-200] First, as in [Step-100] of the first embodiment, a gate electrode is formed on a semiconductor substrate. Specifically, after forming the element isolation region 11 in the silicon semiconductor substrate 10, the silicon semiconductor substrate 10
The gate insulating film 13 is formed on the surface of the substrate. Thereafter, the n-type well 12A and the p-type well 1 are formed in the silicon semiconductor substrate 10.
2B is provided based on the ion implantation method. Next, a polysilicon layer having a thickness of about 0.1 μm containing impurities and a tungsten silicide layer having a thickness of about 0.1 μm are sequentially formed on the entire surface.
Then, the tungsten silicide layer and the polysilicon layer are patterned. Thus, the gate electrodes 14A and 14B can be formed. The height H of the gate electrodes 14A, 14B is about 0.2
μm. In the figure, the gate electrodes 14A and 14B are represented by one layer.

[Step-210] Next, as in [Step-110] of the first embodiment, the gate electrodes 14A, 14B
A low-concentration impurity region (p ⁻ region) 15A and a low-concentration impurity region (n ⁻ region) 15B are formed in the regions of the silicon semiconductor substrate 10 on both sides by ion implantation.

[Step-220] Then, similarly to [Step-120] of the first embodiment, after the insulating film 16 is formed on the entire surface, one of the low-concentration impurity regions 15A is formed from the top surfaces of the gate electrodes 14A and 14B. Insulating film 1 extending to a part of.
A mask 17 covering the region 6 is provided on the insulating film 16. In the first embodiment, masks 17A and 17B are used twice in [Step-120] and [Step-150].
Was formed and the insulating film 16 was etched twice. However, in the second embodiment, the mask 17 may be formed only once. Specifically, a thickness of about 0.
An insulating film 16 of 2 μm is formed on the entire surface. Next, a mask 17 made of a resist material is formed on the entire surface, and one low-concentration impurity region is formed from the top surface of the gate electrode 14A by using lithography technology to form a p-channel transistor and an n-channel transistor. A mask 17 covering a region of the insulating film 16 extending to a part of 15A,
Further, a mask 17 is provided on the insulating film 16 to cover a region of the insulating film 16 extending from the top surface of the gate electrode 14B to a part of the one low-concentration impurity region 15B (see FIG. 7A).

[Step-230] Next, the insulating film 16 is etched using the mask 17 as an etching mask. Thereby, the insulating film 16 extending from the top surface of the gate electrode 14A to a part of one of the low-concentration impurity regions 15A is formed.
16A, and at the same time, a region 16B of the insulating film 16 extending from the top surface of the gate electrode 14B to a part of one of the low-concentration impurity regions 15B can be formed (FIG. 7).
(B)). In the second embodiment, the regions 16A and 16B of the insulating film are formed on one side of the gate electrodes 14A and 14B. Further, the insulating film regions 16A, 1
Gate sidewalls 18A and 18B are simultaneously formed by etching back the insulating film 16 on the side walls of the gate electrodes 14A and 14B where 6B is not formed.

[Step-240] Thereafter, the mask 17 is removed. Then, an SiO ₂ film 40 having a thickness of about 10 nm is formed on the exposed surface of the silicon semiconductor substrate 10 by a thermal oxidation method. This SiO ₂ film 40 prevents the occurrence of channeling in ion implantation and prevents impurity ions from being deeply implanted along the silicon crystal lattice, resulting in a wide impurity distribution and the formation of a deep junction. Formed for Next, a resist 31A is formed as an ion implantation mask, and the exposed silicon semiconductor substrate 10 is formed.
A high-concentration impurity region is formed in a self-aligned manner by an ion implantation method. Specifically, in order to form a p-channel transistor, the resist 31A and the region 1 of the insulating film are formed.
Using 6A as an ion implantation mask, boron is ion-implanted into the exposed silicon semiconductor substrate 10 at a dose of 5 × 10 ¹⁵ / cm ² . Thereby, a high-concentration impurity region (p ⁺ region) 19A (source region 19A ₁ , drain region 19A ₂ ) can be formed (see FIG. 8A). Then, after removing the resist 31A and forming a resist 31B as an ion implantation mask, a high-concentration impurity region is formed in an exposed region of the silicon semiconductor substrate 10 in a self-aligned manner by an ion implantation method. Specifically, in order to form an n-channel transistor, the resist 31B and the region 16B of the insulating film are used as a mask for ion implantation, and the exposed silicon semiconductor substrate 10 is exposed to a dose of 5 × 10 ¹⁵ / cm ² . To implant phosphorus or arsenic. As a result, the high-concentration impurity region (n ⁺ region) 19B (the source region 19B ₁ , the drain region 19
B ₂ ) can be formed (see FIG. 8B).

[Step-250] Then, resist 31B
And, as in [Step-170] of the first embodiment,
An interlayer insulating layer is formed on the entire surface, and the source / drain regions 19 are formed.
A contact plug is formed on the interlayer insulating layer above A ₁ , 19A ₂ , 19B ₁ , and 19B ₂ as necessary, and a metal wiring material layer is formed on the interlayer insulating layer. Are formed by patterning the wiring.

Also in the second embodiment, as shown in the enlarged schematic partial cross-sectional view of FIG. 6B, a portion extends from the top surface of gate electrode 14B to a portion of low-concentration impurity region 15B. The distance L from the end of the insulating film region 16B on the low concentration impurity region 15B to the side wall of the gate electrode 14B was 1 μm. Width L of gate side wall 18B
_s is about 0.2 μm, and the height H of the gate electrode 14B is about 0.2 μm. Therefore, to satisfy L ≧ 2H, moreover, it meets the L ≧ 2L _s. Also, the gate electrode 14
The distance L from the end on the low concentration impurity region 15A to the side wall of the gate electrode 14A in the region 16A of the insulating film extending from the top surface of A to a part of the low concentration impurity region 15A is 1 μm.
m. Width L _s of the gate side wall 18A is about 0.2 [mu] m, the height H of the gate electrode 14A is about 0.
2 μm. Therefore, L ≧ 2H is satisfied, and L
We are satisfied ≧ 2L _s.

In the second embodiment, the region of the insulating film extending from the top surface of the gate electrode to at least one of the low-concentration impurity regions is used as a mask for ion implantation.
A high concentration impurity region is formed in a region of a semiconductor substrate by an ion implantation method. Therefore, the low concentration impurity regions 15A, 15B
In addition, the offset regions 20A and 20B can be reliably provided. In the second embodiment, [Step-2
30], when the insulating film 16 is etched, the top surface of the insulating film 16 to be etched is flat. Therefore, unlike the prior art, the low-concentration impurity regions 15A, 1A
The problem that a portion 5B (a part of the offset regions 20A and 20B) is scooped and a damaged region is generated can be reliably avoided. Therefore, the drain region 19
When a high voltage V _pp is applied to A ₂ and 19B ₂ , even if the depletion layer extends, the damage does not reach the damaged region, and the problem that the junction leakage increases can be reliably avoided.
Moreover, even if the silicon semiconductor substrate 10 is scooped and a damaged region is formed, such a damaged region is located in the high-concentration impurity regions 19A and 19B, so that a high voltage V _pp is applied to the drain regions 19A ₂ and 19B _2. When the voltage is applied, the problem that the depletion layer does not reach such a damaged region and the junction leak increases can be reliably avoided. In the method of manufacturing a high-breakdown-voltage semiconductor device according to the second embodiment, the number of resist patterns is increased by one compared with the conventional method of manufacturing a high-breakdown-voltage semiconductor device, but the number of etching (etch-back) is not changed.

The present invention has been described based on the embodiments of the present invention, but the present invention is not limited to these embodiments. The manufacturing conditions and materials used for the high-breakdown-voltage semiconductor device according to the embodiment of the invention are merely examples, and can be changed as appropriate. In the embodiment of the invention, the gate electrode 14
Low concentration impurity regions 15A, 15B from the top surfaces of A, 14B.
Are formed on one side of the gate electrodes 14A and 14B, and the gate electrode 14 where the insulating film regions 16A and 16B are not formed is formed.
Gate side walls 18A, 18 on side walls of A, 14B
B was formed. On the other hand, depending on the specifications of the high breakdown voltage semiconductor device, as shown in a schematic partial cross-sectional view of the n-channel transistor, the top surface of the gate electrode 14B extends to a part of the low-concentration impurity region 15B, as shown in FIG. Extended insulating film region 16B
May be formed on both sides of the gate electrode 14B. With such a structure, even if a high voltage is applied V _pp to the source region 19B ₁ in the high voltage transistor, there is no fear that caused problems. Note that a similar structure can be employed in a p-channel transistor.

[0045]

According to the present invention, when an offset region is provided, it is possible to reliably avoid the occurrence of a phenomenon that junction leakage increases due to a damaged region generated in a semiconductor substrate when an LDD structure is formed. it can. Therefore, a high breakdown voltage semiconductor device having high performance and high reliability can be manufactured.

[Brief description of the drawings]

FIG. 1 is a schematic partial cross-sectional view of a silicon semiconductor substrate and the like for describing a method for manufacturing a high withstand voltage semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a schematic partial cross-sectional view of a silicon semiconductor substrate and the like for explaining the method for manufacturing the high withstand voltage semiconductor device according to the first embodiment of the present invention, following FIG. 1;

FIG. 3 is a schematic partial cross-sectional view of the silicon semiconductor substrate and the like for explaining the method for manufacturing the high withstand voltage semiconductor device according to the first embodiment of the invention, following FIG. 2;

FIG. 4 is a schematic partial cross-sectional view of the silicon semiconductor substrate and the like for explaining the method for manufacturing the high withstand voltage semiconductor device according to the first embodiment of the present invention, following FIG. 3;

FIG. 5 is a schematic partial cross-sectional view of the silicon semiconductor substrate and the like for illustrating the method for manufacturing the high withstand voltage semiconductor device according to the first embodiment of the invention, following FIG. 4;

FIG. 6 is a schematic partial cross-sectional view of a silicon semiconductor substrate and the like for explaining a method of manufacturing the high withstand voltage semiconductor device according to the first embodiment of the invention, and a schematic enlarged view of an offset region and the like, following FIG. FIG.

FIG. 7 is a schematic partial cross-sectional view of a silicon semiconductor substrate and the like for describing a method for manufacturing a high withstand voltage semiconductor device according to a second embodiment of the present invention;

FIG. 8 is a schematic partial cross-sectional view of a silicon semiconductor substrate and the like for explaining the method for manufacturing the high withstand voltage semiconductor device according to the second embodiment of the present invention, following FIG. 7;

FIG. 9 is a schematic partial sectional view showing a modification of the high breakdown voltage semiconductor device of the present invention.

FIG. 10 is a schematic partial cross-sectional view of a silicon semiconductor substrate and the like for describing a conventional method for manufacturing a high breakdown voltage semiconductor device.

FIG. 11 is a schematic partial cross-sectional view of a silicon semiconductor substrate and the like for describing a conventional method for manufacturing a high breakdown voltage semiconductor device, following FIG. 11;

FIG. 12 is a schematic partial cross-sectional view of a silicon semiconductor substrate or the like for describing a problem in a conventional method of manufacturing a high breakdown voltage semiconductor device.

FIG. 13 is a schematic partial cross-sectional view of a silicon semiconductor substrate or the like for describing a problem in a conventional method of manufacturing a high breakdown voltage semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Silicon semiconductor substrate, 11 ... Element isolation area, 12A, 12B ... Well, 13 ... Gate insulating film, 14A, 14B ... Gate electrode, 15A, 15
B: low concentration impurity region, 16: insulating film, 16
A, 16B: region of insulating film, 17, 17A, 17B
... Mask, 18A, 18B ... Gate sidewall, 19A, 19B ... High concentration impurity region, 19A
₁ , 19B ₁ ... source region, 19A ₂ , 19B ₂ ...
Drain region, 20A, 20B... Offset region,
30A, 30B, 31A, 31B ... resist, 40
... SiO ₂ film

Claims (14)

[Claims] (A) a step of forming a gate electrode on a semiconductor substrate; (b) a step of forming low-concentration impurity regions by ion implantation in regions of the semiconductor substrate on both sides of the gate electrode; (D) forming an insulating film over the entire surface and then providing a mask on the insulating film to cover a region of the insulating film extending from the top surface of the gate electrode to at least one of the low-concentration impurity regions; Etching the insulating film using the mask as an etching mask, thereby forming a region of the insulating film extending from the top surface of the gate electrode to at least one of the low-concentration impurity regions; (E) using the mask as a mask for ion implantation,
Forming a high-concentration impurity region in an exposed region of the semiconductor substrate by an ion implantation method. 2. A method according to claim 1, wherein a distance from an end on the low concentration impurity region to a side wall of the gate electrode in a region of the insulating film extending from the top surface of the gate electrode to a part of the low concentration impurity region is 1 μm or more. The method for manufacturing a high withstand voltage semiconductor device according to claim 1. 3. The distance from an end on the low concentration impurity region in the region of the insulating film extending from the top surface of the gate electrode to a part of the low concentration impurity region to the side wall of the gate electrode is L, and the height of the gate electrode is 2. The method according to claim 1, wherein when L is H, L ≧ 2H is satisfied. 4. The manufacturing method of a high breakdown voltage semiconductor device according to claim 1, wherein an insulating film region extending from the top surface of the gate electrode to a part of the low concentration impurity region is formed on both sides of the gate electrode. Method. 5. An insulating film region extending from a top surface of the gate electrode to a part of the low-concentration impurity region is formed on one side of the gate electrode, and a gate is formed on a side wall of the gate electrode where the insulating film region is not formed. 2. The method according to claim 1, wherein a sidewall is formed. 6. The distance between an end of the low concentration impurity region in the region of the insulating film extending from the top surface of the gate electrode to a part of the low concentration impurity region and the side wall of the gate electrode is L, when the width is L _s, the method of producing a high voltage semiconductor device according to claim 5, characterized by satisfying the L ≧ 2L _s. 7. A step of forming a gate electrode on a semiconductor substrate, a step of forming a low-concentration impurity region in a region of the semiconductor substrate on both sides of the gate electrode by an ion implantation method, (D) forming an insulating film over the entire surface and then providing a mask on the insulating film to cover a region of the insulating film extending from the top surface of the gate electrode to at least one of the low-concentration impurity regions; Etching the insulating film using the mask as an etching mask, thereby forming a region of the insulating film extending from the top surface of the gate electrode to at least one of the low-concentration impurity regions; (E) removing the mask, forming a high-concentration impurity region in the exposed region of the semiconductor substrate by an ion implantation method using the region of the insulating film as a mask for ion implantation, Of the gate electrode When the distance from the end of the low concentration impurity region in the insulating film extending from the surface to a part of the low concentration impurity region to the side wall of the gate electrode is L, and the height of the gate electrode is H, the distance A method for manufacturing a high withstand voltage semiconductor device, wherein L satisfies 1 μm or more, or L ≧ 2H. 8. The manufacturing method of a high breakdown voltage semiconductor device according to claim 7, wherein an insulating film region extending from the top surface of the gate electrode to a part of the low concentration impurity region is formed on both sides of the gate electrode. Method. 9. An insulating film region extending from a top surface of the gate electrode to a part of the low-concentration impurity region is formed on one side of the gate electrode, and a gate is formed on a side wall of the gate electrode where the insulating film region is not formed. 8. The method according to claim 7, wherein a sidewall is formed. 10. When the width of the gate sidewall was L _s, claim 9, characterized by satisfying the L ≧ 2L _s
3. The method for manufacturing a high breakdown voltage semiconductor device according to claim 1. (A) a gate electrode formed on a semiconductor substrate; (B) a high-concentration impurity region formed in a region of the semiconductor substrate on both sides of the gate electrode; and (C) a semiconductor substrate on both sides of the gate electrode. An area,
A low-concentration impurity region formed in a region between the gate electrode and the high-concentration impurity region; and (D) a region of an insulating film extending from a top surface of the gate electrode to at least one of the low-concentration impurity regions. A semiconductor device, wherein a distance from an end of the insulating film extending from the top surface of the gate electrode to a part of the low-concentration impurity region on the low-concentration impurity region to a side wall of the gate electrode is L; Wherein the height L is H, the distance L satisfies 1 μm or more, or L ≧ 2H. 12. The high breakdown voltage semiconductor device according to claim 11, wherein an insulating film region extending from the top surface of the gate electrode to a part of the low concentration impurity region is formed on both sides of the gate electrode. . 13. An insulating film region extending from the top surface of the gate electrode to a part of the low-concentration impurity region is formed on one side of the gate electrode, and a side wall of the gate electrode where the insulating film region is not formed is formed. The high breakdown voltage semiconductor device according to claim 11, wherein a gate sidewall is formed. 14. When the width of the gate sidewall was L _s, claim 1, characterized by satisfying the L ≧ 2L _s
4. The high breakdown voltage semiconductor device according to 3.