JP2000012727A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, in which the arrangement of a board can be facilitated by enhancing the efficiency of leading out a wiring pattern formed on the board. SOLUTION: In an insertion board 10D of a semiconductor device 10 inserted between a semiconductor element 11 and a wiring board 20 and connecting the electrodes of the semiconductor element 11 with lands 21 of the wiring board 20, a plurality of insertion board lands 16 are formed in lattice at a plurality of intervals of arrangement at plural conductor parts which are jointed to the plurality of lands 21 of the wiring board 20 thus forming a plurality of wiring patterns L13, as required, between the insertion board lands 16. A plurality of wiring patterns can also be formed, as required, between the lands 21A of the wiring board 20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
For example, CSP (Chip Size Package) and MCM (Multi Chi
This is suitable for application to a semiconductor device in which chip components are mounted at a high density, such as p Module).

[0002]

2. Description of the Related Art Conventionally, in a semiconductor device called a CSP (Chip Size Package), a flip chip (IC chip) is mounted on a CSP substrate, and a CSP substrate on which the flip chip is mounted is mounted on a mother substrate. ing.

Here, in the CSP substrate, a wiring pattern for transmitting flip-chip input / output signals and a mother substrate connection land (hereinafter referred to as a CSP land) formed at an end of the wiring pattern are formed. I have.
That is, as shown in FIG. 7, the CSP substrate 1A has CSP lands 2A, 3A and 4A each having a diameter of 0.5 [mm] and a wiring pattern L1A formed with a line width of 0.1 [mm].
The distance between the CSP lands 2A, 3A and 4A is 0.8 [mm] between the centers.

In such a CSP substrate 1A, the minimum pattern interval is generally required to be 0.1 [mm] or more.

[0005]

By the way, in the CSP substrate 1A having such a configuration, the CSP lands 2A, 3A
And 4A are formed in a grid pattern at equal intervals, and in such an arrangement of the CSP lands 2A, 3A and 4A, the wiring patterns L1A from the CSP lands 2A, 3A and 4A are arranged in the same direction (for example, rightward in FIG. 7). ), Only one wiring pattern L1A can be formed between the CSP lands 2A in the outermost row (the side on which the wiring pattern is drawn).

As a result, it becomes difficult to wire the wiring pattern L1A drawn from the innermost CSP lands 4A between the outermost CSP lands 2A, and the CSP board 1A is used as a drawing pattern of the CSP lands 4A. However, there is a problem that the configuration cannot be avoided, such as using a via hole formed in the depth direction of the substrate.

As shown in FIG. 8, the mother board 1B on which the CSP is mounted also has the CS
Similarly to the case of the P board 1A, the mother board side lands 2B, 3B having a diameter of 0.5 [mm] are provided at positions corresponding to the CSP lands 2A, 3A, and 4A provided on the CSP board 1A.
And a wiring pattern L1B having a line width of 0.1 [mm] are formed, and the mother board side lands 2B, 3B and 4B are formed.
Is 0.8 [mm] between centers.

Accordingly, also in the mother board 1B having such a configuration, the mother board side lands 2B, 3B and 4B are formed in a grid pattern at equal intervals, and the arrangement of such mother board side lands 2B, 3B and 4B. In order to pull out the wiring patterns L1B from the mother board side lands 2B, 3B and 4B in the same direction (for example, to the right in FIG. 8), the mother board side lands 2B in the outermost row (the side from which the wiring pattern is drawn) Only one wiring pattern L1B can be formed between 3B and 4B.

As a result, it becomes difficult to wire the wiring pattern L1B drawn out from each mother board side land 4B in the innermost row between the mother board side lands 2B in the outermost row, and to pull out the mother board side land 4B. As a pattern, a via hole formed in the depth direction of the mother substrate 1B is used.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and by improving the efficiency of drawing out a wiring pattern formed on a substrate, an insertion substrate and a wiring substrate (mother substrate) are provided.
It is intended to propose a semiconductor device which can simplify both or any one of the substrate configurations.

[0011]

According to the present invention, there is provided a semiconductor device which is interposed between a semiconductor element and a wiring board and electrically connects an electrode of the semiconductor element and a land of the wiring board by a conductor. In the insertion board of the device,
Wiring formed between the interposer board lands by forming a plurality of interposer board lands formed at the joints of the plurality of conductor portions with the plurality of lands of the wiring board in a grid pattern at a plurality of arrangement intervals. A plurality of patterns can be formed as needed. Therefore, the efficiency of drawing out the wiring pattern on the interposer can be improved.

Also, in a wiring board on which a semiconductor device including a semiconductor element and an insertion board is mounted, a land formed at a position corresponding to the insertion board land formed on the insertion board is formed of the insertion board land. By arranging at a plurality of arrangement intervals corresponding to the formation positions, a plurality of wiring patterns formed between the lands of the wiring board can be formed as necessary. Accordingly, it is possible to improve the drawing efficiency of the wiring pattern on the wiring board on which the semiconductor device is mounted.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

In FIG. 1, reference numeral 10 denotes a semiconductor device (CSP) mounted on a mother board 20 as a whole, including a flip chip 11, a first-layer CSP board section 10A as an interposer board, and a second-layer CSP. It comprises a substrate unit 10B, a third-layer CSP substrate unit 10C, and a fourth-layer CSP substrate unit 10D.

A flip chip (IC chip) 11 is mounted on the first layer CSP board portion 10A. The flip chip 11 is configured such that the electrodes 12 arranged at the ends thereof are connected to the first layer CSP substrate 10 via bonding wires 13.
A is connected to the flip-chip land 14 of FIG.
Is formed.

A first layer C is provided at the end of the wiring pattern L10.
Via holes (Via Hol) in the direction penetrating the SP substrate 10A
e) V10 is formed, and the wiring pattern L11 of the second-layer CSP substrate unit 10B is connected to the wiring pattern L10 of the first-layer CSP substrate unit 10A via the via hole V10.

A via hole V11 is formed at the end of the wiring pattern L11 of the second-layer CSP substrate portion 10B in a direction penetrating through the second-layer CSP substrate portion 10B. CSP board part 10C
Is connected to the wiring pattern L11 of the second-layer CSP substrate unit 10B.

A via hole V12 is formed at the end of the wiring pattern L12 of the third-layer CSP substrate portion 10C in a direction penetrating the third-layer CSP substrate portion 10C. CSP board part 10D
Is connected to the wiring pattern L12 of the third-layer CSP substrate unit 10C.

At the end of the wiring pattern L13 of the fourth-layer CSP board portion 10D, a CSP land (interposed board land) 16 for connecting a mother board is formed. 20 lands 21
, The semiconductor device (CSP) 10 can be mounted on the motherboard 20.

Here, in the fourth-layer CSP substrate portion 10D on which the CSP lands 16 for connecting the motherboard 20 to connect the semiconductor device (CSP) 10 to the motherboard 20, as shown in FIG. The CSP lands 16 are arranged substantially in a lattice pattern. Incidentally, FIG. 2 shows the fourth layer CSP.
This shows only the CSP lands 16 formed on the substrate section 10D. Among the plurality of CSP lands 16, the plurality of CSP lands 16A arranged at the outermost periphery (row) are:
Each of them is formed at equal intervals with a mutual interval (center interval) PA of 1.0 [mm].

The plurality of CSP lands 16B in the second row formed inside the outermost circumference (row) are formed at regular intervals with a mutual interval (center interval) PB of 0.8 [mm]. Further, the plurality of CSP lands 16C arranged at the innermost circumference (row) have a distance PC (center distance) between each other.
It is formed at equal intervals as 0.8 [mm].

As described above, the CSP lands 16A, 16B and 16C constituting the three rows as the CSP lands 16 are described.
Is the distance PA between the outermost (row) CSP lands 16A,
It is formed wider than the intervals PB and PC between the second row and the innermost CSP lands 16B and 16C. By the way,
Each of the CSP lands 16A, 16B and 16C is formed with a diameter of 0.5 [mm].

FIG. 3 shows the CSP lands 16 (16A, 16B, 16C) and the wiring pattern L13 formed on the fourth-layer CSP substrate portion 10D described above with reference to FIGS.
And the layout of the via holes V12, showing the wiring patterns L
Each of the patterns 13 has a line width WL of 0.1 [mm] and an interval PL of each pattern of 0.1 [mm]. This fourth
Second row and innermost circumference (row) in the layer CSP substrate section 10D
The wiring pattern L13 drawn out from the CSP lands 16B and 16C has the space PA between the outermost CSP lands 16A of 1.0 [mm], so that two wiring patterns L13 can be wired therebetween. .

That is, since the CSP lands 16A, 16B and 16C of three rows arranged in a rectangular shape as a whole are formed in the fourth-layer CSP substrate part 10D, the distance between the CSP lands 16B of the second row is formed. It is sufficient that PB is an interval through which only one wiring pattern L13 drawn from the innermost (row) CSP land 16C passes. As a result, the interval PB of the CSP land 16B is formed at 0.8 [mm].

On the other hand, the space PA between the outermost (row) CSP lands 16A is the second row and innermost (row) CSP land 16A.
Since the wiring patterns L13 are formed at intervals (1.0 [mm]) that can pass through the wiring patterns L13 one by one (a total of two wirings) respectively drawn from the lands 16B and 16C, the second and innermost circumferences (rows) are formed through these spaces. A total of two wiring patterns L13 from the CSP lands 16B and 16C can be drawn out of the outermost (row) CSP lands 16A.

As described above, a plurality of CSPs on the outermost periphery (row)
The lands 16A are formed at arrangement intervals that are widened according to the number of wiring patterns L13 passed between the adjacent CSP lands 16A.

The mother board 2 on which the CSP 10 is mounted
0, the fourth layer CS on the CSP 10 side as shown in FIG.
Each CSP land 16A, 16B and 1 of the P board part 10D
6C (FIG. 2), lands 21A, 21B
And 21C are arrayed. FIG. 4 shows only the lands 21 (21A, 21B and 21C) formed on the mother substrate 20. This multiple lands 2
1, a plurality of lands 21 arranged on the outermost periphery (row)
A is 1.0 [mm] between each other (center interval) PA
Are formed at equal intervals.

The plurality of lands 21B in the second row formed inside the outermost circumference (row) are formed at regular intervals with a mutual interval (center interval) PB of 0.8 [mm].
Further, a plurality of lands 21C arranged on the innermost circumference (row)
Are formed at regular intervals, with the mutual distance (center distance) PC being 0.8 [mm].

As described above, the land 2 on the mother substrate 20 side
The lands 21A, 21B, and 21C that constitute three rows as 1 have an interval PA between the outermost (row) lands 21A.
The distance PB between the second row and the innermost land 21B and 21C
And is wider than PCs. By the way, each land 21A, 21B and 21C is the C of CSP10 respectively.
Each of the SP lands 16 (16A, 16B and 16C) is formed with a diameter of 0.5 [mm].

Accordingly, the fourth layer CS described above with reference to FIG.
In the same manner as in the case of the P board portion 10D, in the mother board 20, as shown in FIG. 5, between the lands 21A of the outermost circumference (row), the lands 21C of the innermost circumference (row) and the lands 21C of the second row are arranged. Two wiring patterns L drawn from the land 21B
23 (the line width WL of each wiring pattern L23 is 0.1 [mm]).

In the above configuration, the semiconductor device (CS
P) 10 is a fourth member forming a joint with the mother substrate 20.
Each of the square-shaped 3 formed on the layer CSP substrate portion 10D
CSP land 16 in the row (CSP land 1 in the outermost circumference (row)
6A, the CSP lands 16B in the second row and the CSP lands 16C in the innermost circumference (row) connect the wiring patterns L13 wired in the direction of the end of the fourth-layer CSP substrate unit 10D. In this case, since only one row of CSP lands 16C is formed inside the array of CSP lands 16B of the second row, the CSP lands 16 of the second row are formed.
One wiring pattern L13 is wired in each of the intervals PB of B.

On the other hand, since two rows of CSP lands 16B and 16C are arranged inside the arrangement of the outermost (row) CSP lands 16A, the outermost (row) CSP lands 16A are formed. Is 2 for each
One wiring pattern L13 is wired.

Therefore, the CSP land 16 on the innermost circumference (row)
The wiring pattern L13 drawn from C is the second row of CS
The fourth layer CSP substrate unit 1 passes through the space PB between the P lands 16B and the space PA between the outermost (row) CSP lands 16A.
It is pulled out to the end side of 0D.

The wiring pattern L13 drawn from the CSP land 16B in the second row is the outermost (column) CSP.
The fourth layer CSP substrate 1 through the space PA of the land 16A
It is pulled out to the end side of 0D.

As described above, the distance PA between the outermost (row) CSP lands 16A is set to the wiring pattern L passing through the distance PA.
13, the wiring patterns L
13 withdrawal efficiency can be improved.

The mother board 2 on which the CSP 10 is mounted
Reference numeral 0 denotes three rows of lands 21 each formed in a rectangular shape corresponding to the CSP lands 16A, 16B, and 16C at the joint with the fourth layer CSP substrate 10D on the CSP 10 side.
(Land 21A on the outermost circumference (row), land 21B on the second row)
And the innermost land (row) land 21C) is a wiring pattern L23 drawn out toward the end of the mother substrate 20.
Are connected. In this case, since only one row of lands 21C is arranged inside the arrangement of the lands 21B of the second row, one wiring pattern L23 is wired in each of the intervals PB of the lands 21B of the second row. You.

On the other hand, the outermost (row) Halland 2
Since two rows of lands 21B and 21C are arranged inside the 1A array, two wiring patterns L23 are respectively wired in the space PA between the outermost (row) lands 21A.

Accordingly, the wiring pattern L23 drawn from the innermost land (column) land 21C is the land 21C of the second row.
B and the distance P between the outermost (row) land 21A.
A is drawn out to the end side of the mother substrate 20 through A.

The wiring pattern L23 led out from the land 21B in the second row is the land 21A on the outermost circumference (row).
Is drawn out to the end side of the mother substrate 20 through the space PA.

As described above, in the mother board 20, the CSP
In accordance with the arrangement of the CSP lands 16 in FIG. 10, the spacing PA between the outermost (row) lands 21A is formed in accordance with the number of wiring patterns L23 passing through the spacing PA, thereby improving the extraction efficiency of the wiring pattern L23. can do.

According to the above configuration, the CSP land 16A
And the intervals PA and PB of 16B are set to the intervals PA and PB.
Are formed in accordance with the number of wiring patterns L13 passing through the wiring pattern L13, the efficiency of drawing out the wiring patterns L13 can be improved,
As a result, all CSP lands 16A, 16B and 16
With respect to C, the signal can be led out to the end side of the fourth-layer CSP substrate portion 10D by the wiring pattern L13.

As described above, when a via hole is used for a part of the CSP land (for example, the innermost circumference (row) of the CSP substrate) as in the related art, it is possible to avoid a complicated configuration due to the conventional technique.

Similarly, in the mother board 20, the spaces PA and PB between the lands 21A and 21B are made to correspond to the number of the wiring patterns L23 passing through the spaces PA and PB, corresponding to the arrangement of the CSP lands 16 of the CSP 10. By forming the wiring pattern L23, the extraction efficiency of the wiring pattern L23 can be improved. As a result, all the lands 21A, 21
The signals of B and 21C can be drawn out to the end of the mother board 20 by the wiring pattern L23.

In this case, when a via hole is used for a part of the land (for example, the innermost circumference (row) of the mother substrate) as in the conventional case, the structure can be prevented from being complicated by any method.

In the above embodiment, three rows of CSP lands 16A, 16B and 1
Although the case where the present invention is applied to the semiconductor device (CSP) having the 6C and the motherboard 20 corresponding thereto has been described, the number of columns of the CSP land portion and the land portion on the motherboard side is not limited to this. As shown in FIG. 6 in which parts corresponding to those in FIG. 3 are assigned the same reference numerals, four rows of CSP lands 16X, 16A, 16B and 1 from the outermost (row) side.
The present invention can be applied to the semiconductor device 40 having 6C. In this case, the land arrangement on the mother board side is the same as that shown in FIG. 6, and the wiring pattern extraction efficiency can be improved also on the mother board.

In this case, each CSP land 16X on the outermost periphery (row) is set to a distance PX between the CSP lands 16X.
As the three wiring patterns L13 from the lands 16A, 16B and 16C pass, they are formed at an arrangement interval of 1.2 [mm]. In addition, the arrangement intervals PA and PB of the CSP lands 16A in the second row and the CSP lands 16B in the third row
Is similar to the case described above for FIGS. 2 and 3,
Wiring pattern L13 passing through respective intervals PA and PB
1.0 [mm] and 0.8 [mm] according to the number of

In this case, the land structure is the same on the mother board 20 side as well, and the drawing efficiency of the wiring pattern can be improved on both the CSP side and the mother board side.

In the above-described embodiment, the case where the present invention is applied to a semiconductor device having a CSP configuration has been described. However, the present invention is not limited to this, and for example, an MCM (Multi Chi
p Module), BGA (Ball Grid Array) or PGA (Pin
The present invention can also be applied to a semiconductor device such as a Grid Array.

In the above embodiment, each CS
P lands 16A, 16B and 16C and mother substrate 2
The diameter of the lands 21A, 21B and 21C on the 0 side is 0.5 [m
m], and the line width WL of the wiring patterns L13 and L23 is 0.1 [m
m], and the interval PL between the wiring patterns L13 and L23 is 0.1 [m
m], the distance PA between the CSP lands 16A (the lands 21A on the motherboard) and the distance PB between the CSP lands 16B (the lands 21B on the motherboard) are set to 1.0 [mm].
Although the case of 0.8 [mm] has been described, the present invention is not limited to this, and various sizes can be applied.

In the above-described embodiment, the semiconductor device having the configuration in which the wiring pattern L13 is pulled out toward the end of the fourth-layer CSP substrate portion 10D has been described. The present invention can be applied to an apparatus. In this case, each CSP land 16
A, 16B and 16C and land 2 of mother substrate 20
Sequence spacing PA, PB and PC of 1A, 21B and 21C
Should be set.

[0051]

As described above, according to the present invention, an interposer substrate for a semiconductor device which is interposed between a semiconductor element and a wiring board and electrically connects the electrodes of the semiconductor element and the lands of the wiring board by conductors. Forming a plurality of interposer board lands formed at joints of the plurality of conductor parts with the plurality of lands of the wiring board in a lattice pattern at a plurality of arrangement intervals, thereby forming the plurality of interposer board lands. A plurality of wiring patterns can be formed as needed.

In this way, it is possible to improve the efficiency of forming the wiring pattern formed on the interposer board.
The configuration of the semiconductor device having the interposed substrate can be simplified.

Also, on the wiring board side on which the semiconductor device is mounted, the lands arranged corresponding to the arrangement of the interposer board lands are formed at a plurality of arrangement intervals, so that the wiring formed between the lands is formed. A plurality of patterns can be formed as needed.

Thus, the efficiency of forming a wiring pattern formed on the wiring board on which the semiconductor device is mounted can be improved, and the configuration of the wiring board on which the semiconductor device is mounted can be simplified accordingly.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a configuration of a semiconductor device according to the present invention.

FIG. 2 is a schematic plan view showing an arrangement state of CSP lands.

FIG. 3 is a partial plan view showing a configuration of a CSP substrate.

FIG. 4 is a schematic plan view showing an arrangement state of lands on a mother board.

FIG. 5 is a partial plan view showing a configuration of a mother substrate.

FIG. 6 is a partial plan view showing a configuration of a CSP substrate and a configuration of a mother substrate according to another embodiment.

FIG. 7 is a partial plan view showing a configuration of a conventional CSP substrate.

FIG. 8 is a partial plan view showing a configuration of a conventional mother board.

[Explanation of symbols]

1. CSP board, 2, 3, 4, 16A, 16B, 16
C: CSP land, 10: semiconductor device, 10A ...
1st layer CSP substrate section, 10B ... second layer CSP substrate section,
10C... Third-layer CSP substrate portion, 10D... Fourth-layer CS
P board part, 11 Flip chip (IC chip), 1
7 ... solder, 20 ... mother board, 21, 21A, 21
B, 21C ... land, L1, L13, L23 ... wiring pattern, V1, V10, V11, V12 ... via hole.

Claims (2)

[Claims] A semiconductor device mounted on a wiring board, wherein a semiconductor element is interposed between the semiconductor element and the wiring board, and an electrode of the semiconductor element and a land of the wiring board are electrically connected by a conductor. A plurality of interposer boards to be connected, and a plurality of interposer boards formed at joints between the plurality of conductor portions of the interposer board and the plurality of lands of the wiring board, respectively, and arranged in a grid at a plurality of arrangement intervals. A semiconductor device comprising a land. 2. The interposer board lands may be the number of wiring patterns formed between adjacent interposer board lands of the plurality of interposer board lands, or electrically connected to the plurality of interposer board lands, respectively. 2. The semiconductor device according to claim 1, wherein the semiconductor device is formed at an arrangement interval corresponding to the number of wiring patterns formed between adjacent lands among the lands of the wiring substrate.