JP2000002866A - Method for controlling liquid crystal display device, drive assembly for liquid crystal display device, liquid crystal display device and electronic appliance - Google Patents

Abstract

PROBLEM TO BE SOLVED: To rapidly clear the charges accumulated in a liquid crystal layer and to prevent the deterioration of liquid crystals without depending on an individual device by electrically connecting the liquid crystal layer to a fixed potential when a power supply off is detected. SOLUTION: An off-sequence circuit 140 is a circuit for detecting the voltage drop of a power-supply voltage Vcc when the power source to be supplied to a liquid crystal display device turns off. The circuit causes the transition of the signal level of a signal PWR- and a signal PWR+ when the power-supply voltage Vcc falls to the threshold voltage Vth or below. A constant current circuit 150a connects supply lines of voltages V1, V6 among the plural voltage supply lines to which voltages of V0 to V7 are supplied from a DC-DC converter 130a to a grounding line according to the level transition of the signal PWR- or the signal PWR+. The grounding line exists at the grounding potential of the stable potential regardless of the on/off of the power source and is optimum as the fixed potential of the destination where the charges are removed from the liquid crystal layer. The constant current circuit 150a which supplies the grounding potential supplies the constant current.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for controlling a liquid crystal display device in which, for example, after power is turned off, electric charges accumulated in each liquid crystal layer are quickly cleared to prevent deterioration of the liquid crystal, and a driving method of the liquid crystal display device. The present invention relates to a device, a liquid crystal display device, and electronic equipment using the liquid crystal display device.

[0002]

2. Description of the Related Art In general, an active matrix type liquid crystal display device mainly comprises an element array substrate in which switching elements are provided in each of pixel electrodes arranged in a matrix, and an opposing array in which color filters and the like are formed. Board and
And a liquid crystal filled between the two substrates. Then, a liquid crystal layer is constituted by the pixel electrode, the opposing substrate, and the liquid crystal filled therebetween.

In such a configuration, when an ON (selected) signal is applied to the switching element, the switching element is turned on. For this reason, predetermined charges are accumulated in the liquid crystal layer connected to the switching element. Then, even if the switching element is turned off by applying an off (non-selection state) signal after the charge accumulation, if the resistance of the liquid crystal layer is sufficiently high, the accumulation of the charge in the liquid crystal layer is maintained. As described above, when each switching element is driven to control the amount of charge to be stored, the alignment state of the liquid crystal changes for each pixel, and it is possible to display predetermined information. At this time, since it is sufficient to accumulate charges in each liquid crystal layer during a part of the period, by selecting each scanning line in a time-division manner, the multiplexing in which the scanning line and the data line are shared by a plurality of pixels is performed. Driving is possible.

[0004] As the switching element, mainly
Three-terminal switching elements, such as thin film transistors (TFTs) and MOS transistors, and two-terminal switching elements, such as thin-film diodes (TFDs) that have non-linear current-voltage characteristics. Is done. These three-terminal or two-terminal switching elements are also called non-linear elements because their current-voltage characteristics are non-linear.

By the way, when the power of the liquid crystal display device is turned off, the supply of the drive signal is stopped at the same time as the power is turned off, the electric field applied to the liquid crystal layer when the drive signal is stopped remains as it is, and the direct current is applied to the liquid crystal layer. The voltage is applied. Here, if a DC voltage is continuously applied to the liquid crystal layer, a deterioration phenomenon such as a change in physical properties of the liquid crystal and a decrease in resistivity appears, and the life of the liquid crystal display device is shortened.
Therefore, when the power of the liquid crystal display device is turned off, it is desirable that the supply of the drive signal be continued until the electric charge accumulated in the liquid crystal layer becomes zero.

[0006]

However, the discharge time constant of the stored charge depends on the resistance and size of the pixel electrode,
Since it is determined by various factors such as the material of the liquid crystal and the distance between the substrates, the time required for the electric charge accumulated in the liquid crystal layer to become zero differs for each pixel and for each liquid crystal display device. there were. This problem means that the time during which the drive signal must be supplied after the power is turned off is not determined, and also has a secondary problem that it becomes difficult to design a circuit for supplying the drive signal.

[0007] The present invention has been made in view of such circumstances, and an object of the present invention is to quickly clear electric charges accumulated in a liquid crystal layer without depending on individual devices. Another object of the present invention is to provide a liquid crystal display device control method capable of preventing liquid crystal deterioration, a liquid crystal display device driving device, a liquid crystal display device, and an electronic device using the liquid crystal display device.

[0008]

In order to achieve the above object, a method of controlling a liquid crystal display device according to the present invention is directed to a liquid crystal display for performing a desired display by controlling the amount of charge stored in a liquid crystal layer. A method of controlling an apparatus, comprising: a step of detecting power-off; and a step of electrically connecting the liquid crystal layer to a fixed potential when the power-off is detected.

According to this control method, when power off is detected, the liquid crystal layer is connected to a fixed potential such as a ground potential. The power supply for supplying the fixed potential also serves as a constant current source. For this reason, the charges accumulated in the liquid crystal layer are cleared quickly and at a constant speed, so that a DC voltage is not applied to the liquid crystal for a long period of time, and deterioration of the liquid crystal can be prevented.
In addition, it is possible to set the time until the electric charge accumulated in the liquid crystal layer becomes zero without depending on factors such as the resistance and size of the electrodes of the liquid crystal display panel, the material of the liquid crystal, and the distance between the substrates. Become.

Further, in the above control method for a liquid crystal display device, when the power-off is detected, it is preferable that a signal line for applying a voltage to the liquid crystal layer is electrically connected to the fixed potential. By a simple control such as connecting the signal line to a fixed potential, it is possible to indirectly remove charges from the liquid crystal layer.

Further, in the above control method for a liquid crystal display device, when the power-off is supplied, a signal line electrically connected to the liquid crystal layer is electrically connected to a specific voltage supply line. Preferably, the specific voltage supply line is connected to the fixed potential. After connecting a signal line for supplying voltage to the liquid crystal layer to a specific voltage supply line, a switch for connecting the specific voltage supply line to a fixed potential may be provided, and with a simple configuration and control, Electric charges can be indirectly removed from the liquid crystal layer.

Further, in the above control method for a liquid crystal display device, the specific voltage supply line supplies a first voltage supply line for supplying a positive voltage to the fixed potential and a negative voltage for the first voltage supply line. Preferably, when the power-off is detected, the signal line is alternately connected to the first voltage supply line and the second voltage supply line. A supply line for positive and negative voltages with respect to the fixed potential is provided. Since the two supply lines are alternately connected to the signal line and the two supply lines are connected to the fixed potential, the supply line is switched from the positive potential to the negative potential to the fixed potential. Since the charges can be extracted from the liquid crystal layer as the potential converges, the charges can be easily extracted regardless of whether the liquid crystal layer is in a positive or negative charge storage state.

Further, in the above control method for a liquid crystal display device, the signal line is connected to the first voltage supply line and the second voltage supply line in response to a clock signal having a cycle shorter than a half horizontal scanning period. It is desirable to be connected alternately to the voltage supply line. Since the connection between the supply line and the signal line is switched according to the high frequency clock, the charge can be rapidly discharged regardless of the level of the accumulated charge in the liquid crystal layer.

Further, in the driving apparatus for a liquid crystal display device according to the present invention, a liquid crystal display device for performing a desired display by controlling the amount of electric charge accumulated in the liquid crystal layer, wherein the detection for detecting power-off is performed. And a connection means for connecting the liquid crystal layer to a fixed potential when the detection means detects that the power is off.

According to this driving device, similarly to the above-described invention, when the power-off is detected, the liquid crystal layer is connected to the fixed potential, and the electric charge accumulated in the liquid crystal layer is rapidly and at a constant speed. Is cleared by Therefore, the time until the electric charge accumulated in the liquid crystal layer becomes zero can be set without depending on factors such as the resistance and size of the electrodes of the liquid crystal display panel, the material of the liquid crystal, and the distance between the substrates. Becomes

In this driving device, the connection means further comprises: first connection means for connecting the liquid crystal layer to a specific line when power-off is detected by the detection means; It is desirable to have a second connection means for connecting to a fixed potential. This is because fewer elements need to be added to the conventional configuration in which a predetermined scanning signal is supplied by switching a plurality of lines.

In the driving device, it is preferable that the detecting means detects that the power supply is turned off when the power supply voltage becomes equal to or lower than a threshold value. This is because the configuration for monitoring the power supply voltage is the most reliable for detecting the power-off.

Further, in the above-mentioned driving device for a liquid crystal display device, it is preferable that the connection means is a switching means for connecting the liquid crystal layer and a ground line when a power-off is detected by the detection means. . This is because this configuration is the simplest.

Further, in the above-described driving device for a liquid crystal display device, it is preferable that the connection means electrically connects a signal line for applying a voltage to the liquid crystal layer to the fixed potential. By a simple control such as connecting the signal line to a fixed potential, it is possible to indirectly remove charges from the liquid crystal layer.

Further, in the above-described driving device for a liquid crystal display device, the connection means electrically connects a signal line electrically connected to the liquid crystal layer to a specific line, and connects the specific line to the specific line. It is desirable to connect to the fixed potential. After connecting a signal line for supplying voltage to the liquid crystal layer to a specific voltage supply line, a switch for connecting the specific voltage supply line to a fixed potential may be provided, and with a simple configuration and control, Electric charges can be indirectly removed from the liquid crystal layer.

Further, in the driving device for a liquid crystal display device described above, the specific line has a first supply line for supplying a positive voltage with respect to the fixed potential and a second supply line for supplying a negative voltage with respect to the fixed potential. It is preferable that the connection unit alternately connects the signal line to the first supply line and the second supply line when the power-off is detected. A supply line for positive and negative voltages with respect to the fixed potential is provided. Since the two supply lines are alternately connected to the signal line and the two supply lines are connected to the fixed potential, the supply line is changed from the positive potential to the negative potential to the fixed potential. Since the charges can be extracted from the liquid crystal layer as the convergence, the charges can be easily extracted regardless of whether the liquid crystal layer is in the positive or negative charge storage state.

Further, in the above-described driving device for a liquid crystal display device, the signal line is connected to the first supply line and the second supply line in response to a clock signal having a cycle shorter than a half horizontal scanning period. It is desirable to be connected alternately to the line. Since the connection between the supply line and the signal line is switched according to the high frequency clock, the charge can be rapidly discharged regardless of the level of the accumulated charge in the liquid crystal layer.

Next, in the liquid crystal display device of the present invention,
A liquid crystal display device for performing a desired display by controlling the amount of charge stored in a liquid crystal layer by a scanning signal and a data signal, wherein a detecting unit for detecting power-off and a power-off detected by the detecting unit And control means for instructing connection to a specific line, and, according to the instruction, either the scan line to which the scan signal is supplied or the data line to which the data signal is supplied, or both of them, It is characterized by comprising a first connecting means for connecting to a line, and a second connecting means for connecting the specific line to a fixed potential when the detection means detects that the power is off.

According to this liquid crystal display device, when power off is detected, the liquid crystal layer is connected to a fixed potential and the electric charge accumulated in the liquid crystal layer is rapidly and constant as in the above-described invention. Cleared by speed. Therefore, the time until the electric charge accumulated in the liquid crystal layer becomes zero can be set without depending on factors such as the resistance and size of the electrodes of the liquid crystal display panel, the material of the liquid crystal, and the distance between the substrates. Becomes

Further, in the liquid crystal display device of the present invention,
A liquid crystal display comprising a pixel provided with one substrate provided with a data line and another substrate provided with a scanning line, and having a pixel in which a non-linear element and a liquid crystal layer are connected in series between the data line and the scanning line. A panel, a detection circuit for detecting power-off, and a switch circuit for connecting a supply line for a selection voltage applied to the scanning line to a ground line when power-off is detected by the detection circuit. And

According to this liquid crystal display device, when power-off is detected, the supply line for the selection voltage applied to the scanning line when writing the data signal to the pixel is connected to the ground line. The stored charge is cleared quickly and at a constant rate. In particular, since the selection voltage is a voltage for turning on the two-terminal nonlinear element, electric charges can be extracted from the liquid crystal layer by turning on the nonlinear element without dropping the selection voltage immediately after the detection of power-off. For this reason, it is possible to set the time until the electric charge accumulated in the liquid crystal layer becomes zero without depending on factors such as the resistance and size of the pixel electrode, the material of the liquid crystal, and the distance between the substrates.

Further, in the above liquid crystal display device,
It is preferable that the switch circuit connects the scan line to a supply line that supplies a voltage for turning on the nonlinear element when the power-off is detected, and connects the supply line to a ground line. A scan line for supplying a selection voltage to the liquid crystal layer may be connected to only the selection voltage supply line, and a switch for connecting the supply line to the ground potential may be provided. With a simple configuration and control, Electric charges can be indirectly removed from the liquid crystal layer.

Further, in the above liquid crystal display device,
The supply line includes a first supply line for supplying a selection voltage having a positive polarity with respect to a ground potential, and a second supply line for supplying a selection voltage having a negative polarity with respect to a ground potential. It is desirable to alternately connect to the line and the second supply line. A supply line for positive and negative voltages with respect to the ground potential is provided. Since the two supply lines are alternately connected to the signal line and the two supply lines are connected to the ground potential, the supply line is changed from the positive potential to the negative potential to the ground potential. Since the charges can be extracted from the liquid crystal layer as the convergence, the charges can be easily extracted regardless of whether the liquid crystal layer is in the positive or negative charge storage state.

Further, in the above liquid crystal display device,
It is desirable that the nonlinear element be a two-terminal nonlinear element. Further, the two-terminal type nonlinear element is a thin-film diode (TFD: Thin) composed of a first metal-insulator-second metal.
Film Diode) elements are desirable.

This is because a two-terminal non-linear element such as a TFD element has no intersection between wirings, so that short-circuit failure between wirings does not occur in principle, and furthermore, a film forming process and a photolithography process are shortened. This is because it is advantageous in that it can be performed.

Also, in the liquid crystal display device of the present invention,
A liquid crystal display panel in which a liquid crystal layer is sandwiched between one substrate provided with data lines and the other substrate provided with scanning lines; a detection circuit for detecting power-off; And a switch circuit for connecting a supply line of a voltage to be applied to the scanning line or the data line to a predetermined constant potential.

Without having a non-linear element in such a pixel,
In a simple liquid crystal display device in which an electric field to the liquid crystal layer is controlled only by a pair of electrodes opposed to each other with the liquid crystal layer interposed therebetween, when power-off is detected, a supply line that supplies a voltage to a scanning line or a data line is turned off. By being connected to a predetermined constant potential, the charge stored in the liquid crystal layer is cleared quickly and at a constant speed directly via a scanning line or a data line. Therefore, it is possible to set the time until the electric charge accumulated in the liquid crystal layer becomes zero, without depending on factors such as the resistance and size of the electrode, the material of the liquid crystal, and the distance between the substrates.

Further, in the above liquid crystal display device,
When the power-off is detected, the scanning line or the data line is connected to a first supply line for supplying a positive voltage to the predetermined constant potential and a second supply line for supplying a negative voltage. It is preferable that the switch circuit is connected alternately, and the switch circuit connects the first supply line and the second supply line to the predetermined constant potential. Supply lines of positive and negative voltages with respect to a predetermined constant potential are connected. The two supply lines are alternately connected to signal lines, and the two supply lines are connected to a constant potential. Since the charge can be extracted from the liquid crystal layer as the potential converges, the charge can be easily extracted regardless of whether the liquid crystal layer is in the positive or negative charge storage state.

It is to be noted that examples of electronic devices to which such a liquid crystal display device is applied include a car navigation system, a portable information terminal device, and various other electronic devices.

[0035]

Embodiments of the present invention will be described below with reference to the drawings.

[Liquid Crystal Display Device of First Embodiment] <Embodiment of TFD Element> First, in the liquid crystal display device according to the present embodiment, a nonlinear element (switching element) for driving each liquid crystal pixel is replaced with a TFD element or the like. This will be briefly described based on the example of the two-terminal type nonlinear element. Note that the nonlinear element of the present invention is not limited to a TFD element,
Of course, it may be a three-terminal switching element such as an element or a MOS transistor.

FIG. 1A is a plan view showing a layout for one pixel in a liquid crystal panel substrate to which a TFD element is applied, and FIG. 1B is a plan view showing the structure of the TFD element.
It is sectional drawing shown along the AA in (a).

As shown in these figures, the TFD element 20
Is based on the insulating film 31 formed on the substrate 30
The first metal film 22, the oxide film 24 serving as an insulator, and the second metal film 26 are formed in this order from the side of the insulating film 31, and the metal-insulator-metal Adopt a sandwich structure. With this structure, the TFD element 20 has diode switching characteristics in both positive and negative directions.

The first metal film 22 constituting the TFD element 20 becomes the scanning line 12 as one terminal as it is, while the second metal film 26 becomes the pixel electrode 3 as the other terminal.
4 is connected. Note that the wiring 12 may be used as a data line instead of a scanning line, and may be configured to apply a data signal to the pixel electrode 34 via the data line 12 and the TFD element 20.

The substrate 30 has insulating properties and transparency, and is made of, for example, glass, plastic, or the like. Here, the reason why the insulating film 31 is provided is to prevent the first metal film 22 from peeling off from the base by heat treatment after the deposition of the second metal film 26, and
This is for preventing impurities from diffusing into the first metal film 22. Therefore, if this is not a problem, the insulating film 31 can be omitted.

The first metal film 22 is a conductive metal thin film and is made of, for example, tantalum alone or a tantalum alloy.

The oxide film 24 is, for example, an insulating film formed by anodizing the surface of the first metal film 22 in a chemical conversion solution.

The second metal film 26 is a conductive metal thin film and is made of, for example, chromium alone or a chromium alloy.

The pixel electrode 34 is made of ITO (Indium Tin Oxide) when used for a transmissive liquid crystal display panel.
When applied to a reflective liquid crystal display panel, it is made of a metal film having a large light reflectance such as aluminum or silver.

<Another Example of TFD Element>
Another example of the D element will be described.

(Common use of second metal film and pixel electrode) FIG. 1
In the TFD element 20 shown in (a) and (b), the second metal film 26 and the pixel electrode 34 are formed of different metal films, but as shown in the cross-sectional view of FIG. Alternatively, the pixel electrodes may be formed of a transparent conductive film 36 made of the same ITO film or the like. The TFD element 20 having such a configuration includes the second metal film 26 and the pixel electrode 3
4 has the advantage that it can be formed by the same process. In FIG. 2, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

(Back-to-back structure)
As another example of the D element, a back-to-back (back-t
o-back) A TFD element having a structured structure will be described. FIG.
FIG. 3A is a plan view showing a layout of one pixel on a liquid crystal panel substrate to which the TFD element is applied, and FIG.
(B) is a sectional view showing the structure of the TFD element along the line BB. In FIG. 3, the same components as those in FIG. 1 are denoted by the same reference numerals, and the description thereof will be omitted.

The back-to-back structure refers to a structure in which two diodes are connected in series in opposite directions in order to make the nonlinear characteristics symmetrical in both the positive and negative directions. For this reason,
As shown in the drawing, the TFD element 40 has a structure in which a first TFD element 40a and a second TFD 40b are connected in series with opposite polarities. Specifically, the substrate 30, the insulating film 31 formed on the surface thereof, the first metal film 42, the oxide film 44 formed on the surface by anodic oxidation, and the oxide film 44 formed on the surface and separated from each other And the second metal films 46a and 46b.

The second metal film 46a in the first TFD element 40a becomes the scanning line 48 as it is, while the second metal film 46b in the second TFD element 40b is connected to the pixel electrode 45. The oxide film 44 is formed as shown in FIG.
The film thickness is set smaller than that of the oxide film 24 in the TFD element 20 shown in FIG. The specific configuration of each component such as the first metal film 42, the oxide film 44, and the second metal films 46a and 46b is the same as that of the TFD element 20 described above, and thus the description thereof is omitted. And

In addition, it is also possible to secure the symmetry of the non-linear characteristic by using a ring-shaped element in which two diodes are connected in parallel in opposite directions.

<Embodiment of Liquid Crystal Display> Next, a liquid crystal display according to an embodiment in which the above-mentioned TFD element 20 is applied as a two-terminal nonlinear element will be described. FIG.
FIG. 1 is a block diagram illustrating a schematic configuration of a main part of a liquid crystal display device according to a first embodiment.

As shown in the figure, in the liquid crystal display panel 10, a pixel 16 is formed corresponding to each intersection of i data lines X1 to Xi and j scanning lines Y1 to Yj. Pixel 16
Has a configuration in which a liquid crystal display element (liquid crystal layer) 18 and a two-terminal nonlinear element 20 are connected in series. here,
One of the scanning lines Y1 to Yj in the figure is the same as the scanning line 12 in FIG.

Each of the scanning lines Y1 to Yj is driven by a scanning signal driving circuit 100, and each of the data lines X1 to Xi is driven by a data signal driving circuit 110. Further, the scanning signal drive circuit 100 and the data signal drive circuit 110 are controlled by the drive control circuit 120.

In the figure, the TFD element 20 is connected to the scanning line side and the liquid crystal layer 18 is connected to the data line side. Conversely, as described above, the TFD element 20 may be arranged on the data line side to connect the TFD element to the data line, and a scanning line may be provided on the side facing the TFD element 20 with the liquid crystal layer 18 interposed therebetween.

Now, the DC-DC converter 130a is
The power supply voltage Vcc is converted to generate and output voltages V0 to V7 used in the liquid crystal display device. In the present embodiment, the power supply voltage Vcc is, for example, a voltage of 12V. The off-sequence circuit 140a is a circuit for detecting a voltage drop of the power supply voltage Vcc when the power supply to the liquid crystal display device is turned off. When the power supply voltage Vcc becomes lower than the threshold voltage Vth, the signal PWR- And the level of the signal PWR + is changed. On the other hand, the constant current circuit 150a
Among the plurality of voltage supply lines to which the voltages V0 to V7 are supplied from the DC converter 130a, the supply lines of the voltages V1 and V6 are changed according to the level transition of the signal PWR- or the signal PWR +.
It connects to the ground line. The ground wire is
It is at a stable ground potential irrespective of the OFF state, and is optimal as a fixed potential at which charges are removed from the liquid crystal layer. The constant current circuit 150a that supplies the ground potential becomes a constant current source that supplies a constant current.

The details of the liquid crystal display panel 10, the scanning signal drive circuit 100, the data signal drive circuit 110, the drive control circuit 120, the off-sequence circuit 140a, and the constant current circuit 150a among the components shown in FIG. .

<Liquid Crystal Display Panel> First, details of the liquid crystal display panel 10 will be described. FIG. 5 is a partially broken perspective view schematically showing one example.

As shown in this figure, the liquid crystal display panel 10
Includes an element array substrate 30 and an opposing substrate 32 disposed opposite to the element array substrate 30. The counter substrate 32 is made of, for example, a glass substrate.

In the element array substrate 30, the pixel electrodes 3
4 are arranged in a matrix. here,
The pixel electrodes 34 arranged in the same row are connected to one of the scanning lines Y1 to Yj extending in a strip shape in the row direction via the TFD element 20 having the structure shown in FIGS. I have. Note that the structure of the TFD element 20 in FIG. 5 is similar to that of FIG. 1 except that the second metal film overlaps the pixel electrode 34.

On the other hand, in the counter substrate 32, the i data lines X1 to Xi extend in a strip shape in the column direction orthogonal to the extending direction of the scanning lines Y1 to Yj, respectively. Are formed so as to intersect the pixel electrode 34 with the liquid crystal layer interposed therebetween.

Now, the element array substrate 30 and the opposing substrate 32 configured as described above are separated by a sealant applied along the periphery of the substrate and appropriately dispersed spacers.
A certain gap is maintained, and for example, TN (Twisted Nematic) type liquid crystal is sealed in this closed space, thereby forming the liquid crystal layer 18 in FIG.

In addition, the opposing substrate 32 is provided with color filters arranged in, for example, a striped mosaic shape or a triangle shape depending on the use of the liquid crystal display panel 10. And a black matrix such as resin black in which carbon or titanium is dispersed in a photoresist. In addition, an alignment film or the like that has been rubbed in a predetermined direction is provided on the opposing surfaces of the element array substrate 30 and the opposing substrate 32 on the liquid crystal layer side, while the rear surface (outside) of each substrate has an alignment direction. A corresponding polarizing plate is provided (all are not shown).

However, in the liquid crystal display panel 10,
The use of polymer-dispersed liquid crystal in which liquid crystals are dispersed as fine particles in a polymer eliminates the need for the above-mentioned alignment film, polarizing plate, etc., thereby increasing the light use efficiency and thus increasing the brightness of the liquid crystal display panel. And low power consumption.
Further, when the liquid crystal display panel 10 is of a reflective type, the pixel electrodes 34 are formed of a metal film having a high reflectivity such as aluminum, and the liquid crystal molecules are substantially vertically aligned in the absence of a voltage instead of the TN type liquid crystal. An SH (super homeotropic) type liquid crystal or the like may be used. The pixel electrode 34
In the case where is a reflection type, the polarizing plate may be disposed only outside the counter substrate 32.

As described above, the scanning lines on the element array substrate 30 and the data lines on the counter substrate 32 shown in FIG. 5 may be interchanged.

<Scanning Signal Driving Circuit> Next, details of the scanning signal driving circuit 100 for supplying a scanning signal to the liquid crystal display panel 10 will be described.

As shown in FIG. 6, the scanning signal driving circuit 10
0 mainly includes a clock control circuit 101, a shift register 103, a latch 104, a decoder 105, a level shifter 106, and an LCD driver 107.

The clock control circuit 1
01 generates a shift clock YSCL for data shift as shown in FIG. 7 based on the scan-side clock signal YCLK output from the drive control circuit 120 and supplies it to the shift register 103. The shift clock YSCL is
This is a signal having the same cycle as the scanning side clock signal YCLK and having an even phase.

The shift register 103 is provided with shift registers having j-bit parallel outputs corresponding to the number of the scanning lines Y1 to Yj in three columns independently for each of the input data D0, D1, and D2. Configuration. Therefore, the shift register 103 outputs three bits for each of the scanning lines Y1 to Yj. Here, the input data D0, D1, and D2 are data for selecting the voltages of the respective scanning lines Y1 to Yj, and are output from the drive control circuit 120 as serial data. The shift clock YSCL is supplied to each shift register constituting the shift register 103, and each of these shift registers transfers data at the rising timing and the falling timing of the shift clock YSCL, as shown in FIG. While taking in, the taken-in data is sequentially shifted.

Next, the latch 104 is provided with a latch for taking in data of j bits in three columns in parallel. The latch 104 outputs the parallel output data of three columns × j bits by the shift register 103 at the rising edge of the latch strobe signal LS. At the timing, it is configured to take in the latches of 3 columns × j bits as they are. Here, the latch strobe signal LS is a signal supplied from the drive control circuit 120, and is a signal that rises at a predetermined timing after each shift register included in the shift register 103 captures j-bit data. .

Therefore, the latch 104 outputs the serial data D0, D0 output from the drive control circuit 120 at the rising timing of the latch strobe signal LS.
1 and D2 are converted into 3-bit parallel data for each of the scanning lines Y1 to Yj and output.

Next, the decoder 105 controls the drive control circuit 1
When the signal XSET supplied from 20 is at a normal H level, 3-bit parallel data is decoded and converted into a signal for selecting one of V0 to V7 as the voltage of the selection signal. However, when the signal XSET transitions to the L level in response to the power-off of the liquid crystal display device, the decoder 105 determines that the signal M supplied from the drive control circuit 120 is at the H level regardless of the parallel data from the latch 104. A signal for compulsorily selecting the voltage V1 and the voltage V6 when the signal M is at the L level is output. Here, the signal M is a signal that defines the liquid crystal driving polarity in the charging mode or the discharging mode.

The level shifter 106 shifts the signal decoded by the decoder 105 sequentially.

The LCD driver 107 corresponds to D in FIG.
One of the eight types of voltages V0 to V7 supplied from the C-DC converter 130a is selected and output for each of the scanning signals Y1 to Yj according to the signal shifted by the level shifter 107. Thereby, each scanning line Y1
To Yj, eight types of voltages V0 to Vj selected according to the data D0 to D2 every 1/2 period (1 / 2H) of one horizontal scanning period.
One of V7 is supplied as a scanning signal.

Here, if the correspondence between the combination of the values of the 3-bit parallel data D0, D1, and D2 output from the latch 104 and the voltages V0 to V7 of the selection signal is as shown in FIG. First, the decoder 105 decodes the 3-bit parallel data into a signal for selecting any one of the voltages V0 to V7 by the decoder 105, and secondly, shifts the signal via the level shifter 106, so that the scanning signal is output from the LCD driver 107. It is possible to select and output a voltage having a magnitude relationship as shown in FIG. 9 for each of the scanning lines Y1 to Yj.

For example, the latch 104 corresponding to the scanning line Y1
Output corresponding to data D0, D1, D2, DL10, DL11,
Similarly, the latch 104 corresponding to the scanning line Y2 is denoted by DL12.
Output corresponding to data D0, D1, D2, DL20, DL21,
DL22, as shown in FIG. 10, (DL1
0, DL11, DL12) and (DL20, DL21, DL22)
Assuming that (0, 0, 0) and (0, 0, 1) are at the rising timing t1 of the latch strobe signal LS, the voltage of the scanning line Y1 becomes V4 and the voltage of the scanning line Y2 becomes V4 in the period T1. V3.

Similarly, the values of (DL10, DL11, DL12) and (DL20, DL21, DL22) are
At LS rising timing t2, (1,
1, 1) and (0, 0, 1), during the period T2, the voltage of the scanning line Y1 becomes V2, and the voltage of the scanning line Y2 becomes
It remains at V3. FIG. 10 shows only one polarity of the scanning signal in the charging mode and the scanning signal in the discharging mode for the sake of explanation.

With such a scanning signal driving circuit 100, it becomes possible to drive the scanning signal separately in two modes of a charging mode and a discharging mode, and to drive both modes with both positive and negative polarities. Is possible.

<Data Signal Driving Circuit> Next, a data signal driving circuit 1 for supplying a data signal to the liquid crystal display panel 10
10 will be described in detail.

As shown in FIG. 11, the data signal driving circuit 110 mainly includes a shift register 111, a latch 11
2. It is composed of a DA converter 113 and an output circuit 114.

The shift register 111 sequentially shifts and outputs latch signals that are synchronous with the clock signal XCLK and that correspond to the data signal output terminals X1 to Xi.

The latch 112 is connected to each data signal output terminal X1
.. Xi. Each latch area latches n-bit serial gradation data GD0 to GDn supplied every n bits in the order of the data line with a latch signal from the shift register 111, and latches a latch pulse signal synchronized with the horizontal synchronization signal. Output at the rising edge of LP.

Here, since the gradation data GD0 to GDn, the clock signal XCLK and the latch pulse signal LP are supplied in association with each other by the drive control circuit 120, each latch area of the latch 112 is supplied in serial. Of the corresponding grayscale data, the grayscale data GD0 to GDn to the corresponding data lines are taken in, and the latch pulse signal LP
At the rising timing of the data line.

The DA converter 113 converts each gradation data corresponding to each data line into an analog signal and supplies the analog signal to the output circuit 114.

The output circuit 114 includes a DA converter 113
Is a buffer for current-amplifying the analog signal converted by the above, and performs voltage modulation output of gradation data.

Therefore, each of the data signal output terminals X1 to Xi
After that, data signals that are voltage-modulated according to the respective gradations are output.

Here, since the gradation data from the latch 112 is performed at the rising timing of the latch pulse signal LP synchronized with the horizontal synchronization signal, the output circuit 114 applies the data signal to the data line every one horizontal scanning period. Will be output. However, as described above, in each of the charging mode and the discharging mode, the selection voltage (the voltage V1 or V2 in FIG. 10) that determines the display state of the liquid crystal is:
Since the data signal is output during one half of one horizontal scanning period, the data signal is correspondingly output at 1 / half of one horizontal scanning period.
2 is set to be output.

<Driving Control Circuit> Next, the driving control circuit 12
0 will be described in detail.

As shown in FIG. 12, the drive control circuit 120
Is mainly composed of a basic timing creation unit 121, a driver control unit 122, a data output unit 123, and an A / D conversion unit 124.

The basic timing generator 121
Generates a clock signal and a timing signal to be supplied to each circuit based on synchronization signals such as a vertical synchronization signal and a horizontal synchronization signal separated from a composite signal and the like, and generates a driver control unit 122, a data output unit 123, and an A / It is supplied to the D conversion unit 124.

The A / D converter 124 converts a video signal, which is an analog signal separated from a composite signal or the like, into digital data and supplies the digital data to the data output unit 123.

The data output section 123 converts the digital data into n + 1-bit gradation data GD0 to GDn and serially converts the n + 1-bit gradation data at a predetermined timing based on a clock signal from the basic timing generation section 121. Then, the data signal is supplied to the data signal drive circuit 110.

The driver control section 122
From the basic timing generation unit 121, the above-described clock signal YCLK, latch strobe signal LS, and data D0 to D2
Alternatively, the liquid crystal driving polarity signal M is supplied to the scanning signal driving circuit 100, while the clock signal XCLK and the latch pulse signal LP are supplied to the data signal driving circuit 110.

Further, the driver control unit 122
When a signal PWR + output from an off-sequence circuit 140 to be described later becomes H level, the scanning signal drive circuit 100
Signal XSET to be supplied to
A signal M that defines the liquid crystal drive polarity in the charge mode or the discharge mode is a signal synchronized with the scanning clock signal YCLK.

The signal from the driver control unit 122 is generated based on the clock signal and the timing signal of the basic timing generation unit 121, and the basic timing generation unit 121 converts the signal into a synchronization signal such as a vertical synchronization signal or a horizontal synchronization signal. Since the clock signal and the timing signal are generated based on the scanning signal, the scanning signal output from the scanning signal driving circuit 100 and the data signal output from the data signal driving circuit 110 are also synchronized with the horizontal synchronizing signal and the vertical synchronizing signal. Becomes

<Driving Operation> FIGS. 13 (a) to 13 (a) show the operation of the scanning signal driving circuit 100, the data signal driving circuit 110, and the drive control circuit 120 when a normal display is performed on the liquid crystal display device. This will be described with reference to d).

FIG. 13A shows a data line Xn (X1 ≦ Xn
6 is a timing chart showing an example of a data signal via ≦ Xi). As shown in the figure, the data signal is supplied in the latter half of one horizontal scanning period H.

FIG. 13B shows a certain scanning line Ym (Y1 ≦ Ym <Y
FIG. 4C is a timing chart showing a scanning signal via j), and FIG. 4C is a timing chart showing a scanning signal via the next scanning line Ym + 1. As shown in these figures, the scanning signal output from the scanning line driving circuit 100 is:
The charge mode waveform and the discharge mode waveform are set so as to be alternately output every one horizontal scanning period H, and the charge mode waveform and the discharge mode waveform are also output every one vertical scanning period TV for one scanning line. It is set to output alternately.

FIG. 14D shows the voltage applied to the pixel 16 at the position corresponding to the intersection of the data line Xn and the scanning line Ym + 1, that is, the voltage applied to both ends of the TFD element 20 and the liquid crystal layer 18. 5 is a timing chart showing applied voltages. Here, the voltage VLC applied to the liquid crystal layer 18 is indicated by oblique lines.

In this example, the overcharge period Tp in the discharge mode
In re, the voltage (V7−V3) is applied, so that the TFD element 20 is turned on, and the liquid crystal layer 18 is turned on.
Is overcharged.

Next, when a voltage of (V2-V3) is applied in the discharge period Tdc, the amount of discharge is suppressed by the data signal, so that the charged state of the liquid crystal layer 18 is maintained. Therefore, when the setting of the liquid crystal display device is the normally white mode, black is displayed, and when the setting is the normally black mode, white is displayed.

Further, after one vertical scanning period TV, when a voltage of (V1-V4) is applied in the charging period Tc in the charging mode, the TFD element 20 is turned on, and the liquid crystal layer 18 is used for the data signal. Charged accordingly. Therefore, in the normally white mode, black is continuously displayed, and in the normally black mode, white is continuously displayed.

Conversely, although not shown, when the voltage (V2-V4) is applied in the discharge period Tdc in the discharge mode, a large number of charges are charged in the liquid crystal layer 18 during the overcharge period Tpre. I do. Therefore, white is displayed in the normally white mode, and black is displayed in the normally black mode.

Further, although not shown, in the charging period Tc in the charging mode after one vertical scanning period TV, (V1
When the voltage of -V3) is applied, the amount of charge to the liquid crystal layer 18 remains small, so that white is continuously displayed in the normally white mode, and continuously displayed in the normally black mode. Black will be displayed.

As described above, in the charging mode, the liquid crystal layer 18 is charged in accordance with the data signal by supplying the selection voltage V1, while in the discharging mode, the precharge voltage V7 having the opposite polarity to the selection voltage V1 is supplied. The liquid crystal layer 18
Is overcharged irrespective of the data signal, and thereafter, the selection voltage V2 having a polarity opposite to the precharge voltage V7 is supplied, and the discharge amount of the liquid crystal layer 18 is controlled by the data signal, thereby displaying the display state of the liquid crystal pixel. Can be controlled. And such a charge mode and a discharge mode are:
The same applies to the reverse polarity. For this reason, the selection voltage that determines the display state is V1 and V6 in the discharge mode.
And V2 and V5 in the charging mode.

In the driving in the charge mode and the discharge mode, even when the polarity of the voltage applied to the liquid crystal layer is inverted when the voltage is applied to the liquid crystal layer via the TFD element 20 based on the data signal, the driving of the TFD element is performed. 20 controls the charge by using the one-way state, the TFD
It is possible to eliminate the influence of the polarity variation of the element (the asymmetry of the current characteristic due to the polarity of the applied voltage).

Then, the charge mode and the discharge mode are alternately driven, and both modes are alternately driven with both positive and negative polarities, so that when the charge to the liquid crystal layer is almost stopped, the TFD element 20 is driven. Even if the voltage applied to the liquid crystal fluctuates due to variations in the characteristics of the TFD element, the error voltage generated in the liquid crystal applied voltage in the charge mode and the error voltage generated in the liquid crystal applied voltage in the discharge mode become the effective voltage. Since they mutually cancel each other, it is possible to effectively prevent the occurrence of display unevenness and the like.

<Off-Sequence Circuit> Next, an example of a specific configuration of the off-sequence circuit 140 will be described with reference to FIG.

As shown, the power supply voltage Vcc is equal to the resistance R
1, Schmitt-type comparator 1 divided by R2
41, while the positive input is
A reference voltage Vref is supplied. The power supply voltage Vcc is connected to the resistor R1,
Since the voltage divided by R2 is higher than the reference voltage Vref when the power is turned on, the output of the comparator 141 is at L level. The output of the comparator 141 is supplied to the base (gate) of the transistor 142 via the resistor R3, and is also supplied to the base (gate) of the transistor 144 via the inverter 143.

Here, the emitter (source) of the transistor 142 is grounded, while the collector (drain) is pulled up to +5 V via the resistor R4.
Since the transistor 142 is normally off, the pull-up potential (H level) is extracted as the signal PWR-. The emitter (drain) of the transistor 144 has a potential of +5 V, while its collector (source) is pulled down to the ground level via the resistor R5. Since the transistor 144 is normally on, the pull-down potential (L level) is extracted as the signal PWR +.

Therefore, when the power supply to the liquid crystal display device is turned off, the power supply voltage Vcc gradually decreases, and when the voltage obtained by dividing the power supply voltage Vcc by the resistors R1 and R2 becomes Vref or less, the output of the comparator 141 becomes , L level to H
As a result of the transition to the level, the transistor 142 changes from the off state to the on state, while the transistor 144 changes from the off state to the on state. For this reason, when the power supply voltage Vcc gradually decreases due to the power-off, the off-sequence circuit 1
The signal PWR- output from 40 changes from H level to L level, and the signal PWR + changes from L level to H level.

Here, the value of the power supply voltage Vcc at which the output of the comparator 142 transitions from the L level to the H level is the threshold voltage Vth (Vth = Vref if the comparator 141 has no offset voltage, and Vth = Vref if the comparator 141 has the offset voltage Voff). Is V
(th = Vref + Voff), and the off-sequence circuit 140 detects that the power supply is off when the power supply voltage falls below the threshold, and changes and outputs the levels of the signal PWR + and the signal PWR-. In the present embodiment, the threshold voltage Vth is set to, for example, about 10V.

<Constant Current Circuit> Next, the constant current circuit 150a
Will be described. The constant current circuit 150a switches from power-on to power-off, and when the signal PWR + and the signal PWR- undergo level transition, the supply lines of the selection voltages V1 and V6 that determine the display state of the pixel in the scanning signal are substantially connected to the ground line. This is the switch circuit to be connected. An example of the specific configuration will be described with reference to FIG.

As shown in the figure, the DC-DC converter 1
The supply line of the voltage V1 among the liquid crystal driving voltages V0 to V7 output by 30a is connected to the drain of the transistor 151. Here, the signal PWR + from the off-sequence circuit 140 is supplied to the gate of the transistor 151, while the source is grounded. That is, normally, since the signal PWR + is at the L level, the transistor 1
Although 51 is off, the transistor 151 is turned on when the power is turned off and the signal PWR + goes high.

The supply line of the voltage V6 among the voltages V0 to V7 output from the DC-DC converter 130a is connected to the source of the transistor 152. Here, the signal PWR- from the off-sequence circuit 140 is supplied to the gate of the transistor 152, and the drain is connected to the power supply voltage Vcc. That is, since the signal PWR- is normally at the H level, the transistor 1
52 is off, but when the power is turned off and the signal PWR- goes low, the transistor 152 is also turned on.

<Power-Off Operation> The power-off operation of the configuration of the off-sequence circuit 140 and the constant current circuit 150a will be described with reference to FIG.

First, as shown in FIG. 16A, when the power is turned off at timing T10, the power supply voltage Vcc gradually drops to the ground level. Here, at the timing T11, when the power supply voltage Vcc becomes equal to or lower than the threshold voltage Vth, the signal PWR + transitions to the signal H level by the above-described off-sequence circuit 140 (see FIG. 13B).
PWR- transits to the L level (see FIG. 3C).

When signal PWR + transitions to H level, driver control unit 122 in drive control circuit 120
(See FIG. 12), the signal XSET transitions to the L level (see FIG. 12 (d)), while the signal M which previously defines the liquid crystal drive polarity in the charge mode or the discharge mode.
Are synchronized with the scanning-side clock signal YCLK (see FIG. 3E). The scanning side clock signal YCLK is a high frequency clock signal for transferring the voltage selection data D0 to D2 for the scanning lines to the scanning line driving circuit 100 within a 1/2 H period. Also switches to the high frequency clock signal. Instead of the signal M, a scanning clock signal YCLK may be used.

Further, when the signal XSET transitions to the L level and the signal M synchronizes with the scanning clock signal YCLK, the decoder 105 in the scanning signal driving circuit 100
Irrespective of the parallel data from the latch 104, a signal for alternately forcibly selecting the voltage V1 and the voltage V6 is output.

For this reason, all the scanning lines Y1 to Yj are
The supply line of the voltage V1 and the voltage
The V6 supply line is alternately selectively connected in synchronization with the scanning clock signal YCLK or the signal M.

On the other hand, when the signal PWR- transits to L level,
By the above-described constant current circuit 150a, the supply line for the voltage V1 is connected to the ground line via the transistor 151, while the supply line for the voltage V6 is connected to the supply line for the power supply voltage Vcc via the transistor 152. Note that the voltage V6
Is connected to the supply line of the power supply voltage Vcc.
As shown in FIG. 7, since the level eventually reaches the ground level, such a configuration is substantially equivalent to the configuration in which the supply line of the voltage V6 is connected to the ground line. Therefore, the transistors 151 and 152 in the constant current circuit serve as constant current sources for flowing a current for setting the supply line to the ground potential.

Therefore, the charges accumulated in all the liquid crystal layers 18 are supplied to the constant current circuit 150 via the supply line of the voltage V1.
a after being forcibly discharged by the transistor 151 in FIG.
52, the charge is forcibly extracted, and the charge extraction and the discharge are alternately repeated according to the short-time switching of the signal YCLK or the signal M. That is, the transistor 151
Sinks current from all liquid crystal layers 18, while transistor 152 emits current to all liquid crystal layers 18. In particular, supply lines for the selection voltages V1 and V6 of the scanning signal
Since it was used to extract charges from the liquid crystal layer 18, the potential of the two supply lines was near the selection voltage at the beginning of the power-off detection, and the TFD element 20 could be turned on.
The accumulated charges can be alternately drained from the liquid crystal layer 18 to the V1 side and the V6 side via the element 20. During the power-off operation, the positive and negative voltages are alternately applied to the liquid crystal layer 18, so that even if the voltage stored in the pixel at the power-off timing is at any positive or negative voltage level, the charge is discharged. Can be done.

Therefore, all the liquid crystal layers 18 are equivalent to being connected to a kind of fixed potential, and the charges stored therein are cleared quickly and at a constant speed (FIG. 16). (F)). In the present embodiment, the connection between each data line and the voltage supply line V1 or V6 is switched according to the frequency of the signal YCLK or the signal M. However, if the clock signal has a frequency higher than 1 / 2H, other signals may be used. May be synchronized.

Therefore, according to the liquid crystal display device of this embodiment, the electric charge accumulated in the liquid crystal layer is not dependent on factors such as the resistance and size of the pixel electrode, the material of the liquid crystal, and the distance between the substrates. It is easy to set the time until it reaches zero.

[Liquid Crystal Display Device of Second Embodiment] Next, a liquid crystal display device according to a second embodiment of the present invention will be described.

The constant current circuit 150a (see FIG. 4) according to the first embodiment indirectly connects the supply lines of the voltages V1 and V6 to the ground line based on the level transition of the signals PWR + and PWR-. The constant current circuit 150b according to the second embodiment includes a power supply voltage Vc
This is performed directly by the voltage drop of c.

Therefore, unlike the first embodiment, the liquid crystal display device of the second embodiment shown in FIG.
PWR- is not supplied to the constant current circuit 150b.

The details of the constant current circuit 150b will be described with reference to FIG. As shown in the figure, the power supply voltage Vcc is directly supplied to the gate of the transistor 153, the source is grounded, and the drain is
Voltage V0 output by C-DC converter 130a
Of V7, it is pulled up to voltage V1 via resistor R11. The drain of the pulled-up transistor 153 is connected to the gate of the transistor 154, the source is grounded, and the drain is connected to the supply line of the voltage V1.

That is, when the power supply voltage Vcc is the normal voltage when the power is on, the transistor 153 is on. However, when the power supply voltage Vcc drops below the voltage Vth, the transistor 153 is turned off and the transistor 153 is turned off.
4 is pulled up and turned on. Therefore, the voltage
The configuration is such that the V1 supply line is connected to the ground line via the transistor 154.

On the other hand, the gate of transistor 155 is grounded, the drain is pulled down to voltage V6 of voltages V0 to V7 via resistor R12, and the source is connected to the supply line of power supply voltage Vcc. ing. The source of the transistor 155 that is pulled down is connected to the gate of the transistor 156, the source is connected to the supply line of the voltage V6, and the drain is the power supply voltage.
Connected to Vcc supply line.

That is, when the power supply voltage Vcc is the normal voltage when the power is on, the transistor 155 is off, but when the power supply voltage Vcc drops below the voltage Vth, the transistor 155 is turned on and the transistor 155 is turned on.
6 also changes from the off state to the on state. Therefore, the supply line of the voltage V6 is connected to the supply line of the power supply voltage Vcc. The power supply voltage Vcc is as shown in FIG.
As shown in FIG. 7, the level eventually reaches the ground level.
6 is substantially equivalent to the configuration of connecting to a ground line. Therefore, the transistor 15 in the constant current circuit
Reference numerals 4 and 156 serve as constant current sources for supplying a current for setting the supply line to the ground potential.

The other components are the same as in the first embodiment. That is, when the power supply voltage Vcc drops, all the scanning lines Y1 to Yj are alternately connected to the supply lines of the voltages V1 and V6 and switched at a high frequency. Since the supply lines of the voltages V1 and V6 gradually become the ground level by the transistors 154 and 156 in the constant current circuit 150b, the charges accumulated in all the liquid crystal layers 18 are rapidly and similarly to the first embodiment. It becomes possible to clear at a constant speed.

[Liquid Crystal Display Device of Third Embodiment] Next, a liquid crystal display device according to a third embodiment of the present invention will be described. In addition, parts that are not described have the same configuration as the first embodiment.

In the first or second embodiment, the constant current circuit 150a or 150b
When the drop of the power supply voltage Vcc is detected, the supply lines of the voltages V1 and V6 are connected to the ground line.
In the embodiment, the DC-DC converter 130b connects the supply lines of the voltages V1 and V6 and the ground line.

For this reason, as shown in FIG. 19, the liquid crystal display device of the third embodiment has a constant current circuit 150a or 1
Instead of 50b being present, signal PWR + and signal PWR-
It is configured to be supplied to the C-DC converter 130b. In the DC-DC converter 130b, the final-stage transistors that output the voltages V1 and V6 are configured substantially as shown by the transistors 151 and 152 in FIG. 15, respectively.

That is, the DC-DC converter 13
In the case of 0b, the last-stage transistor is configured such that the value of the suction current from the supply line of the voltage V1 and the value of the discharge current to the supply line of the voltage V6 are large.

Accordingly, also in the liquid crystal display device of the third embodiment, the charges accumulated in all the liquid crystal layers 18 can be cleared quickly and at a constant speed, as in the first and second embodiments. Becomes

[Liquid Crystal Display Device of Fourth Embodiment]
A liquid crystal display according to a fourth embodiment of the present invention will be described. In addition, parts that are not described have the same configuration as the first embodiment.

In the first to third embodiments described above,
Each pixel 16 at a position corresponding to the intersection of the scanning lines Y1 to Yj and the data lines X1 to Xi of the liquid crystal display panel 10 is formed by electrically connecting the two-terminal nonlinear element 20 and the liquid crystal layer 18 in series. Met. In the present embodiment, the scanning lines (scanning electrodes) Y1 to Yj arranged in a stripe shape intersect with the data lines (data electrodes) X1 to Xi arranged in a stripe shape, and the liquid crystal layer at the intersecting portion intersects each of the pixels 16 to form a pixel 16. And no switching element is arranged in each pixel 16. That is, the liquid crystal display panel 10 has the first substrate having the scanning lines Y1 to Yj formed on the inner surface and the second substrate having the data lines X1 to Xi formed on the inner surface opposed to each other. It is configured by sandwiching an STN (super twisted nematic) type liquid crystal 18 having a twist orientation of a degree or more. Although not shown, a retardation plate is disposed on at least one of the outer sides of the pair of substrates, and a pair of polarizing plates is disposed with the pair of substrates and the retardation plate interposed therebetween. Specifically, in FIG. 4, FIG. 17, FIG. 19, etc., except for the TFD element 20,
The configuration is such that the voltage difference between the scanning line and the data line is directly applied to the liquid crystal layer 18 of each pixel 16.

FIG. 20 is a diagram showing driving waveforms of the liquid crystal display device of this embodiment. The driving method shown in FIG. 20 selects four scanning lines (four lines) simultaneously and sequentially selects the scanning lines in units of four lines (Multi-Line Selecti).
on). Therefore, the scanning lines selected at the same time
Selection voltage of signal polarity defined based on orthonormal matrix
V2 or -V2 is applied. This orthonormal matrix defines the signal polarity of a selection voltage applied to, for example, one frame period for simultaneously selected scanning lines. For example,
If four selections are made in one frame by simultaneous selection of four lines, a matrix of 4 rows and 4 columns is obtained.

In FIG. 20, Y1 to Y8 are scanning signal waveforms applied from scanning signal driving circuit 100 to scanning lines Y1 to Y8, and X1 is data signal driving circuit 110 to data line X1.
Is a data signal waveform applied to the data signal. For example, the signal polarity of the selection voltage of one of the four lines to be simultaneously selected and the selection voltage of the other three lines are reversed, and each line is selected four times in one frame period, of which the opposite of the other lines is selected. The selection voltage of the signal polarity is applied once. In FIG. 20, each line is selected once (1H period) for each of the fields f1 to f4. It is to be noted that, instead of selecting the scanning lines in a dispersed manner on the time axis within one frame period (1F), each scanning line is continuously selected within one frame period, and the remaining period is set as a non-selection period. The pulse waveform to be set may be used.

On the other hand, for the data lines X1 to Xi, according to the result of the matrix operation of the above-described orthonormal matrix and the display data (ON or OFF) of the pixel at the intersection of the four scanning lines and the data line. , V2, V1, Vc, -V1, -V2. Therefore, in the first 1H of the data line X1 shown in FIG. 20, the operation result of the matrix of the on / off data of the four pixels at the intersection of the data line X1 and the scanning lines Y1 to Y4 and the above orthonormal matrix Is selected and applied to the data line X1.

In such a simple matrix type liquid crystal display device, the driving voltages Vc, V1 to V3, and -V1 to -V3
The level voltage is DC-DC as in the above-described embodiment.
It is formed by converters 130a and 130b. The center voltage Vc is a ground voltage.

Also in the liquid crystal display device of the present embodiment, the configuration is such that the transistors 151 and 152 shown in FIG. 15 or the transistors 154 and 156 shown in FIG. 18 are connected to the voltage supply lines V3 and -V3 of the scanning signal. By adopting or adopting the same configuration of the DC-DC converter 130b as shown in FIG. 19, the off or drop of the power supply voltage Vcc is detected, and the supply lines of the voltages V3 and -V3 are grounded. Can be connected to a wire. Further, in the scanning signal driving circuit 100, all the scanning lines Y1 to Yj are alternately connected to the voltage supply lines V3 and -V3 in synchronization with a clock signal having a frequency much higher than 1H, as in the above-described embodiment. , All the scanning lines Y1 to Yj can be connected to the supply lines of the voltages V3 and -V3 alternately and at a high frequency. Since the supply lines of the voltages V3 and -V3 gradually become the ground level (Vc), the charges accumulated in all the liquid crystal layers 18 are cleared quickly and at a constant speed, as in the above-described embodiment. It becomes possible. In particular, since the scanning signal has a larger amplitude than the data signal, while alternately applying the positive and negative selection voltages of the scanning signal to the liquid crystal layer and converging this voltage to the ground potential,
When the charge of the liquid crystal layer is extracted, a voltage higher than the storage voltage of the liquid crystal layer is applied, so that the charge is easily discharged.

In the case of the present embodiment, the high frequency clock for transferring the data signals GD0 to GDn at high speed to the data signal driving circuit 110 is supplied to the scanning signal driving circuit 100 and the two voltage supply lines V3 and -V3. It is preferable to use it for connection switching control between.

The liquid crystal layer 18 may be connected to a fixed potential via a data line instead of a scanning line. That is, FIG. 1 shows the relationship between the supply line of the drive voltage V1 and -V1 supplied to the data lines X1 to Xi or the supply line of the set of V2 and -V2.
18 or the transistors 151 and 152 shown in FIG.
19, or a DC-D similar to that shown in FIG.
By employing the configuration of the C converter 130b or the like, it is possible to detect the off or drop of the power supply voltage Vcc and connect the supply line to the ground line. Further, in the data signal drive circuit 110, as in the above-described embodiment, all the data lines X1 to Xi are synchronized with a clock signal having a frequency much higher than 1H, and the pair of supply lines V1 and -V1 are connected to each other. , Or between pairs of supply lines of V2 and -V2, all of which are connected alternately through the supply lines of the voltages V1, -V1 or the supply lines of the voltages V2, -V2. Can be connected to the ground line. Then, the supply lines of the voltages V1 and -V1 or the voltages V2 and -V2 gradually become the ground level (Vc) by the transistors connected to the voltage supply lines. The charge stored in the layer 18 can be cleared quickly and at a constant speed.

As described above, both the connection of the scanning line to the ground line and the connection of the data line to the ground line are performed together, so that the electric charge of the liquid crystal layer is rapidly extracted. Good.

[Modification] In the first to fourth embodiments described above, the power-off is detected indirectly by the drop of the power supply voltage Vcc. However, the power-off is directly detected. Then, the signal PWR + and the signal PWR- may be generated to clear the charge accumulated in the liquid crystal layer as in the above-described embodiment.

In the first to fourth embodiments, when power off is detected due to a drop in the power supply voltage Vcc, all of the scanning lines Y1 to Yj are alternately switched to two voltage supply lines. And these two lines are connected to the ground line via the transistors 151 and 152. However, the data line X1 is connected in accordance with the signal PWR + or the signal PWR-.
To Xi may be simultaneously connected to the ground line. That is, as shown in FIG. 11, the signal PWR + or the signal PWR- is supplied to the data signal driving circuit 110, and the data signal driving circuit 110
A configuration in which all of the data lines X1 to Xi are connected to the ground line by the level transition of PWR- may be used. In FIG. 11, a transistor 160 is connected between the ground line and the data line Xi, and the signal PWR + is
0 is input to the gate, and when the power is turned off, the transistor 1
The data line Xi may be connected to the ground line by turning on 60. In this case, the transistor 160 is connected between each of the data lines X1 to Xi and the ground line. The scanning line may be connected to the ground potential by the method of the above-described embodiment, and the data line may be connected to the ground potential.

Further, in the first to third embodiments,
When power-off is detected due to a drop in the power supply voltage Vcc, all of the scanning lines Y1 to Yj are alternately connected to supply lines for the selection voltages V1 and V6 of the scanning signal that determines the display state of the pixel in the charging mode. However, a configuration may be adopted in which the selection mode is alternately connected to the supply lines of the selection voltages V2 and V5 of the scanning signal that determines the display state of the pixel in the discharge mode.

[Electronic Equipment: Part 1] Next, the first
Some examples in which the liquid crystal display devices of the fourth to fourth embodiments are used in electronic devices will be described.

First, a video projector using the liquid crystal display device as a light valve will be described. FIG.
FIG. 1 is a plan view showing a configuration example of a video projector.

As shown in this figure, a lamp unit 1102 including a white light source such as a halogen lamp is provided inside a video projector 1100. The projection light emitted from the lamp unit 1102 is transmitted to a plurality of mirrors 1106, 1 arranged in a light guide 1104.
.., And two dichroic mirrors 110
8 are separated into three primary colors of RGB, and liquid crystal panels 1110R and 111 serving as light valves corresponding to the respective primary colors.
OB and 1110G.

The configuration of the liquid crystal panels 1110R, 1110B and 1110G is the above-described liquid crystal display panel 10, and is driven by R, G and B primary color signals supplied from a circuit (not shown). Now, the light modulated by these liquid crystal panels is transmitted to the dichroic prism 111.
2 is incident from three directions. In the dichroic prism 1112, the R and B lights are refracted at 90 degrees, while the G light travels straight. Therefore, as a result of combining the images of each color, a color image is projected on a screen or the like via the projection lens 1114.

The liquid crystal panels 1110R, 1110B
And 1110G have a dichroic mirror 1108
Accordingly, light corresponding to each of the primary colors of R, G, and B enters, so that it is not necessary to provide a color filter on the counter substrate 32.

[Electronic Apparatus: Part 2] An example in which the liquid crystal display device is applied to a personal computer will be described. FIG. 22 is a front view showing the configuration of this personal computer. In the figure, a personal computer 1200 has a main body 12 having a keyboard 1202.
04 and a liquid crystal display 1206. The liquid crystal display 1206 is configured by adding a color filter and a backlight to the liquid crystal display panel 10 described above.

[Electronic Apparatus: Part 3] Next, an example in which a liquid crystal display panel is applied to a pager will be described. FIG.
FIG. 2 is an exploded perspective view showing the structure of the pager. As shown in this figure, the pager 1300 is a metal frame 1
In 302, the liquid crystal display panel 10 is connected to the light guide 1306 including the backlight 1306 a and the circuit board 13.
08, the first and second shield plates 1310 and 1312 are housed together. The liquid crystal display panel 10 and the circuit board 10 are electrically connected to each other by the two elastic conductors 1314 and 1316 for the counter substrate 32 and by the film tape 1318 for the element array substrate 30. .

Note that, in addition to the electronic devices described with reference to FIGS. 21 to 23, a liquid crystal television, a viewfinder type, a monitor direct-view type video tape recorder, a car navigation device, an electronic organizer, a calculator, a word processor, Workstations, mobile phones, video phones, POS terminals,
A device including a touch panel and the like are examples of the electronic device. It goes without saying that the present invention can be applied to these various electronic devices.

[0158]

As described above, according to the present invention,
When the power supply to the liquid crystal display device is detected, the liquid crystal layer is connected to a fixed potential via a constant current source, so that the electric charge accumulated in the liquid crystal layer can be quickly transferred without depending on each device. As a result, the deterioration of the liquid crystal can be prevented.

[Brief description of the drawings]

FIG. 1A is a plan view illustrating a layout for one pixel of a liquid crystal panel substrate to which a TFD element is applied, and FIG. 1B is a cross-sectional view taken along line AA.

FIG. 2 is a cross-sectional view showing the structure of another TFD element.

3A is a plan view showing a layout for one pixel of a liquid crystal panel substrate to which another TFD element is applied, and FIG. 3B is a cross-sectional view taken along the line BB.

FIG. 4 is a block diagram illustrating a main configuration of the liquid crystal display device according to the first embodiment of the present invention.

FIG. 5 is a partially cutaway perspective view showing the configuration of the liquid crystal display panel.

FIG. 6 is a block diagram illustrating a detailed configuration of a scanning signal driving circuit.

FIG. 7 is a timing chart showing a data fetching operation in the scanning signal driving circuit.

FIG. 8 is a diagram showing a relationship between parallel data D0, D1, and D2 supplied to the scanning signal driving circuit and an output voltage.

FIG. 9 is a diagram showing a magnitude relationship between output voltages.

FIG. 10 is a diagram showing voltage waveforms showing an output operation of a scanning signal by the scanning signal driving circuit.

FIG. 11 is a block diagram showing a detailed configuration of a data signal drive circuit.

FIG. 12 is a block diagram illustrating a detailed configuration of a drive control circuit.

FIGS. 13A to 13D are driving waveform diagrams illustrating driving examples of a liquid crystal display panel, respectively.

FIG. 14 is a circuit diagram illustrating a configuration of an off-sequence circuit.

FIG. 15 is a circuit diagram illustrating a configuration of a constant current circuit according to the first embodiment.

FIGS. 16A to 16F are timing charts each showing an operation when the power is turned off.

FIG. 17 is a block diagram illustrating a main configuration of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 18 is a circuit diagram illustrating a configuration of a constant current circuit according to the second embodiment.

FIG. 19 is a block diagram illustrating a main configuration of a liquid crystal display device according to a third embodiment of the present invention.

FIG. 20 is a diagram showing driving waveforms indicating the operation of the liquid crystal display device according to the fourth embodiment of the present invention.

FIG. 21 is a cross-sectional view illustrating a configuration of a liquid crystal projector as an example of an electronic apparatus to which the liquid crystal display panel is applied.

FIG. 22 is a front view illustrating a configuration of a personal computer as an example of an electronic device to which the liquid crystal display panel is applied.

FIG. 23 is an exploded perspective view illustrating a configuration of a pager as an example of an electronic apparatus to which the liquid crystal display panel is applied.

[Explanation of symbols]

10 liquid crystal display panel 12, 48, X1 to Xi scanning line 14, Y1 to Yj data line 16, pixel area (pixel) 18 liquid crystal layer 20, 40 TFD element 22, first metal film (first metal), 24, oxide film (insulator), 26, second metal film (second metal), 30, element array substrate, 32, counter substrate, 36, 45 ... pixel electrode, 100 ... scanning signal drive circuit, 110 ... data signal drive circuit, 120 ... drive control circuit, 130a, 130b ... DC-DC converter, 140 ... off-sequence circuit (detection means 150a, 150b ... constant current circuit (fixed potential, switch circuit), 151, 152, 154, 155 ... transistor (first connection means), 153, 155 ... transistor (detection means)

Claims (22)

[Claims] 1. A method of controlling a liquid crystal display device for performing a desired display by controlling an amount of electric charge stored in a liquid crystal layer, comprising: a step of detecting power-off; Electrically connecting the liquid crystal layer to a predetermined fixed potential. 2. The control method for a liquid crystal display device according to claim 1, wherein when the power-off is detected, a signal line for applying a voltage to the liquid crystal layer is electrically connected to the fixed potential. 3. When the power supply is turned off, a signal line electrically connected to the liquid crystal layer is electrically connected to a specific voltage supply line, and the specific voltage supply line is connected to the fixed potential. 2. The control method for a liquid crystal display device according to claim 1, wherein the connection is established. 4. The specific voltage supply line includes a first voltage supply line that supplies a positive voltage with respect to the fixed potential, and a second voltage supply line that supplies a negative voltage. When the power-off is detected, the signal line is connected to the first
4. The control method according to claim 3, wherein the voltage supply line and the second voltage supply line are alternately connected. 5. The method according to claim 1, wherein the signal line is alternately connected to the first voltage supply line and the second voltage supply line in response to a clock signal having a cycle shorter than a half horizontal scanning period. The control method for a liquid crystal display device according to claim 4, wherein: 6. A driving device for a liquid crystal display device for performing a desired display by controlling an amount of electric charge stored in a liquid crystal layer, comprising: detecting means for detecting power-off; and detecting power-off by the detecting means. And a connection means for connecting the liquid crystal layer to a fixed potential. 7. The connection means includes: first connection means for connecting the liquid crystal layer to a specific line when power off is detected by the detection means; and a connection means for connecting the specific line to a fixed potential. 7. The driving device for a liquid crystal display device according to claim 6, further comprising two connection means. 8. The driving device for a liquid crystal display device according to claim 6, wherein said detecting means detects that the power supply is turned off when the power supply voltage becomes equal to or lower than a threshold value. 9. The liquid crystal display device according to claim 6, wherein the connection unit is a switching unit that connects the liquid crystal layer and a ground line when power off is detected by the detection unit. Drive. 10. The driving device for a liquid crystal display device according to claim 6, wherein said connection means electrically connects a signal line for applying a voltage to said liquid crystal layer to said fixed potential. 11. The liquid crystal display according to claim 11, wherein the connection unit electrically connects a signal line electrically connected to the liquid crystal layer to a specific line, and connects the specific line to the fixed potential. A driving device for a liquid crystal display device according to claim 6. 12. The specific line includes a first supply line for supplying a positive voltage with respect to the fixed potential and a second supply line for supplying a negative voltage with respect to the fixed potential. 12. The driving device for a liquid crystal display device according to claim 11, wherein, when detected, the connection unit alternately connects the signal line to the first supply line and the second supply line. 13. The signal line according to claim 1, wherein the signal line is alternately connected to the first supply line and the second supply line according to a clock signal having a cycle shorter than a half horizontal scanning period. The driving device for a liquid crystal display device according to claim 12. 14. A liquid crystal display device for performing a desired display by controlling the amount of charge stored in a liquid crystal layer with a scanning signal and a data signal, comprising: detecting means for detecting power-off; When OFF is detected, control means for instructing connection to a specific line, and, according to the instruction, any of a scan line to which the scan signal is supplied or a data line to which the data signal is supplied,
Alternatively, it is provided with first connection means for connecting both of them to the specific line, and second connection means for connecting the specific line to a fixed potential when power-off is detected by the detection means. A liquid crystal display device characterized by the above-mentioned. 15. One substrate provided with a data line,
A liquid crystal display panel having a pixel on which a non-linear element and a liquid crystal layer are connected in series between the data line and the scanning line, and a detection circuit for detecting power off; And a switch circuit for connecting a supply line of a selection voltage to be applied to the scanning line to a ground line when power off is detected by the detection circuit. 16. The switch circuit, when the power-off is detected, connects the scanning line to a supply line that supplies a voltage for turning on the nonlinear element, and connects the supply line to a ground line. The liquid crystal display device according to claim 15, wherein: 17. The supply line includes a first supply line for supplying a positive selection voltage with respect to a ground potential and a second supply line for supplying a negative selection voltage. 17. The liquid crystal display device according to claim 16, wherein the first supply line and the second supply line are connected alternately. 18. The liquid crystal display device according to claim 15, wherein the nonlinear element is a two-terminal nonlinear element. 19. The liquid crystal display device according to claim 18, wherein the two-terminal nonlinear element is a thin-film diode element composed of a first metal-insulator-second metal. 20. One substrate provided with a data line,
A liquid crystal display panel in which a liquid crystal layer is sandwiched between the other substrate provided with a scanning line; a detection circuit for detecting power off; and when the detection circuit detects power off, the scan line or the A switch circuit for connecting a supply line of a voltage applied to the data line to a predetermined constant potential. 21. When the power-off is detected, the scanning line or the data line supplies a first supply line for supplying a positive voltage to the predetermined constant potential and a second supply line for supplying a negative voltage. 2 are alternately connected to the first supply line and the second supply line.
21. The liquid crystal display device according to claim 20, wherein said supply line is connected to said predetermined constant potential. 22. An electronic apparatus comprising the liquid crystal display device according to claim 14.