ITMI20050773A1 - Passivazione di fusibili a traccia - Google Patents

Passivazione di fusibili a traccia

Info

Publication number
ITMI20050773A1
ITMI20050773A1 IT000773A ITMI20050773A ITMI20050773A1 IT MI20050773 A1 ITMI20050773 A1 IT MI20050773A1 IT 000773 A IT000773 A IT 000773A IT MI20050773 A ITMI20050773 A IT MI20050773A IT MI20050773 A1 ITMI20050773 A1 IT MI20050773A1
Authority
IT
Italy
Prior art keywords
passivation
track fuses
fuses
track
Prior art date
Application number
IT000773A
Other languages
English (en)
Italian (it)
Inventor
Dieter Arand
Hubert Benzel
Gabriele Godzik
Roland Guenschel
Andreas Junger
Polichronis Lepidis
Horst Magenau
Lutz Mueller
Matthias Neubauer
Juergen Nitsche
Frank Schaefer
Oliver Schatz
Frank Wehrmann
Original Assignee
Bosch Gmbh Robert
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bosch Gmbh Robert filed Critical Bosch Gmbh Robert
Publication of ITMI20050773A1 publication Critical patent/ITMI20050773A1/it

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C17/00Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
IT000773A 2004-05-03 2005-04-29 Passivazione di fusibili a traccia ITMI20050773A1 (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE102004021541A DE102004021541A1 (de) 2004-05-03 2004-05-03 Passivierung von Brennstrecken

Publications (1)

Publication Number Publication Date
ITMI20050773A1 true ITMI20050773A1 (it) 2005-11-04

Family

ID=35169515

Family Applications (1)

Application Number Title Priority Date Filing Date
IT000773A ITMI20050773A1 (it) 2004-05-03 2005-04-29 Passivazione di fusibili a traccia

Country Status (4)

Country Link
JP (1) JP2005322929A (fr)
DE (1) DE102004021541A1 (fr)
FR (1) FR2869721A1 (fr)
IT (1) ITMI20050773A1 (fr)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5847596Y2 (ja) * 1979-09-05 1983-10-29 富士通株式会社 半導体装置
JP2695548B2 (ja) * 1991-09-04 1997-12-24 富士通株式会社 半導体装置
US5622892A (en) * 1994-06-10 1997-04-22 International Business Machines Corporation Method of making a self cooling electrically programmable fuse
EP0762498A3 (fr) * 1995-08-28 1998-06-24 International Business Machines Corporation Fenêtre pour fusible avec une épaisseur contrÔlée d'oxyde d'un fusible

Also Published As

Publication number Publication date
JP2005322929A (ja) 2005-11-17
FR2869721A1 (fr) 2005-11-04
DE102004021541A1 (de) 2005-12-08

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