IT978720B - Sistema e circuito asincrono con singola linea per bit - Google Patents

Sistema e circuito asincrono con singola linea per bit

Info

Publication number
IT978720B
IT978720B IT19922/73A IT1992273A IT978720B IT 978720 B IT978720 B IT 978720B IT 19922/73 A IT19922/73 A IT 19922/73A IT 1992273 A IT1992273 A IT 1992273A IT 978720 B IT978720 B IT 978720B
Authority
IT
Italy
Prior art keywords
circuit
single line
per bit
line per
asynchronous system
Prior art date
Application number
IT19922/73A
Other languages
English (en)
Original Assignee
Dyad Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dyad Systems Inc filed Critical Dyad Systems Inc
Application granted granted Critical
Publication of IT978720B publication Critical patent/IT978720B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Shift Register Type Memory (AREA)
  • Read Only Memory (AREA)
IT19922/73A 1972-02-01 1973-02-01 Sistema e circuito asincrono con singola linea per bit IT978720B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US22252072A 1972-02-01 1972-02-01

Publications (1)

Publication Number Publication Date
IT978720B true IT978720B (it) 1974-09-20

Family

ID=22832548

Family Applications (1)

Application Number Title Priority Date Filing Date
IT19922/73A IT978720B (it) 1972-02-01 1973-02-01 Sistema e circuito asincrono con singola linea per bit

Country Status (7)

Country Link
US (1) US3736575A (it)
JP (1) JPS4887740A (it)
CA (1) CA978604A (it)
DE (1) DE2304007A1 (it)
GB (1) GB1427993A (it)
IT (1) IT978720B (it)
NL (1) NL7301371A (it)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3972034A (en) * 1975-05-12 1976-07-27 Fairchild Camera And Instrument Corporation Universal first-in first-out memory device
US4163291A (en) * 1975-10-15 1979-07-31 Tokyo Shibaura Electric Co., Ltd. Input-output control circuit for FIFO memory
US4110842A (en) * 1976-11-15 1978-08-29 Advanced Micro Devices, Inc. Random access memory with memory status for improved access and cycle times
NL7713708A (nl) * 1977-12-12 1979-06-14 Philips Nv Informatiebuffergeheugen van het "eerst-in, eerst-uit" type met vaste ingang en variabele uitgang.
FR2573890B1 (fr) * 1984-11-27 1987-07-24 Bendix Electronics Sa Dispositifs electroniques d'acquisition des signaux periodiques asynchrones
US4679213A (en) * 1985-01-08 1987-07-07 Sutherland Ivan E Asynchronous queue system
FR2632091A1 (fr) * 1988-05-30 1989-12-01 Chauffour Jean Claude Procede de memorisation electronique de donnees au moyen de cellules a deux etats, et ses moyens de mise en oeuvre

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3544992A (en) * 1967-06-01 1970-12-01 Bell Telephone Labor Inc Code translator

Also Published As

Publication number Publication date
DE2304007A1 (de) 1973-08-09
US3736575A (en) 1973-05-29
JPS4887740A (it) 1973-11-17
GB1427993A (en) 1976-03-10
NL7301371A (it) 1973-08-03
CA978604A (en) 1975-11-25

Similar Documents

Publication Publication Date Title
IT957498B (it) Sistema e circuito limitatore e o amplificatore di ampiezza
IT956847B (it) Sistema di memoria perfezionato
IT963417B (it) Sistema di memoria perfezionato
ES160142Y (es) Recipiente sellado y flexible.
IT938913B (it) Sistema elettronico modulare
IT946272B (it) Sistema di collegamento
IT969688B (it) Sistema di trasmissione soppresso re di sovratensioni
IT958934B (it) Sistema pirotecnico multiplo
IT978463B (it) Metodo e dispositivo di aerazione
IT970965B (it) Sistema di memoria perfezionato
BE774523Q (nl) Breek- en schepinrichting
BE783579A (fr) Systemes et procedes de detection de mots numeriques uniques
IT950719B (it) Sistema di memoria perfezionato
IT951497B (it) Sistema di memoria perfezionato
IT969956B (it) Sistema di isolamento termico
BR7302939D0 (pt) Conficador e decondificador de sequencia de linhas
FI45789C (fi) Laite säiliöiden ja muiden rakennuksien päällystysvaipassa.
IT978720B (it) Sistema e circuito asincrono con singola linea per bit
BR7302812D0 (pt) Dispositivo de centragem,e acoplamento flexivel dispositivo de centragem, e acoplamento flexivel
TR17380A (tr) Ueruen ve usul
BE769922R (fr) Polymercapto-polyphosphites et polyphosphates
BR7106263D0 (pt) Aperfeicoamento em circuito de engate amplificador de sentido
IT975315B (it) Circuito di tenuta di linea telefo nica
NO136864C (no) B{re- og koplingsinnretning for logiske kretsenheter
NL151539B (nl) Schakel- en geheugenelement.