IT955882B - Metodo per la fabbricazione di dispositivi semiconduttori e dispo sitivi cosi ottenuti - Google Patents
Metodo per la fabbricazione di dispositivi semiconduttori e dispo sitivi cosi ottenutiInfo
- Publication number
- IT955882B IT955882B IT24886/72A IT2488672A IT955882B IT 955882 B IT955882 B IT 955882B IT 24886/72 A IT24886/72 A IT 24886/72A IT 2488672 A IT2488672 A IT 2488672A IT 955882 B IT955882 B IT 955882B
- Authority
- IT
- Italy
- Prior art keywords
- devices
- sitive
- manufacturing
- semiconductor devices
- semiconductor
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15060971A | 1971-06-07 | 1971-06-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| IT955882B true IT955882B (it) | 1973-09-29 |
Family
ID=22535286
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IT24886/72A IT955882B (it) | 1971-06-07 | 1972-05-26 | Metodo per la fabbricazione di dispositivi semiconduttori e dispo sitivi cosi ottenuti |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPS5116270B1 (enExample) |
| DE (1) | DE2218892A1 (enExample) |
| FR (1) | FR2140376B1 (enExample) |
| GB (1) | GB1323850A (enExample) |
| IT (1) | IT955882B (enExample) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5010101A (enExample) * | 1973-05-25 | 1975-02-01 |
-
1972
- 1972-03-16 FR FR727209924A patent/FR2140376B1/fr not_active Expired
- 1972-04-05 JP JP47033553A patent/JPS5116270B1/ja active Pending
- 1972-04-19 DE DE19722218892 patent/DE2218892A1/de not_active Withdrawn
- 1972-05-19 GB GB2356072A patent/GB1323850A/en not_active Expired
- 1972-05-26 IT IT24886/72A patent/IT955882B/it active
Also Published As
| Publication number | Publication date |
|---|---|
| GB1323850A (en) | 1973-07-18 |
| DE2218892A1 (de) | 1972-12-21 |
| FR2140376A1 (enExample) | 1973-01-19 |
| JPS5116270B1 (enExample) | 1976-05-22 |
| FR2140376B1 (enExample) | 1974-06-28 |
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