IT940702B - Sistema di memoria perfezionato per complessi di elaborazione dei dati - Google Patents

Sistema di memoria perfezionato per complessi di elaborazione dei dati

Info

Publication number
IT940702B
IT940702B IT31320/71A IT3132071A IT940702B IT 940702 B IT940702 B IT 940702B IT 31320/71 A IT31320/71 A IT 31320/71A IT 3132071 A IT3132071 A IT 3132071A IT 940702 B IT940702 B IT 940702B
Authority
IT
Italy
Prior art keywords
perfected
data processing
memory system
processing complexes
complexes
Prior art date
Application number
IT31320/71A
Other languages
English (en)
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of IT940702B publication Critical patent/IT940702B/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
    • G11C11/415—Address circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Static Random-Access Memory (AREA)
IT31320/71A 1970-12-28 1971-11-19 Sistema di memoria perfezionato per complessi di elaborazione dei dati IT940702B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10165870A 1970-12-28 1970-12-28

Publications (1)

Publication Number Publication Date
IT940702B true IT940702B (it) 1973-02-20

Family

ID=22285763

Family Applications (1)

Application Number Title Priority Date Filing Date
IT31320/71A IT940702B (it) 1970-12-28 1971-11-19 Sistema di memoria perfezionato per complessi di elaborazione dei dati

Country Status (11)

Country Link
US (1) US3740723A (it)
JP (1) JPS545657B1 (it)
BE (1) BE775348A (it)
CA (1) CA953032A (it)
CH (1) CH531238A (it)
DE (1) DE2163342C3 (it)
ES (1) ES398243A1 (it)
FR (1) FR2119928B1 (it)
GB (1) GB1320935A (it)
IT (1) IT940702B (it)
SE (1) SE383427B (it)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4371923A (en) * 1970-12-28 1983-02-01 Hyatt Gilbert P Computer system architecture
US4028675A (en) * 1973-05-14 1977-06-07 Hewlett-Packard Company Method and apparatus for refreshing semiconductor memories in multi-port and multi-module memory system
US3866183A (en) * 1973-08-31 1975-02-11 Honeywell Inf Systems Communications control apparatus for the use with a cache store
US3968478A (en) * 1974-10-30 1976-07-06 Motorola, Inc. Chip topography for MOS interface circuit
NL7507050A (nl) * 1975-06-13 1976-12-15 Philips Nv Geheugensysteem.
US3983544A (en) * 1975-08-25 1976-09-28 International Business Machines Corporation Split memory array sharing same sensing and bit decode circuitry
US4040029A (en) * 1976-05-21 1977-08-02 Rca Corporation Memory system with reduced block decoding
US4106109A (en) * 1977-02-01 1978-08-08 Ncr Corporation Random access memory system providing high-speed digital data output
US4181935A (en) * 1977-09-02 1980-01-01 Burroughs Corporation Data processor with improved microprogramming
US4298932A (en) * 1979-06-11 1981-11-03 International Business Machines Corporation Serial storage subsystem for a data processor
US4541075A (en) * 1982-06-30 1985-09-10 International Business Machines Corporation Random access memory having a second input/output port
US4719598A (en) * 1985-05-31 1988-01-12 Harris Corporation Bit addressable programming arrangement
US5587962A (en) * 1987-12-23 1996-12-24 Texas Instruments Incorporated Memory circuit accommodating both serial and random access including an alternate address buffer register
US5093807A (en) 1987-12-23 1992-03-03 Texas Instruments Incorporated Video frame storage system
US5138705A (en) * 1989-06-26 1992-08-11 International Business Machines Corporation Chip organization for an extendable memory structure providing busless internal page transfers
US5243703A (en) * 1990-04-18 1993-09-07 Rambus, Inc. Apparatus for synchronously generating clock signals in a data processing system
US6751696B2 (en) 1990-04-18 2004-06-15 Rambus Inc. Memory device having a programmable register
IL96808A (en) * 1990-04-18 1996-03-31 Rambus Inc Introductory / Origin Circuit Agreed Using High-Performance Brokerage
US5359722A (en) * 1990-07-23 1994-10-25 International Business Machines Corporation Method for shortening memory fetch time relative to memory store time and controlling recovery in a DRAM
US6002865A (en) * 1992-05-28 1999-12-14 Thomsen; Erik C. Location structure for a multi-dimensional spreadsheet
US5781687A (en) * 1993-05-27 1998-07-14 Studio Nemo, Inc. Script-based, real-time, video editor
US5924115A (en) * 1996-03-29 1999-07-13 Interval Research Corporation Hierarchical memory architecture for a programmable integrated circuit having an interconnect structure connected in a tree configuration
US6167486A (en) 1996-11-18 2000-12-26 Nec Electronics, Inc. Parallel access virtual channel memory system with cacheable channels
US6708254B2 (en) 1999-11-10 2004-03-16 Nec Electronics America, Inc. Parallel access virtual channel memory system
US7873795B2 (en) * 2005-03-22 2011-01-18 Hewlett-Packard Development Company, L.P. Multi-process support in a shared register
US10235103B2 (en) * 2014-04-24 2019-03-19 Xitore, Inc. Apparatus, system, and method of byte addressable and block addressable storage and retrival of data to and from non-volatile storage memory

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1190706B (de) * 1963-07-17 1965-04-08 Telefunken Patent In zwei abwechselnden Zyklen arbeitende programmgesteuerte elektronische digitale Rechenmaschine
US3341817A (en) * 1964-06-12 1967-09-12 Bunker Ramo Memory transfer apparatus
US3391390A (en) * 1964-09-09 1968-07-02 Bell Telephone Labor Inc Information storage and processing system utilizing associative memory
US3460094A (en) * 1967-01-16 1969-08-05 Rca Corp Integrated memory system
US3569938A (en) * 1967-12-20 1971-03-09 Ibm Storage manager
US3560935A (en) * 1968-03-15 1971-02-02 Burroughs Corp Interrupt apparatus for a modular data processing system
GB1215216A (en) * 1968-05-17 1970-12-09 Venner Ltd Improvements relating to integrated circuit chips
US3588845A (en) * 1968-09-09 1971-06-28 Cii Associative memory
US3588839A (en) * 1969-01-15 1971-06-28 Ibm Hierarchical memory updating system
US3609712A (en) * 1969-01-15 1971-09-28 Ibm Insulated gate field effect transistor memory array
US3641511A (en) * 1970-02-06 1972-02-08 Westinghouse Electric Corp Complementary mosfet integrated circuit memory

Also Published As

Publication number Publication date
SE383427B (sv) 1976-03-08
GB1320935A (en) 1973-06-20
DE2163342A1 (de) 1972-07-13
FR2119928B1 (it) 1976-09-03
CA953032A (en) 1974-08-13
BE775348A (fr) 1972-03-16
AU3713971A (en) 1973-06-28
DE2163342C3 (de) 1974-01-31
FR2119928A1 (it) 1972-08-11
CH531238A (de) 1972-11-30
DE2163342B2 (de) 1973-06-28
US3740723A (en) 1973-06-19
JPS545657B1 (it) 1979-03-19
ES398243A1 (es) 1974-09-16

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