IT9022445A1 - SYSTEM AND CIRCUIT FOR THE ESTIMATION OF THE ERROR SIGNAL IN THE UPDATE OF THE ADAPTIVE EQUALIZER IN NUMERICAL RADIO LINKS - Google Patents

Description

Description

Accompanying an industrial patent application entitled: "System and circuit for estimating the error signal in updating the adaptive equalizer in digital radio links"

Description of the invention:

The present invention relates to a system for estimating the error signal used in updating an adaptive equalizer.

In said system, the following is carried out: A) an estimate of the transmitted data and 8) the error is calculated using said estimate A) and the signal at the output of the equalizer. The invention also comprises the circuits for implementing the system in question.

State of the art:

Currently, the adaptive equalizer update in digital radio links takes place according to various techniques.

These techniques can be grouped into two families:

A) techniques independent of the phase of the signal carrier to be equalized

B) techniques that depend on the phase of the carrier of the signal to be equalized

The techniques of group A generally have the disadvantage of inducing a large noise in the operation of the adaptive equalizer; on the other hand, they have the advantage of allowing independent operation of the carrier estimation and equalization circuits.

The independent operation of said circuits ensures rapid achievement of good estimates of the carrier frequency and good values of the coefficients of the adaptive equalizer.

The techniques of group 8 generally have the disadvantage of introducing a mutual dependence of the carrier estimation and adaptive equalization circuits.

This dependence generally makes it slow to reach good estimates of the carrier frequency and good values of the coefficients of the adaptive equalizer.

On the other hand, the techniques of group B offer the advantage of inducing low noise in the operation of the adaptive equalizer.

Summary of the invention

The first object of the invention is to provide a system which does not have the aforementioned drawbacks: which allows in particular the introduction of a low noise in the operation of the adaptive equalizer and which allows the mutually independent operation of said equalizer and of the circuit for the carrier frequency estimation.

Another object is to provide a simple and effective circuitry for the implementation of said system.

General solution:

The solution idea according to the invention is based on a particular estimator of the transmitted data and on an equally critical calculator of the error necessary for updating the adaptive equalizer. This solution allows the minimization of an adequate functional of the signal at the output of the adaptive equalizer.

This functional is expressed by I:

In I, G (P) is the functional of order p to be minimized, E {.} Stands for the average value of what is contained in curly brackets, it is the complex signal at the output of the adaptive equalizer to the k-th signaling interval is the complex data transmitted at the k-th signaling interval.

One of the problems that arise in the minimization of GìP) is that of having good estimates of the modulus of the transmitted complex data.

Having said A the set of complex data belonging to the QAM signaling, the estimate of the modulus of the data transmitted at the k-th signaling interval, which we indicate with can conveniently take place according to II:

In II the notation indicates the value of the complex datum (belonging to set A) which minimizes the quantity within parentheses.

The complex error signal estimated at the k-th signaling interval relating to the functional G (P), which we indicate with, is obtained as indicated by III:

Figure 1 schematically illustrates, by means of functional blocks, the method of calculating the error signal.

In said figure 1 appear:

a block for estimating the modulus of the transmitted data (marked DEC, reference 33)

a block for estimating the error signal for updating the adaptive equalizer (marked with ER, ref. 36).

The complex signal at the output of the equalizer EQ (38) is used by the device for estimating the modulus of the transmitted data (line 32) to provide the estimate (line 34).

The device for calculating the error signal receives in input the complex signal at the output of the equalizer EQ (38) (line 35) and the estimate of the modulus of the transmitted data (line 34) and supplies to the output (line 37) the error signal that can be used for updating the adaptive equalizer.

The circuit for implementing the system according to the invention comprises: a signal squared elevator, a set of adders and a comparison operator between various quantities for the implementation of II; an elevator to the power p-2, two elevators to the power p, an adder and three multipliers for the implementation of III.

The various aspects and advantages of the invention will become clearer from the description of the embodiment represented by way of non-limiting purpose in the attached drawing (Figure 2).

Said drawing refers to obtaining the complex error signal relating to the functional G (P) of generic order p.

The signals zkp and zkq respectively represent the real part and the imaginary part of the complex signal

Block 5 marked with represents a circuit which calculates the square of the modulus of the complex signal that is applied to its input, ie the sum of the squares of the two real input signals (real part and imaginary part).

The block 6 marked with is representative of the circuit which calculates the p-th power of the module of the complex signal (consisting of a real part and an imaginary part) which is applied to its input.

Similarly, block 7 marked with calculates the order power (p-2) of the complex input signal module.

The blocks marked with (10-1, 10-2, ..., 10-n and 22) represent adder circuits.

The blocks marked with x (24, 27, 27 ') represent multiplier circuits.

Blocks marked with |. | (12-1, 12-2, ..., 12-n) represent rectifier circuits that calculate the absolute or modulus value of the real signal applied to the input.

The block 14 marked with CMPn is representative of a circuit having n inputs and an output, which compares the value of the inputs, identifies the symbol a which corresponds to the input signal of lesser value and calculates its module, supplying it to the output.

Block 16 marked with (.) P represents a booster circuit to the power p.

Block 18 marked with / - represents a change of sign. As shown schematically in Figure 2, the signals zkp and zkq are applied to lines 1 and 1 '.

Said signals are simultaneously applied to block 5 (through lines 2 and 2 '), to block 6 (through lines 3 and 3') and to block 7 (through lines 4 and 4 ').

The output signal at block 5 passes on line 8 and is therefore applied simultaneously to the n adders (10-1, 10-2, ..., 10-n of which in the figure only the first, the second and the nth) through lines 9-1, 9-2, -, 9-n.

The signals are applied to the aforementioned adders

which are all and only the squared modules changed in sign of the complex data belonging to the QAM signaling.

The outputs of said adders pass on lines 11-1, 11-2, ... 11-n and are applied to the rectifier circuits 12-1, 12-2, ..., 12-n.

The outputs of these are applied neatly to the n inputs of the circuit 14, through the lines 13-1, 13-2, ..., 13-n.

The output of the CMPn circuit is the estimate of the modulus of the transmitted complex data.

Through the line 15, said estimate is applied to the exponentiation circuit p (16), the output of which passes on the line 17 and is applied to the sign change circuit 18.

The output of circuit 18 (via line 19) and the output of block 6 (via line 20) are summed in adder 22.

The output of the adder 22 and the output of block 7 (respectively through the lines 23 and 21) are supplied as input to the multiplier 24, which in turn applies its output to the line 25 and therefore to the multipliers 28 and 28 ' (via lines 27 and 27 ').

The multipliers 28 and 28 'also receive the signals zkp and zkq (from the lines 26 and 26') in input and produce the signals (on the lines 29 and 29 ').

These latter signals represent the real part and the imaginary part of the complex signal which constitutes the output of the whole device.

Said complex signal is the estimate of the error signal that can be used for updating the adaptive equalizer in digital radio links.

Claims (8)

Claims: 1) System for estimating the error signal for updating the adaptive equalizer in digital radio links for QAM signals, characterized by the fact that at least: A) an estimate of the modulus of the data transmitted, according to formula II B) an estimate of the error using said estimate obtained in stage A), according to formula III. 2) System for estimating the modulus of the transmitted data according to claim 1, characterized by the fact of calculating, for the estimate A), the square of the modulus of the signal at the output of the equalizer and providing the estimate of the modulus of the transmitted data which minimizes the absolute value of the difference between the square of said estimate and the square of the signal modulus 3) System according to claim 2, characterized in that the estimate elaborated is made to coincide with the value of the module of one of the possible complex data transmitted on the QAM transmission considered. 4) System for the estimation of the error signal characterized by the fact that for the estimate B the product of three factors is made: the complex signal at the output of the equalizer the power of order (p-2) of the signal module at the output of said equalizer the difference between the p-th power of the signal module at the output of the equalizer and the p-th power of the estimate provided by estimator A. 5) Device for implementing the system according to the preceding claims characterized in that it comprises: C) a circuit for estimating the modulus of the transmitted data (estimate A), D) a circuit for estimating (estimate N) of the error that uses the estimate provided by circuit C. 6) Device according to claim 5, characterized by the fact that circuit C substantially comprises a squared module calculator, adders, absolute value extractors and a comparison circuit with n inputs capable of calculating the module of the symbol to which the minimum value input. 7) Device according to claim 5, characterized in that the circuit D substantially comprises: a power calculator of order p of a real signal a calculator of p-th power of the module of a complex signal a power calculator (p-2) -th of the module of a complex signal three multipliers, an adder and a change of sign. 8) System and devices essentially as described and represented.