IT8621235A0 - Procedimento per la fabbricazione di dispositivi integrati, in particolare dispositivi cmos adoppia sacca. - Google Patents

Procedimento per la fabbricazione di dispositivi integrati, in particolare dispositivi cmos adoppia sacca.

Info

Publication number
IT8621235A0
IT8621235A0 IT8621235A IT2123586A IT8621235A0 IT 8621235 A0 IT8621235 A0 IT 8621235A0 IT 8621235 A IT8621235 A IT 8621235A IT 2123586 A IT2123586 A IT 2123586A IT 8621235 A0 IT8621235 A0 IT 8621235A0
Authority
IT
Italy
Prior art keywords
devices
procedure
manufacture
double bag
particular double
Prior art date
Application number
IT8621235A
Other languages
English (en)
Other versions
IT1213457B (it
Inventor
Livio Baldi
Cappelletti Paolo Giuseppe
Original Assignee
Catania A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Catania A filed Critical Catania A
Priority to IT8621235A priority Critical patent/IT1213457B/it
Publication of IT8621235A0 publication Critical patent/IT8621235A0/it
Priority to EP87110269A priority patent/EP0254973B1/en
Priority to DE8787110269T priority patent/DE3780371T2/de
Priority to US07/075,718 priority patent/US4806501A/en
Priority to JP62183231A priority patent/JP2706723B2/ja
Application granted granted Critical
Publication of IT1213457B publication Critical patent/IT1213457B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H01L21/8228—Complementary devices, e.g. complementary transistors
    • H01L21/82285—Complementary vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/103—Mask, dual function, e.g. diffusion and oxidation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
IT8621235A 1986-07-23 1986-07-23 Procedimento per la fabbricazione di dispositivi integrati, in particolare dispositivi cmos adoppia sacca. IT1213457B (it)

Priority Applications (5)

Application Number Priority Date Filing Date Title
IT8621235A IT1213457B (it) 1986-07-23 1986-07-23 Procedimento per la fabbricazione di dispositivi integrati, in particolare dispositivi cmos adoppia sacca.
EP87110269A EP0254973B1 (en) 1986-07-23 1987-07-16 Method for making twin tub integrated devices, in particular twin tub cmos devices
DE8787110269T DE3780371T2 (de) 1986-07-23 1987-07-16 Methode zum herstellen doppelwanniger integrierter bauelemente, speziell cmos-bauelemente mit zwillingswannen.
US07/075,718 US4806501A (en) 1986-07-23 1987-07-20 Method for making twin tub CMOS devices
JP62183231A JP2706723B2 (ja) 1986-07-23 1987-07-22 ツインタブを有する半導体集積装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8621235A IT1213457B (it) 1986-07-23 1986-07-23 Procedimento per la fabbricazione di dispositivi integrati, in particolare dispositivi cmos adoppia sacca.

Publications (2)

Publication Number Publication Date
IT8621235A0 true IT8621235A0 (it) 1986-07-23
IT1213457B IT1213457B (it) 1989-12-20

Family

ID=11178814

Family Applications (1)

Application Number Title Priority Date Filing Date
IT8621235A IT1213457B (it) 1986-07-23 1986-07-23 Procedimento per la fabbricazione di dispositivi integrati, in particolare dispositivi cmos adoppia sacca.

Country Status (5)

Country Link
US (1) US4806501A (it)
EP (1) EP0254973B1 (it)
JP (1) JP2706723B2 (it)
DE (1) DE3780371T2 (it)
IT (1) IT1213457B (it)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5350491A (en) * 1992-09-18 1994-09-27 Advanced Micro Devices, Inc. Oxide removal method for improvement of subsequently grown oxides for a twin-tub CMOS process
EP0716443B1 (en) * 1994-12-08 2000-10-11 AT&T Corp. Fabrication of integrated circuit having twin tubs
US5573963A (en) * 1995-05-03 1996-11-12 Vanguard International Semiconductor Corporation Method of forming self-aligned twin tub CMOS devices
US5792680A (en) * 1996-11-25 1998-08-11 Vanguard International Semiconductor Corporation Method of forming a low cost DRAM cell with self aligned twin tub CMOS devices and a pillar shaped capacitor
US5956583A (en) * 1997-06-30 1999-09-21 Fuller; Robert T. Method for forming complementary wells and self-aligned trench with a single mask
US6054344A (en) * 1998-10-30 2000-04-25 Taiwan Semiconductor Manufacturing Company OTP (open trigger path) latchup scheme using buried-diode for sub-quarter micron transistors
US6599813B2 (en) 2001-06-29 2003-07-29 International Business Machines Corporation Method of forming shallow trench isolation for thin silicon-on-insulator substrates

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5413779A (en) * 1977-07-04 1979-02-01 Toshiba Corp Semiconductor integrated circuit device
DE3133841A1 (de) * 1981-08-27 1983-03-17 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen
JPS5864044A (ja) * 1981-10-14 1983-04-16 Toshiba Corp 半導体装置の製造方法
US4435896A (en) * 1981-12-07 1984-03-13 Bell Telephone Laboratories, Incorporated Method for fabricating complementary field effect transistor devices
NL8105559A (nl) * 1981-12-10 1983-07-01 Philips Nv Werkwijze voor het aanbrengen van een smalle groef in een substraatgebied, in het bijzonder een halfgeleidersubstraatgebied.
US4613885A (en) * 1982-02-01 1986-09-23 Texas Instruments Incorporated High-voltage CMOS process
US4412375A (en) * 1982-06-10 1983-11-01 Intel Corporation Method for fabricating CMOS devices with guardband
DE3314450A1 (de) * 1983-04-21 1984-10-25 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen
JPS604236A (ja) * 1983-06-22 1985-01-10 Nec Corp 半導体装置の製造方法
JPS60198767A (ja) * 1984-03-23 1985-10-08 Hitachi Ltd 半導体集積回路装置
US4692992A (en) * 1986-06-25 1987-09-15 Rca Corporation Method of forming isolation regions in a semiconductor device
US4707455A (en) * 1986-11-26 1987-11-17 General Electric Company Method of fabricating a twin tub CMOS device

Also Published As

Publication number Publication date
DE3780371T2 (de) 1993-03-11
EP0254973B1 (en) 1992-07-15
IT1213457B (it) 1989-12-20
EP0254973A1 (en) 1988-02-03
JPS63107060A (ja) 1988-05-12
JP2706723B2 (ja) 1998-01-28
DE3780371D1 (de) 1992-08-20
US4806501A (en) 1989-02-21

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Legal Events

Date Code Title Description
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970730