IT8520599A0 - Architettura di sistema a piu'processori. - Google Patents

Architettura di sistema a piu'processori.

Info

Publication number
IT8520599A0
IT8520599A0 IT8520599A IT2059985A IT8520599A0 IT 8520599 A0 IT8520599 A0 IT 8520599A0 IT 8520599 A IT8520599 A IT 8520599A IT 2059985 A IT2059985 A IT 2059985A IT 8520599 A0 IT8520599 A0 IT 8520599A0
Authority
IT
Italy
Prior art keywords
system architecture
processor system
processor
architecture
Prior art date
Application number
IT8520599A
Other languages
English (en)
Other versions
IT1184553B (it
Inventor
Claudio Fiacconi
Antonio Franzosi
Original Assignee
Honeywell Inf Systems
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Inf Systems filed Critical Honeywell Inf Systems
Priority to IT20599/85A priority Critical patent/IT1184553B/it
Publication of IT8520599A0 publication Critical patent/IT8520599A0/it
Priority to CA000507547A priority patent/CA1254663A/en
Priority to EP86105844A priority patent/EP0201020B1/en
Priority to DE8686105844T priority patent/DE3687426T2/de
Priority to US06/859,593 priority patent/US4862354A/en
Priority to JP61104584A priority patent/JPS61286961A/ja
Priority to KR1019860003591A priority patent/KR920006616B1/ko
Application granted granted Critical
Publication of IT1184553B publication Critical patent/IT1184553B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Computer And Data Communications (AREA)
IT20599/85A 1985-05-07 1985-05-07 Architettura di sistema a piu' processori IT1184553B (it)

Priority Applications (7)

Application Number Priority Date Filing Date Title
IT20599/85A IT1184553B (it) 1985-05-07 1985-05-07 Architettura di sistema a piu' processori
CA000507547A CA1254663A (en) 1985-05-07 1986-04-25 Multiprocessor system architecture
EP86105844A EP0201020B1 (en) 1985-05-07 1986-04-28 Multiprocessor system architecture
DE8686105844T DE3687426T2 (de) 1985-05-07 1986-04-28 Mehrprozessorsystem-architektur.
US06/859,593 US4862354A (en) 1985-05-07 1986-05-05 Multiprocessor system with interrupt notification and verification unit
JP61104584A JPS61286961A (ja) 1985-05-07 1986-05-07 マイクロプロセツサ・システム・ア−キテクチヤと通信方法
KR1019860003591A KR920006616B1 (ko) 1985-05-07 1986-05-07 멀티프로세서 시스템장치 및 그 통신방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT20599/85A IT1184553B (it) 1985-05-07 1985-05-07 Architettura di sistema a piu' processori

Publications (2)

Publication Number Publication Date
IT8520599A0 true IT8520599A0 (it) 1985-05-07
IT1184553B IT1184553B (it) 1987-10-28

Family

ID=11169369

Family Applications (1)

Application Number Title Priority Date Filing Date
IT20599/85A IT1184553B (it) 1985-05-07 1985-05-07 Architettura di sistema a piu' processori

Country Status (7)

Country Link
US (1) US4862354A (it)
EP (1) EP0201020B1 (it)
JP (1) JPS61286961A (it)
KR (1) KR920006616B1 (it)
CA (1) CA1254663A (it)
DE (1) DE3687426T2 (it)
IT (1) IT1184553B (it)

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US6192418B1 (en) * 1997-06-25 2001-02-20 Unisys Corp. System and method for performing external procedure calls from a client program to a server program while both are operating in a heterogenous computer
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US6591348B1 (en) 1999-09-09 2003-07-08 International Business Machines Corporation Method and system for resolution of transaction collisions to achieve global coherence in a distributed symmetric multiprocessor system
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US6587930B1 (en) * 1999-09-23 2003-07-01 International Business Machines Corporation Method and system for implementing remstat protocol under inclusion and non-inclusion of L1 data in L2 cache to prevent read-read deadlock
US6457085B1 (en) 1999-11-04 2002-09-24 International Business Machines Corporation Method and system for data bus latency reduction using transfer size prediction for split bus designs
US6542949B1 (en) 1999-11-08 2003-04-01 International Business Machines Corporation Method and apparatus for increased performance of a parked data bus in the non-parked direction
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US6529990B1 (en) 1999-11-08 2003-03-04 International Business Machines Corporation Method and apparatus to eliminate failed snoops of transactions caused by bus timing conflicts in a distributed symmetric multiprocessor system
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Also Published As

Publication number Publication date
IT1184553B (it) 1987-10-28
KR860009352A (ko) 1986-12-22
US4862354A (en) 1989-08-29
DE3687426D1 (de) 1993-02-18
EP0201020B1 (en) 1993-01-07
DE3687426T2 (de) 1993-07-29
KR920006616B1 (ko) 1992-08-10
CA1254663A (en) 1989-05-23
EP0201020A2 (en) 1986-12-17
JPS61286961A (ja) 1986-12-17
EP0201020A3 (en) 1989-06-14

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TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970530