IT8024776A0 - CIRCUIT ARRANGEMENT FOR SHIFT OF PULSES. - Google Patents

CIRCUIT ARRANGEMENT FOR SHIFT OF PULSES.

Info

Publication number
IT8024776A0
IT8024776A0 IT8024776A IT2477680A IT8024776A0 IT 8024776 A0 IT8024776 A0 IT 8024776A0 IT 8024776 A IT8024776 A IT 8024776A IT 2477680 A IT2477680 A IT 2477680A IT 8024776 A0 IT8024776 A0 IT 8024776A0
Authority
IT
Italy
Prior art keywords
pulses
shift
circuit arrangement
arrangement
circuit
Prior art date
Application number
IT8024776A
Other languages
Italian (it)
Other versions
IT1132980B (en
Inventor
Gottfried Tschanner
Original Assignee
Siemens Ag Albis
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag Albis filed Critical Siemens Ag Albis
Publication of IT8024776A0 publication Critical patent/IT8024776A0/en
Application granted granted Critical
Publication of IT1132980B publication Critical patent/IT1132980B/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/76—Television signal recording
    • H04N5/91—Television signal processing therefor
    • H04N5/93—Regeneration of the television signal or of selected parts thereof
    • H04N5/95—Time-base error compensation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00058—Variable delay controlled by a digital setting
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00234—Layout of the delay element using circuits having two logic levels
    • H03K2005/00247—Layout of the delay element using circuits having two logic levels using counters

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
IT24776/80A 1979-09-28 1980-09-19 CIRCUITUAL ARRANGEMENT FOR THE MOVEMENT OF PULSES IT1132980B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CH877579A CH646287A5 (en) 1979-09-28 1979-09-28 Circuit for time offset pulses.

Publications (2)

Publication Number Publication Date
IT8024776A0 true IT8024776A0 (en) 1980-09-19
IT1132980B IT1132980B (en) 1986-07-09

Family

ID=4344598

Family Applications (1)

Application Number Title Priority Date Filing Date
IT24776/80A IT1132980B (en) 1979-09-28 1980-09-19 CIRCUITUAL ARRANGEMENT FOR THE MOVEMENT OF PULSES

Country Status (4)

Country Link
EP (1) EP0039330A1 (en)
CH (1) CH646287A5 (en)
IT (1) IT1132980B (en)
WO (1) WO1981000940A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4488297A (en) * 1982-04-05 1984-12-11 Fairchild Camera And Instrument Corp. Programmable deskewing of automatic test equipment
US4458165A (en) * 1983-03-23 1984-07-03 Tektronix, Inc. Programmable delay circuit
US4600945A (en) * 1983-03-31 1986-07-15 Rca Corporation Digital video processing system with raster distortion correction
JPS60143017A (en) * 1983-12-29 1985-07-29 Advantest Corp Clock synchronizing logical device
US4737670A (en) * 1984-11-09 1988-04-12 Lsi Logic Corporation Delay control circuit
JPH0677791A (en) * 1992-08-26 1994-03-18 Nippondenso Co Ltd Delay device, programmable delay line, and oscillator

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2774872A (en) * 1952-12-17 1956-12-18 Bell Telephone Labor Inc Phase shifting circuit
US2960568A (en) * 1958-02-26 1960-11-15 Rca Corp Tape reproducing system
DE1252234B (en) * 1963-10-05
FR2073660A5 (en) * 1969-12-13 1971-10-01 Tokyo Shibaura Electric Co
US3913021A (en) * 1974-04-29 1975-10-14 Ibm High resolution digitally programmable electronic delay for multi-channel operation
DE2520089A1 (en) * 1975-05-06 1976-11-18 Philips Patentverwaltung Pulse generator compensates timing mechanism faults - using shift register counter decoder and logic to assess reference deviations
US4016511A (en) * 1975-12-19 1977-04-05 The United States Of America As Represented By The Secretary Of The Air Force Programmable variable length high speed digital delay line
JPS5927513B2 (en) * 1976-11-05 1984-07-06 日本テレビジヨン工業株式会社 signal generator
US4129867A (en) * 1977-04-28 1978-12-12 Motorola Inc. Multi-pulse modulator for radar transponder
US4104538A (en) * 1977-04-29 1978-08-01 Fairchild Camera And Instrument Corporation Digitally synthesized back-up frequency
US4271483A (en) * 1977-08-04 1981-06-02 Independent Broadcasting Authority Delay circuits

Also Published As

Publication number Publication date
CH646287A5 (en) 1984-11-15
WO1981000940A1 (en) 1981-04-02
IT1132980B (en) 1986-07-09
EP0039330A1 (en) 1981-11-11

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