IT8024284A0 - CIRCUIT ARRANGEMENT SUITABLE FOR MANAGING THE EXCHANGE OF DATA BETWEEN A PAIR OF PROCESSORS, OPERATING ACCORDING TO THE MASTER-SLAVE PRINCIPLE, AND A SUPPORT PROCESSOR. - Google Patents

CIRCUIT ARRANGEMENT SUITABLE FOR MANAGING THE EXCHANGE OF DATA BETWEEN A PAIR OF PROCESSORS, OPERATING ACCORDING TO THE MASTER-SLAVE PRINCIPLE, AND A SUPPORT PROCESSOR.

Info

Publication number
IT8024284A0
IT8024284A0 IT8024284A IT2428480A IT8024284A0 IT 8024284 A0 IT8024284 A0 IT 8024284A0 IT 8024284 A IT8024284 A IT 8024284A IT 2428480 A IT2428480 A IT 2428480A IT 8024284 A0 IT8024284 A0 IT 8024284A0
Authority
IT
Italy
Prior art keywords
managing
processors
master
exchange
pair
Prior art date
Application number
IT8024284A
Other languages
Italian (it)
Other versions
IT1209258B (en
Inventor
Corti Mariagrazia
Landi Mario
Original Assignee
Sits Soc It Telecom Siemens
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sits Soc It Telecom Siemens filed Critical Sits Soc It Telecom Siemens
Priority to IT8024284A priority Critical patent/IT1209258B/en
Publication of IT8024284A0 publication Critical patent/IT8024284A0/en
Priority to FR8113480A priority patent/FR2489556A1/en
Priority to BR8104670A priority patent/BR8104670A/en
Priority to GB8125467A priority patent/GB2084770A/en
Priority to DE19813133715 priority patent/DE3133715A1/en
Application granted granted Critical
Publication of IT1209258B publication Critical patent/IT1209258B/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2097—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements maintaining the standby controller/processing unit updated
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0407—Selecting arrangements for multiplex systems for time-division multiplexing using a stored programme control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2023—Failover techniques
    • G06F11/2025—Failover techniques using centralised failover control functionality

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Software Systems (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Multi Processors (AREA)
  • Hardware Redundancy (AREA)
IT8024284A 1980-08-26 1980-08-26 CIRCUIT PROVISION SUITABLE TO MANAGE THE EXCHANGE OF DATA BETWEEN A COUPLE OF PROCESSORS, OPERATING ACCORDING TO THE MASTER-SLAVE PRINCIPLE, AND A SUPPORT PROCESSOR. IT1209258B (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
IT8024284A IT1209258B (en) 1980-08-26 1980-08-26 CIRCUIT PROVISION SUITABLE TO MANAGE THE EXCHANGE OF DATA BETWEEN A COUPLE OF PROCESSORS, OPERATING ACCORDING TO THE MASTER-SLAVE PRINCIPLE, AND A SUPPORT PROCESSOR.
FR8113480A FR2489556A1 (en) 1980-08-26 1981-07-09 CIRCUIT ARRANGEMENT CAPABLE OF MANAGING THE EXCHANGE OF DATA BETWEEN A COUPLE OF COMPUTERS, OPERATING ACCORDING TO THE MASTER-SERVO PRINCIPLE, AND A SUPPORT COMPUTER
BR8104670A BR8104670A (en) 1980-08-26 1981-07-21 CIRCUIT ARRANGEMENT
GB8125467A GB2084770A (en) 1980-08-26 1981-08-20 Data exchange between a pair of computers operating according to the masterslave principle and a support computer
DE19813133715 DE3133715A1 (en) 1980-08-26 1981-08-26 "CIRCUIT ARRANGEMENT BETWEEN AN AUXILIARY COMPUTER AND A PAIR OF COMPUTERS"

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8024284A IT1209258B (en) 1980-08-26 1980-08-26 CIRCUIT PROVISION SUITABLE TO MANAGE THE EXCHANGE OF DATA BETWEEN A COUPLE OF PROCESSORS, OPERATING ACCORDING TO THE MASTER-SLAVE PRINCIPLE, AND A SUPPORT PROCESSOR.

Publications (2)

Publication Number Publication Date
IT8024284A0 true IT8024284A0 (en) 1980-08-26
IT1209258B IT1209258B (en) 1989-07-16

Family

ID=11212939

Family Applications (1)

Application Number Title Priority Date Filing Date
IT8024284A IT1209258B (en) 1980-08-26 1980-08-26 CIRCUIT PROVISION SUITABLE TO MANAGE THE EXCHANGE OF DATA BETWEEN A COUPLE OF PROCESSORS, OPERATING ACCORDING TO THE MASTER-SLAVE PRINCIPLE, AND A SUPPORT PROCESSOR.

Country Status (5)

Country Link
BR (1) BR8104670A (en)
DE (1) DE3133715A1 (en)
FR (1) FR2489556A1 (en)
GB (1) GB2084770A (en)
IT (1) IT1209258B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1255618B (en) * 1992-09-30 1995-11-09 Sits Soc It Telecom Siemens DUPLICATED CONTROL AND PROCESSING UNIT FOR TELECOMMUNICATIONS EQUIPMENT
DE4241319A1 (en) * 1992-12-09 1994-06-16 Ant Nachrichtentech Computer system
JPH07152788A (en) * 1993-06-28 1995-06-16 At & T Global Inf Solutions Internatl Inc Parallel retrieval method and parallel- processing computer system using said method

Also Published As

Publication number Publication date
GB2084770A (en) 1982-04-15
FR2489556A1 (en) 1982-03-05
DE3133715A1 (en) 1982-04-08
BR8104670A (en) 1982-04-06
IT1209258B (en) 1989-07-16

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