BR8104670A - CIRCUIT ARRANGEMENT - Google Patents

CIRCUIT ARRANGEMENT

Info

Publication number
BR8104670A
BR8104670A BR8104670A BR8104670A BR8104670A BR 8104670 A BR8104670 A BR 8104670A BR 8104670 A BR8104670 A BR 8104670A BR 8104670 A BR8104670 A BR 8104670A BR 8104670 A BR8104670 A BR 8104670A
Authority
BR
Brazil
Prior art keywords
circuit arrangement
arrangement
circuit
Prior art date
Application number
BR8104670A
Other languages
Portuguese (pt)
Inventor
Maria G Corti
Mario Landi
Original Assignee
Italtel Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Italtel Spa filed Critical Italtel Spa
Publication of BR8104670A publication Critical patent/BR8104670A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2097—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements maintaining the standby controller/processing unit updated
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0407—Selecting arrangements for multiplex systems for time-division multiplexing using a stored programme control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2023—Failover techniques
    • G06F11/2025—Failover techniques using centralised failover control functionality
BR8104670A 1980-08-26 1981-07-21 CIRCUIT ARRANGEMENT BR8104670A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8024284A IT1209258B (en) 1980-08-26 1980-08-26 CIRCUIT PROVISION SUITABLE TO MANAGE THE EXCHANGE OF DATA BETWEEN A COUPLE OF PROCESSORS, OPERATING ACCORDING TO THE MASTER-SLAVE PRINCIPLE, AND A SUPPORT PROCESSOR.

Publications (1)

Publication Number Publication Date
BR8104670A true BR8104670A (en) 1982-04-06

Family

ID=11212939

Family Applications (1)

Application Number Title Priority Date Filing Date
BR8104670A BR8104670A (en) 1980-08-26 1981-07-21 CIRCUIT ARRANGEMENT

Country Status (5)

Country Link
BR (1) BR8104670A (en)
DE (1) DE3133715A1 (en)
FR (1) FR2489556A1 (en)
GB (1) GB2084770A (en)
IT (1) IT1209258B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1255618B (en) * 1992-09-30 1995-11-09 Sits Soc It Telecom Siemens DUPLICATED CONTROL AND PROCESSING UNIT FOR TELECOMMUNICATIONS EQUIPMENT
DE4241319A1 (en) * 1992-12-09 1994-06-16 Ant Nachrichtentech Computer system
JPH07152788A (en) * 1993-06-28 1995-06-16 At & T Global Inf Solutions Internatl Inc Parallel retrieval method and parallel- processing computer system using said method

Also Published As

Publication number Publication date
GB2084770A (en) 1982-04-15
IT1209258B (en) 1989-07-16
DE3133715A1 (en) 1982-04-08
IT8024284A0 (en) 1980-08-26
FR2489556A1 (en) 1982-03-05

Similar Documents

Publication Publication Date Title
FI811744L (en) Circuit arrangement
BR8102742A (en) ELECTRONIC SPOLET
BR8107265A (en) ADAPTABLE DECISION LEVEL CIRCUIT
BR8106172A (en) SYNCHRONIZATION CIRCUIT
DK145528C (en) AIM
IT1156136B (en) DEMULTIPLATOR CIRCUIT
BR8102499A (en) CIRCUIT BREAKER
BR8205190A (en) SYNCHRONIZER-SUPERVISOR CIRCUIT
BR8504840A (en) PRE-ACCENTUATION CIRCUIT
BR8108811A (en) MECHANICAL TUNER WITH MICROPHONISM ELIMINATING CIRCUIT
IT1206117B (en) DEMULTIPLATOR CIRCUIT.
FI823709L (en) Circuit arrangement
BR8406677A (en) MULTIPLICATION CIRCUIT
FI811873L (en) Circuit arrangement
BR8002805A (en) LINE CIRCUIT
AT383903B (en) CIRCUIT ARRANGEMENT
AR228069A1 (en) SUBSCRIBER CONNECTION CIRCUIT
IT1169233B (en) AMPLIFIER CIRCUIT
BR8103787A (en) SWITCHING CIRCUIT
BR8104634A (en) CIRCUIT ARRANGEMENT
BR8108670A (en) CURRENT LIMITATION CIRCUIT
BR8104534A (en) FREE SWITCHING CIRCUIT
BR8106863A (en) SAFETY CIRCUIT
BR8104670A (en) CIRCUIT ARRANGEMENT
BR8106570A (en) CIRCUIT ARRANGEMENT