GB2084770A - Data exchange between a pair of computers operating according to the masterslave principle and a support computer - Google Patents
Data exchange between a pair of computers operating according to the masterslave principle and a support computer Download PDFInfo
- Publication number
- GB2084770A GB2084770A GB8125467A GB8125467A GB2084770A GB 2084770 A GB2084770 A GB 2084770A GB 8125467 A GB8125467 A GB 8125467A GB 8125467 A GB8125467 A GB 8125467A GB 2084770 A GB2084770 A GB 2084770A
- Authority
- GB
- United Kingdom
- Prior art keywords
- pair
- data
- computers
- output
- register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000004891 communication Methods 0.000 claims abstract description 16
- 230000015654 memory Effects 0.000 claims description 12
- 238000012545 processing Methods 0.000 claims description 8
- 238000012546 transfer Methods 0.000 claims description 7
- 230000004913 activation Effects 0.000 claims description 3
- 101000653235 Homo sapiens Protein-glutamine gamma-glutamyltransferase K Proteins 0.000 abstract description 3
- 102100030944 Protein-glutamine gamma-glutamyltransferase K Human genes 0.000 abstract description 3
- 101100125452 Arabidopsis thaliana ICR1 gene Proteins 0.000 abstract description 2
- 108091006146 Channels Proteins 0.000 description 17
- 238000003745 diagnosis Methods 0.000 description 4
- 101150065817 ROM2 gene Proteins 0.000 description 3
- 101100524639 Toxoplasma gondii ROM3 gene Proteins 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 101001106432 Homo sapiens Rod outer segment membrane protein 1 Proteins 0.000 description 1
- 102100021424 Rod outer segment membrane protein 1 Human genes 0.000 description 1
- 101100467189 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) QCR2 gene Proteins 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/2097—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements maintaining the standby controller/processing unit updated
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/0407—Selecting arrangements for multiplex systems for time-division multiplexing using a stored programme control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
- G06F11/2023—Failover techniques
- G06F11/2025—Failover techniques using centralised failover control functionality
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Software Systems (AREA)
- Computer Networks & Wireless Communication (AREA)
- Hardware Redundancy (AREA)
- Multi Processors (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
A circuit arrangement TCC is provided for data-exchange management between a pair of masterslave computers EL1, EL2 and a support computer ES. The arrangement TCC comprises a first unit IES which interfaces with the support computer ES, second and third units ICR1, ICR2 which interface with the respective remote control units UCR of the pair of computers EL1, EL2, a fourth unit IIO which interfaces with the input-output units I/O of the pair of computers, a microprocessor MIP capable of performing data-exchange management among the above-mentioned interface units, and a "routing" module MIS capable of allocating the communication channel with the fourth interface unit IIO to the input/output unit of either of the pair of computers EL1, EL2 according to predetermined modes. <IMAGE>
Description
SPECIFICATION
Improvements in or relating to circuit arrangements for managing data exchange between a pair of computers operating according to the master-slave principle and a support computer
The present invention relates to a circuit arrangement capable of performing data-exchange management between a pair of computers, provided for example for the control in real time of the switching operations in a digital-type of telephone exchange, and a support computer provided for example to perform operating management of the switching exchange (for instance, maintenance operations, etc.).
In a digital-type of switching telephone exchange, control of the switching operations, in order to ensure a high degree of reliability, is usually assigned to a pair of "special purpose" computers which operate for example, in parallel synchronous fashion according to the master-slave principle.
When the occurrence of a failure is detected in one of the two computers, the faulty computer is taken out of service and diagnosis procedures are performed thereon while the other computer qualifies as "master" and therefore takes command of the peripheral units to continue with the management of the telephone traffic.
According to the invention there is provided a circuit arrangement capable of performing data-exchange management between a support computer and a pair of computers operating according to the master-slave principle, each of which comprises a processing unit which is directly linked to a remote control unit and through a data-bus to an inputoutput unit and a memory unit, the circuit arrangement comprising-a first unit arranged to interface with the support computer;-second and third units arranged to interface with the respective remote control units of the pair of computers;-a fourth unit arranged to interface with the input-output units of the pair of computers;-a microprocessor arranged to perform signal-exchange management among the interface units; and-a "routing" module arranged to allocate the communication channel with the fourth interface unit to the input-output units of the one of the pair of computers selected according to predetermined modes.
Providing the pair of computers can exchange data with the support computer via the input-output elements as well as through remote-control elemtnts, it is possible to provide a particularly simple and economically feasible circuit arrangement, capable of performing data-exchange management between the support computer and the pair of computers through the input-output elements as well as through the remote control elements. In view of the fact that the support computer is linked to the input-output elements of the pair of main computers through a single communication channel, the circuit arrangement is capable of allocating the communication channel to a computer of the said pair according to preset modes.
The invention will be further described, by way of example, with reference to the accompanying drawings, wherein:
Figure 1 is a block-diagram of processing units and of a circuit arrangement contributing a prefered embodiment of the invention;
Figure 2 is a block-diagram of a microprocessor and of interface units of the arrangement of Fig. 1.
Figure 3 shows in detail a "routing" module of the arrangement of Fig. 1.
In Fig. 1, EL, and EL2 indicate a pair of computers allocated for example to command the switching operations in a digital type of telephone exchange, while ES indicates a support computer. Each computer of the pair EL, and EL2 includes a central processing unit
UCE to which a memory array MEM and input-output devices L/O are linked.
A processing array of the type described may exchange data with the outside enviroment through the input-output devices l/O or through a remote-control unit UCR directly connected to the central processing unit UCE.
The Unit UCR is capable of carrying out, upon command given by the support computer ES, the same functions performed by an operator by means of a control board QC.
The circuit arrangement constituting a prefered embodiment of the invention is indicated by TCC and comprises a microprocessor MIP which is linked to the support computer ES through a respective interface unit IES and to the remote-control units UCR of the two computers EL1 and EL2 through respective interface units ICR1, ICR2. The microprocessor MIP is further linked to the input-output devices l/O of the pair of computers EL through an interface unit 110 and a "routing" module
MIS which is provided for the allocation of the channel communicating with the computer ES to a computer of the pair according to modes which will be described hereinafter.
The microprocessor MIP is capable of performing signal exchange among the aforesaid computers by means of a pair of the interface units as shown in detail in Fig. 2.
The microprocessor MIP comprises a databus to which are connected: a central processing unit CPU, a memory array MM and a unit
DMA for direct transfer of data in the memory. To the data-bus are also connected the aforesaid interface units which form peripheral units for microprocessor MIP.
The interface unit IES for the service computer ES comprises a register RG1, having a 1 6-bit storage capacity, which receives the bits in series from the computer ES and performs a series-parallel/conversation. The output of the register RG, is connected to the first input of a multiplexer MT1, the output of which is connected to a second register RG2, also having a 1 6-bit storage capacity and being connected to the data-bus. The contents of the register RG2 are read by the microprocessor MIP by means of two separate readout operations.
Data-transfer from the microprocessor MIP to the computer ES is also performed by means of the multiplexer MT, to the output of which is also connected a third register RG, in which are transferred 16 bits with two different writing operations. The register therefore performs a parallel-series conversion so as to send to the computer ES 1 6-bit packages.
The provision of two separate registers RG and RG3 at the input and output of the computer ES enables the data reception/ transmission operations from/towards the computer ES to overlap.
Interface unit 110 for the input/output elements of the computers EL basically comprises a fourth register RG4, by means of which data-transfer at the output of microprocessor MIP is performed, and of a fifth register RG5 by means of which data-transfer at the input of microprocessor MIP is performed.
The register RG4 comprises three sections, each of which has an 8-bit storage capacity, and which are sequentially enabled for datawriting so as to make up 24-bit packages which are sent in series to the computer EL.
The register RG5 also comprises three sections each of which has an 8-bit storage capacity, so as to be capable of receiving in series a 24-bit package. The outputs of the three sections are connected to an equal number of input groups of a multiplexer MT2 which forwards in sequence on the data-bus of the microprocessor MIP, 8-bit packages in parallel. As in the previous case, the unit 110 is capable of a simultaneously performing a bidirectional data-exchange.
The units ICR, and ICR2 are identical to each other, so that Fig. 2 shows only one such unit ICR which comprises a pair of registers RG6 and RG7, each of which has an 8-bit storage capacity. The registers RG6 and
RG7 receive and send data in parallel. One register of the pair enables data-exchange in one direction to be obtained while the other register enables simultaneous data-exchange in the other direction to be obtained.
Fig. 3 shows in detail the "routing" module
MIS which receives as it inputs the following signals: signals rc1, rc2 sent by the computers
EL1, EL2, respectively, to request the exclusive use of the channel communicating with the computer ES; signals ms, and ms,, ms2 and ms2 sent the computers EL1, EL2, respectively, in a redundant manner on two outputs, which, if no failures occur, are the logic
complement of each other.Supposing for ex
ample that, at a given moment, the computer Eel, is featured as master, then the signals ms
are congruent when the the signals ms, and
ms2 are active and the signals ms, and ms2
are not active; and signals rt1, rt2 which are
activated according to information associated
with the same messages emitted by the ser
vice computer ES and expressing the destina
tion of a given data package. The computer
ES, upon emission of a data package, associ
ates to the package a label expressing the
indication of computer EL to which the data
package is allocated (for instance to the unit
I/O of EL1, or the unit UCR2, etc.).
For the management of the data-stream
coming from the computer EL and going to
the computer ES, unit MIS is capable of
allocating the communication channel to one
of the two computers EL according to the
logic level of signals rc and ms. The allocation
of a channel to a given computer EL causes
actuation by the unit MIS of a signal np
which is intended for the other computer of
the pair of computers to notify the same of
the unavailability of the communication chan
nel. If, for example, the computer EL1 has
activated signal rc, and at the same time
signal ms1 is active, the unit MIS allocates the
communication channel to the computer EL,
and does not activate signal np1 but activates
signal np2 so as to inform the computer EL2 of
the unavailability of the channel.
The unit MIS is also capable of detecting
the presence of incongruities in the aforesaid
signals ms and, when the findings are posi
tive, it activates a signal mse, or mse2 accord
ing to whether the incongruity is detected on
signals ms emitted by EL1 or EL2.
For the management of data4low coming
from the computer ES and going to the com
puter EL, if no request for exclusive use has
been activated, the communication channel is
allocated to both computers EL so that data is
sent by the arrangement TCC to both comput
ers EL.
In the case where at least one signal rc is
active, the unit MIS arranges the allocation of
the channel according to the logic level of
signals ms and according to the logic level
that the aforesaid pair of signals It presents.
The signals ms are supplied to a first read
only memory ROM1 the output binary configu
rations of which address second and third
read-only memories ROM2 and ROM3. The
memory ROM2 is like-wise addressed by the
channel-request bits which are stored in a
register RG8, whereas the memory ROM3 is
like-wise addressed by the bits It which are
stored in a register RGg.
The output of the memory ROMs is con
nected to a register RG10 capable of storing
the state of active bits mse when an incongru
ity is detected in the bits ms and also capable of storing the state of the bits np, activeation of one of which expresses the unavailability of the communication channel for the computer to which the active bit is allocated. The output of the memory ROM2 is likewise connected to a second register RG11 provided to store bits ai designed to enable elemants (driver receiver not shown) by means of which the conversation the input of the arrangement TCC takes place. Activation of a pair of signals as three fore, allows signals to be received from the computer EL whose signal-transmission elements are enabled.
The output of the memory ROM, is connected to a further register RG,2 for storing bits ao designed to enable elements (driverreceiver not shown) by means of which the conversation at the output of arrangement
TCC takes place. Activation of a pair of signals ao therefore allows signals to be sent to the computer EL whose signal-reception elements are enabled.
The registers RGro, RG and RG,2 store the signals present at their inputs when the signal corresponding to the output of a first OR gate
OR is connected to the registers via an AND gate P which is disabled by a signal en, or by a signal en2 active during the transfer of an input-datum or output-datum, respectively, at the arrangement TCC. In this way, modification of the enabling performance of the signal transmission/reception elements (driver-receiver) during the course of a data-transferoperation, is inhibited.
A circuit structure of the type described is capeable of enabling data exchange between the computers EL and the computer ES according to two different operating modes: mode (a): the conversation takes place while the computers EL are synchronous. The arrangement TCC sends data to both computers
EL whereas it ignores data coming from the slave section; mode (b): the conversation takes place with both computers EL operating in an asynchronous manner. The communication channel is allocated to one or the other of the computers EL upon request made thereby.
The asynchronous type of operating mode enables the computer ES to perform management of data relating to the telephone traffic, in co-operation with the master computer EL, as well as the management of diagnosis of failures present in the slave computer EL.
Supposing, for example, that the computer
EL2 is featured as master, and that it has ended data-exchange relating to the telephone traffic with the computer ES, and supposing likewise that the computer EL, suffers from malfunctioning to such an extent as to require initiation of the diagnosis procedure. In such a case, the computer EL1 sends a signal rc, which is detected by arrangement TCC which allocates to it the communication channel with the computer ES by simultaneously sending the signal np2 to the computer EL2. The computer ES thus transfers to the computer
EL, the aforesaid diagnosis programmes.
If the computer EL2 must, once again exchange data relating to the telephone traffic with the computer ES, it sets to zero the signal np2 and sends the signal rc2. The arrangement TCC, in view of the fact that the computer EL2 is featured as master, once again allocates to it the communication channel with the computer ES by simultaneously sending the signal np,.
The arrangement TCC is therefore capable of managing the allocation of the communication channel to computers EL.
Claims (9)
1. A circuit arrangement capable of performing data-exchange management between a support computer and a pair of computers operating according to the master-slave principle, each of which comprises a processing unit which is directly linked to a remote control unit and through a data-bus to an input-output unit and a memory unit, the circuit arrangement comprising a first unit arranged to interface with the support computer; second and third units arranged to interface with the respective remote control units of the pair of computers; a fourth unit arranged to interface with the input-output units of the pair of computers; a microprocessor arranged to perform signal-exchange/ management among the interface units; and a "routing' module arranged allocate the communication channel with the fourth interface unit to the input-output units of one of the pair of computers selected according to predetermined modes.
2. A circuit arrangement as claimed in claim 1, in which the first interface unit comprises: a first register arranged to receive in series a package of bits; a first multiplexer arranged to receive on a first group of inputs the outputs of the first register and having a second group of inputs connected to a databus of the microprocessor; second register the input of which is connected to the output of the first multiplexer and the output of which is connected to the data-bus of the microprocessor; and a third register the input of which is connected to the output of the first multiplexer and which is arranged to forward in series data to the support computer.
3. A circuit arrangement as claimed in claim 1 or 2, in which the fourth unit comprises: a fourth register arranged to receive in parallel data from the data-bus of the microprocessor and to sending the data in series to the "routing" module; a fifth register arranged to receive in series data sent by the "routing" module subdivided into a plurality of sections; and a second mutliplexer having a number of input groups equal to the number of sections of the fifth register and an output connected to the data-bus of the microprocessor.
4. A circuit arrangement as claimed in any one of the preceding claims, in which each of the second and third interface units comprises sixth and seventh registers arranged to send or receive data in paralel to or from a respective remote-control unit and to receive or send data in parallel from or to the data-bus of microprocessor.
5. A circuit arrangement as claimed in any one of the preceding claims, in which the "routing" module comprises a first read-onlymemory arranged to receive at its input signals and complements thereof expressing the master-slave state of the pair of computers; a second read-only-memory arranged to receive at its input the outputs of the first read-onlymemory and the outputs of an eighth register which is arranged to receive signals sent by the pair of computers to request the exclusive use of the communication channel with the support computer; a third read-only-memory arranged to receive at its input the outputs of the first read-only-memory (ROM1) and the outputs of a nineth register which is arranged to receive signals derived by label bits associated with messages sent by the support computer and expressing the destination of a given message; a tenth register connected to the output of the second read-only-memory and arranged to store a pair of bits expressing the presence of incongruities on the masterslave bits sent by the pair of computers and to store a second pair of bits the activation of one of which expresses the unavailability of the communication channel for computer of the pair of computers to which it is allocated; an eleventh register connected to the output of the second read-only-memory and arranged to store bits for enabling transmission-reception elements by means of which data is received; and a twelfth register connected to the output of the third read-only-memory and arranged to store bits for enabling transmission-reception elements by means of which data is emitted.
6. A circuit arrangement as claimed in claim 5, in which the tenth, eleventh and twelfth registers are arranged to be enabled to store data when the output of a gate circuit is active, the gate circuit being arranged to be disabled by a pair of signals which are active during the course of data-transfer in input or in output and having an input connected to the output of an OR gate arranged to receive timing signals from the pair of computers.
7. A circuit arrangement substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.
8. A data processing system including a pair of computers operating according to the master-slave principle, a support computer, and a circuit arrangement as claimed in any one of the preceding claims.
9. A telecommunication switching exchange including a system as claimed in claim 8.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT8024284A IT1209258B (en) | 1980-08-26 | 1980-08-26 | CIRCUIT PROVISION SUITABLE TO MANAGE THE EXCHANGE OF DATA BETWEEN A COUPLE OF PROCESSORS, OPERATING ACCORDING TO THE MASTER-SLAVE PRINCIPLE, AND A SUPPORT PROCESSOR. |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB2084770A true GB2084770A (en) | 1982-04-15 |
Family
ID=11212939
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8125467A Withdrawn GB2084770A (en) | 1980-08-26 | 1981-08-20 | Data exchange between a pair of computers operating according to the masterslave principle and a support computer |
Country Status (5)
| Country | Link |
|---|---|
| BR (1) | BR8104670A (en) |
| DE (1) | DE3133715A1 (en) |
| FR (1) | FR2489556A1 (en) |
| GB (1) | GB2084770A (en) |
| IT (1) | IT1209258B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1994008292A1 (en) * | 1992-09-30 | 1994-04-14 | Siemens Telecomunicazioni S.P.A. | Duplicate control and processing unit for telecommunications equipment |
| EP0601424A2 (en) * | 1992-12-09 | 1994-06-15 | Robert Bosch Gmbh | Computer system |
| US5689631A (en) * | 1993-06-28 | 1997-11-18 | Ncr Corporation | Parallel processing computer and method of solving a problem using simultaneously executed different and competing procedures |
-
1980
- 1980-08-26 IT IT8024284A patent/IT1209258B/en active
-
1981
- 1981-07-09 FR FR8113480A patent/FR2489556A1/en not_active Withdrawn
- 1981-07-21 BR BR8104670A patent/BR8104670A/en unknown
- 1981-08-20 GB GB8125467A patent/GB2084770A/en not_active Withdrawn
- 1981-08-26 DE DE19813133715 patent/DE3133715A1/en not_active Withdrawn
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1994008292A1 (en) * | 1992-09-30 | 1994-04-14 | Siemens Telecomunicazioni S.P.A. | Duplicate control and processing unit for telecommunications equipment |
| EP0601424A2 (en) * | 1992-12-09 | 1994-06-15 | Robert Bosch Gmbh | Computer system |
| EP0601424A3 (en) * | 1992-12-09 | 1995-03-29 | Ant Nachrichtentech | Computer system. |
| US5689631A (en) * | 1993-06-28 | 1997-11-18 | Ncr Corporation | Parallel processing computer and method of solving a problem using simultaneously executed different and competing procedures |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2489556A1 (en) | 1982-03-05 |
| IT1209258B (en) | 1989-07-16 |
| IT8024284A0 (en) | 1980-08-26 |
| BR8104670A (en) | 1982-04-06 |
| DE3133715A1 (en) | 1982-04-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4695952A (en) | Dual redundant bus interface circuit architecture | |
| CA1083726A (en) | System and method for sharing memory | |
| US5761534A (en) | System for arbitrating packetized data from the network to the peripheral resources and prioritizing the dispatching of packets onto the network | |
| US5467452A (en) | Routing control information via a bus selectively controls whether data should be routed through a switch or a bus according to number of destination processors | |
| US5848367A (en) | System and method for sharing a non-volatile memory element as a boot device | |
| US4814974A (en) | Programmable memory-based arbitration system for implementing fixed and flexible priority arrangements | |
| US4280193A (en) | Data link processor for magnetic tape data transfer system | |
| US4115854A (en) | Channel bus controller | |
| US4322792A (en) | Common front-end control for a peripheral controller connected to a computer | |
| US4293928A (en) | Peripheral dependent circuit for peripheral controller | |
| NO169039B (en) | PROCEDURE FOR AA OPERATING A COMMAND PROCESSOR TO AA CONTROL A COMMUNICATION SWITCH, AND COMMAND PROCESSOR FOR IMPLEMENTING THE PROCEDURE | |
| US4509140A (en) | Data transmitting link | |
| US4628478A (en) | Remote data controller for a communication system | |
| GB2286750A (en) | Configuring functional units in a serial master-slave arrangement | |
| US3539998A (en) | Communications system and remote scanner and control units | |
| US4453213A (en) | Error reporting scheme | |
| US3804987A (en) | Multiplexing apparatus having interlaced and/or parallel data transfer with a data processor and communication lines | |
| US5245705A (en) | Functional addressing method and apparatus for a multiplexed data bus | |
| EP0097028A2 (en) | Multiple-microcomputer communications system | |
| EP0658998B1 (en) | Data switching apparatus | |
| GB2084770A (en) | Data exchange between a pair of computers operating according to the masterslave principle and a support computer | |
| EP0103335A2 (en) | Circuit arrangement for the exchange of messages within a telecommunication system consisting of a plurality of modular units | |
| US5530904A (en) | System for tranferring data from one communication line to another using a multiplexer for selecting the lines and transferring data without intervention of a main processor | |
| KR100209458B1 (en) | Method and circuit arrangement for managing uniform unities and switch element | |
| US6360290B1 (en) | Commercial standard digital bus interface circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |