IT8022606A0 - Struttura per l'indirizzamento implicito e l'accesso a dispositivi di memorizzazione. - Google Patents

Struttura per l'indirizzamento implicito e l'accesso a dispositivi di memorizzazione.

Info

Publication number
IT8022606A0
IT8022606A0 IT8022606A IT2260680A IT8022606A0 IT 8022606 A0 IT8022606 A0 IT 8022606A0 IT 8022606 A IT8022606 A IT 8022606A IT 2260680 A IT2260680 A IT 2260680A IT 8022606 A0 IT8022606 A0 IT 8022606A0
Authority
IT
Italy
Prior art keywords
access
storage devices
implicit addressing
implicit
addressing
Prior art date
Application number
IT8022606A
Other languages
English (en)
Other versions
IT1151066B (it
Inventor
Herbert Schorr
Irving Wladawsky-Berger
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of IT8022606A0 publication Critical patent/IT8022606A0/it
Application granted granted Critical
Publication of IT1151066B publication Critical patent/IT1151066B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30138—Extension of register space, e.g. register cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30101—Special purpose registers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30163—Decoding the operand specifier, e.g. specifier format with implied specifier, e.g. top of stack
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/35—Indirect addressing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Executing Machine-Instructions (AREA)
IT22606/80A 1979-06-29 1980-06-06 Struttura per l'indirizzamento implicito e l'accesso a dispositivi di memorizzazione IT1151066B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/053,658 US4280177A (en) 1979-06-29 1979-06-29 Implicit address structure and method for accessing an associative memory device

Publications (2)

Publication Number Publication Date
IT8022606A0 true IT8022606A0 (it) 1980-06-06
IT1151066B IT1151066B (it) 1986-12-17

Family

ID=21985734

Family Applications (1)

Application Number Title Priority Date Filing Date
IT22606/80A IT1151066B (it) 1979-06-29 1980-06-06 Struttura per l'indirizzamento implicito e l'accesso a dispositivi di memorizzazione

Country Status (5)

Country Link
US (1) US4280177A (it)
EP (1) EP0021097B1 (it)
JP (1) JPS5927995B2 (it)
DE (1) DE3072186D1 (it)
IT (1) IT1151066B (it)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4574349A (en) * 1981-03-30 1986-03-04 International Business Machines Corp. Apparatus for addressing a larger number of instruction addressable central processor registers than can be identified by a program instruction
US4652995A (en) * 1982-09-27 1987-03-24 Data General Corporation Encachement apparatus using multiple caches for providing multiple component values to form data items
US4799149A (en) * 1983-03-30 1989-01-17 Siemens Aktiengesellschaft Hybrid associative memory composed of a non-associative basic storage and an associative surface, as well as method for searching and sorting data stored in such a hybrid associative memory
JPS6095651A (ja) * 1983-10-31 1985-05-29 Toshiba Corp 記憶装置
US4587610A (en) * 1984-02-10 1986-05-06 Prime Computer, Inc. Address translation systems for high speed computer memories
US4757447A (en) * 1986-07-28 1988-07-12 Amdahl Corporation Virtual memory system having identity marking for common address space
JPH0348951A (ja) * 1989-07-18 1991-03-01 Fujitsu Ltd アドレスモニタ装置
US6292845B1 (en) * 1998-08-26 2001-09-18 Infineon Technologies North America Corp. Processing unit having independent execution units for parallel execution of instructions of different category with instructions having specific bits indicating instruction size and category respectively
US7114056B2 (en) 1998-12-03 2006-09-26 Sun Microsystems, Inc. Local and global register partitioning in a VLIW processor
US7117342B2 (en) * 1998-12-03 2006-10-03 Sun Microsystems, Inc. Implicitly derived register specifiers in a processor
JP6235844B2 (ja) 2012-09-20 2017-11-22 花王株式会社 皮膚又は毛髪用洗浄剤組成物
JP6224390B2 (ja) 2012-09-20 2017-11-01 花王株式会社 内部オレフィンスルホン酸塩組成物及びこれを含有する洗浄剤組成物

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3685020A (en) * 1970-05-25 1972-08-15 Cogar Corp Compound and multilevel memories
US3764996A (en) * 1971-12-23 1973-10-09 Ibm Storage control and address translation
US3800286A (en) * 1972-08-24 1974-03-26 Honeywell Inf Systems Address development technique utilizing a content addressable memory
US3825904A (en) * 1973-06-08 1974-07-23 Ibm Virtual memory system
US3840862A (en) * 1973-09-27 1974-10-08 Honeywell Inf Systems Status indicator apparatus for tag directory in associative stores
US3949369A (en) * 1974-01-23 1976-04-06 Data General Corporation Memory access technique
US3938097A (en) * 1974-04-01 1976-02-10 Xerox Corporation Memory and buffer arrangement for digital computers
US4070706A (en) * 1976-09-20 1978-01-24 Sperry Rand Corporation Parallel requestor priority determination and requestor address matching in a cache memory system
US4084226A (en) * 1976-09-24 1978-04-11 Sperry Rand Corporation Virtual address translator
US4141067A (en) * 1977-06-13 1979-02-20 General Automation Multiprocessor system with cache memory

Also Published As

Publication number Publication date
EP0021097A2 (en) 1981-01-07
EP0021097A3 (en) 1981-09-23
JPS5927995B2 (ja) 1984-07-10
JPS567284A (en) 1981-01-24
EP0021097B1 (en) 1991-01-09
DE3072186D1 (de) 1991-02-14
US4280177A (en) 1981-07-21
IT1151066B (it) 1986-12-17

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