IT8021992A0 - Sistema di interruzione impiegante un microelaboratore a pre-recupero delle istruzioni. - Google Patents

Sistema di interruzione impiegante un microelaboratore a pre-recupero delle istruzioni.

Info

Publication number
IT8021992A0
IT8021992A0 IT8021992A IT2199280A IT8021992A0 IT 8021992 A0 IT8021992 A0 IT 8021992A0 IT 8021992 A IT8021992 A IT 8021992A IT 2199280 A IT2199280 A IT 2199280A IT 8021992 A0 IT8021992 A0 IT 8021992A0
Authority
IT
Italy
Prior art keywords
recover
microprocessor
instructions
interruption system
interruption
Prior art date
Application number
IT8021992A
Other languages
English (en)
Other versions
IT1148827B (it
Inventor
Floyd Russell Bliss
Peter Tappen Fairchild
Joel Calvin Leininger
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of IT8021992A0 publication Critical patent/IT8021992A0/it
Application granted granted Critical
Publication of IT1148827B publication Critical patent/IT1148827B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
IT21992/80A 1979-06-21 1980-05-13 Sistema di interruzione impiegante un microelaboratore a pre-recupero delle istruzioni IT1148827B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/050,888 US4279016A (en) 1979-06-21 1979-06-21 Instruction pre-fetch microprocessor interrupt system

Publications (2)

Publication Number Publication Date
IT8021992A0 true IT8021992A0 (it) 1980-05-13
IT1148827B IT1148827B (it) 1986-12-03

Family

ID=21968099

Family Applications (1)

Application Number Title Priority Date Filing Date
IT21992/80A IT1148827B (it) 1979-06-21 1980-05-13 Sistema di interruzione impiegante un microelaboratore a pre-recupero delle istruzioni

Country Status (4)

Country Link
US (1) US4279016A (it)
JP (1) JPS5918738B2 (it)
BR (1) BR8003879A (it)
IT (1) IT1148827B (it)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56129950A (en) * 1980-03-07 1981-10-12 Hitachi Ltd Information processor
US4498136A (en) * 1982-12-15 1985-02-05 Ibm Corporation Interrupt processor
US4766533A (en) * 1984-03-09 1988-08-23 The United States Of America As Represented By The United States National Aeronautics And Space Administration Nanosequencer digital logic controller
US4654786A (en) * 1984-04-11 1987-03-31 Texas Instruments Incorporated Data processor using picosquencer to control execution of multi-instruction subroutines in a single fetch cycle
US4794517A (en) * 1985-04-15 1988-12-27 International Business Machines Corporation Three phased pipelined signal processor
US4791557A (en) * 1985-07-31 1988-12-13 Wang Laboratories, Inc. Apparatus and method for monitoring and controlling the prefetching of instructions by an information processing system
JPH0126769Y2 (it) * 1985-10-06 1989-08-10
JPH0740225B2 (ja) * 1985-12-25 1995-05-01 日本電気株式会社 プログラムスキツプ動作制御方式
US4991090A (en) * 1987-05-18 1991-02-05 International Business Machines Corporation Posting out-of-sequence fetches
KR940001878B1 (ko) * 1990-03-08 1994-03-10 가부시끼가이샤 히다찌세이사꾸쇼 멀티 프로세서시스템 및 인터럽션 제어장치
US5809309A (en) * 1990-09-28 1998-09-15 Texas Instruments Incorporated Processing devices with look-ahead instruction systems and methods
US6052801A (en) * 1995-05-10 2000-04-18 Intel Corporation Method and apparatus for providing breakpoints on a selectable address range
US5659679A (en) * 1995-05-30 1997-08-19 Intel Corporation Method and apparatus for providing breakpoints on taken jumps and for providing software profiling in a computer system
US5740413A (en) * 1995-06-19 1998-04-14 Intel Corporation Method and apparatus for providing address breakpoints, branch breakpoints, and single stepping
US5621886A (en) * 1995-06-19 1997-04-15 Intel Corporation Method and apparatus for providing efficient software debugging
US5778221A (en) * 1997-03-17 1998-07-07 International Business Machines Corporation System for executing asynchronous branch and link in parallel processor
WO2004046924A1 (en) * 2002-11-18 2004-06-03 Arm Limited Processor switching between secure and non-secure modes
WO2004046925A1 (en) 2002-11-18 2004-06-03 Arm Limited Security mode switching via an exception vector
US20170277539A1 (en) * 2016-03-24 2017-09-28 Imagination Technologies Limited Exception handling in processor using branch delay slot instruction set architecture

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3453600A (en) * 1966-08-18 1969-07-01 Ibm Program suspension system
US3811114A (en) * 1973-01-11 1974-05-14 Honeywell Inf Systems Data processing system having an improved overlap instruction fetch and instruction execution feature
GB1426749A (en) * 1973-06-05 1976-03-03 Burroughs Corp Micro programme data processor having parallel instruction flow streams for plural level of subinstruction sets
US4050058A (en) * 1973-12-26 1977-09-20 Xerox Corporation Microprocessor with parallel operation
JPS51138356A (en) * 1975-05-26 1976-11-29 Mitsubishi Electric Corp Priority interruption control circuit
US4062058A (en) * 1976-02-13 1977-12-06 The United States Of America As Represented By The Secretary Of The Navy Next address subprocessor
US4041462A (en) * 1976-04-30 1977-08-09 International Business Machines Corporation Data processing system featuring subroutine linkage operations using hardware controlled stacks
JPS5318933A (en) * 1976-08-06 1978-02-21 Fujitsu Ltd Execution method of interruptable order
US4079455A (en) * 1976-12-13 1978-03-14 Rca Corporation Microprocessor architecture
US4097920A (en) * 1976-12-13 1978-06-27 Rca Corporation Hardware control for repeating program loops in electronic computers

Also Published As

Publication number Publication date
JPS564846A (en) 1981-01-19
JPS5918738B2 (ja) 1984-04-28
BR8003879A (pt) 1981-01-13
IT1148827B (it) 1986-12-03
US4279016A (en) 1981-07-14

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